From 72024cbd38f5da862943fd758e753ba7b0e4892e Mon Sep 17 00:00:00 2001
From: Murali Nalajala <mnalajal@quicinc.com>
Date: Mon, 29 Jul 2019 14:01:39 -0700
Subject: [PATCH] dt-bindings: kryo-edac: add kryo edac bindings

Add kryo edac device bindings. These devices can be used
to report various cache errors.

Change-Id: I908e6d935c344bb36a752a8c44db85fdb68f525a
---
 bindings/edac/kryo-edac.yaml | 52 ++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 bindings/edac/kryo-edac.yaml

diff --git a/bindings/edac/kryo-edac.yaml b/bindings/edac/kryo-edac.yaml
new file mode 100644
index 000000000000..bcc5f7275eac
--- /dev/null
+++ b/bindings/edac/kryo-edac.yaml
@@ -0,0 +1,52 @@
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/edac/kryo-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kryo EDAC(Error Detection and Correction) node binding
+
+maintainers:
+  - Murali Nalajala <mnalajal@quicinc.com>
+
+description: |+
+  Kryo EDAC node is defined to describe on-chip error detection and correction
+  for the Kryo core.
+
+  Kryo will report all SBE and DBE found in L1/L2/L3/SCU caches in two registers:
+    ERRXSTATUS - Error Record Primary Status Register
+    ERRXMISC0 - Error Record Miscellaneous Register
+
+  Current implementation of Kryo ECC mechanism is based on interrupts.
+  The following section describes the DT node binding for kryo_cpu_erp.
+
+properties:
+  compatible:
+      const: arm,arm64-kryo-cpu-erp
+      description:
+        Implements cache error detection and correction for Kryo CPUs.
+
+  interrupts:
+    description: Interrupt-specifier for L1/L2, L3/SCU error IRQ(s)
+
+  interrupt-names:
+    description: Descriptive names of the interrupts
+
+required:
+  - compatible
+  - interrupts
+  - interrupt-names
+
+examples:
+  - |
+    kryo-erp {
+      compatible = "arm,arm64-kryo-cpu-erp";
+      interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
+        <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
+        <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+        <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+
+      interrupt-names = "l1-l2-faultirq",
+          "l1-l2-errirq",
+          "l3-scu-errirq",
+          "l3-scu-faultirq";
+    };