mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
Merge branch 'pci/host-layerscape' into next
* pci/host-layerscape: PCI: layerscape: Add ls_pcie_msi_host_init() PCI: layerscape: Add support for LS1043a and LS2080a PCI: layerscape: Remove unused fields from struct ls_pcie PCI: layerscape: Update ls_add_pcie_port() PCI: layerscape: Factor out SCFG related function PCI: layerscape: Ignore PCIe controllers in Endpoint mode PCI: layerscape: Remove ls_pcie_establish_link()
This commit is contained in:
Bjorn Helgaas
commit
7225107e15
3 changed files with 161 additions and 54 deletions
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@ -107,7 +107,7 @@ config PCI_XGENE_MSI
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config PCI_LAYERSCAPE
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bool "Freescale Layerscape PCIe controller"
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depends on OF && ARM
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depends on OF && (ARM || ARCH_LAYERSCAPE)
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select PCIE_DW
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select MFD_SYSCON
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help
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2014 Freescale Semiconductor.
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*
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* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
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* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -11,7 +11,6 @@
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of_pci.h>
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@ -32,27 +31,60 @@
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#define LTSSM_STATE_MASK 0x3f
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#define LTSSM_PCIE_L0 0x11 /* L0 state */
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/* Symbol Timer Register and Filter Mask Register 1 */
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#define PCIE_STRFMR1 0x71c
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/* PEX Internal Configuration Registers */
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
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#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
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/* PEX LUT registers */
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#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
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struct ls_pcie_drvdata {
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u32 lut_offset;
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u32 ltssm_shift;
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struct pcie_host_ops *ops;
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};
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struct ls_pcie {
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struct list_head node;
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struct device *dev;
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struct pci_bus *bus;
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void __iomem *dbi;
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void __iomem *lut;
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struct regmap *scfg;
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struct pcie_port pp;
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const struct ls_pcie_drvdata *drvdata;
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int index;
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int msi_irq;
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};
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#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
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static int ls_pcie_link_up(struct pcie_port *pp)
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static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
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{
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u32 header_type;
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header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE);
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header_type &= 0x7f;
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return header_type == PCI_HEADER_TYPE_BRIDGE;
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}
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/* Clear multi-function bit */
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static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
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{
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iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
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}
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/* Fix class value */
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static void ls_pcie_fix_class(struct ls_pcie *pcie)
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{
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iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
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}
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static int ls1021_pcie_link_up(struct pcie_port *pp)
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{
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u32 state;
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struct ls_pcie *pcie = to_ls_pcie(pp);
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if (!pcie->scfg)
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return 0;
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regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
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state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
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@ -62,27 +94,27 @@ static int ls_pcie_link_up(struct pcie_port *pp)
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return 1;
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}
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static int ls_pcie_establish_link(struct pcie_port *pp)
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{
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unsigned int retries;
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for (retries = 0; retries < 200; retries++) {
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if (dw_pcie_link_up(pp))
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return 0;
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usleep_range(100, 1000);
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}
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dev_err(pp->dev, "phy link never came up\n");
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return -EINVAL;
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}
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static void ls_pcie_host_init(struct pcie_port *pp)
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static void ls1021_pcie_host_init(struct pcie_port *pp)
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{
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struct ls_pcie *pcie = to_ls_pcie(pp);
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u32 val;
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u32 val, index[2];
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pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
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"fsl,pcie-scfg");
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if (IS_ERR(pcie->scfg)) {
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dev_err(pp->dev, "No syscfg phandle specified\n");
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pcie->scfg = NULL;
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return;
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}
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if (of_property_read_u32_array(pp->dev->of_node,
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"fsl,pcie-scfg", index, 2)) {
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pcie->scfg = NULL;
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return;
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}
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pcie->index = index[1];
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dw_pcie_setup_rc(pp);
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ls_pcie_establish_link(pp);
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/*
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* LS1021A Workaround for internal TKT228622
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@ -93,21 +125,97 @@ static void ls_pcie_host_init(struct pcie_port *pp)
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iowrite32(val, pcie->dbi + PCIE_STRFMR1);
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}
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static int ls_pcie_link_up(struct pcie_port *pp)
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{
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struct ls_pcie *pcie = to_ls_pcie(pp);
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u32 state;
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state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
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pcie->drvdata->ltssm_shift) &
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LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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static void ls_pcie_host_init(struct pcie_port *pp)
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{
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struct ls_pcie *pcie = to_ls_pcie(pp);
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iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
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ls_pcie_fix_class(pcie);
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ls_pcie_clear_multifunction(pcie);
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iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
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}
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static int ls_pcie_msi_host_init(struct pcie_port *pp,
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struct msi_controller *chip)
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{
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struct device_node *msi_node;
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struct device_node *np = pp->dev->of_node;
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/*
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* The MSI domain is set by the generic of_msi_configure(). This
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* .msi_host_init() function keeps us from doing the default MSI
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* domain setup in dw_pcie_host_init() and also enforces the
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* requirement that "msi-parent" exists.
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*/
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msi_node = of_parse_phandle(np, "msi-parent", 0);
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if (!msi_node) {
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dev_err(pp->dev, "failed to find msi-parent\n");
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return -EINVAL;
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}
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return 0;
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}
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static struct pcie_host_ops ls1021_pcie_host_ops = {
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.link_up = ls1021_pcie_link_up,
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.host_init = ls1021_pcie_host_init,
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.msi_host_init = ls_pcie_msi_host_init,
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};
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static struct pcie_host_ops ls_pcie_host_ops = {
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.link_up = ls_pcie_link_up,
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.host_init = ls_pcie_host_init,
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.msi_host_init = ls_pcie_msi_host_init,
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};
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static int ls_add_pcie_port(struct ls_pcie *pcie)
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{
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struct pcie_port *pp;
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int ret;
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static struct ls_pcie_drvdata ls1021_drvdata = {
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.ops = &ls1021_pcie_host_ops,
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};
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pp = &pcie->pp;
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pp->dev = pcie->dev;
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static struct ls_pcie_drvdata ls1043_drvdata = {
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.lut_offset = 0x10000,
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.ltssm_shift = 24,
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.ops = &ls_pcie_host_ops,
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};
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static struct ls_pcie_drvdata ls2080_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 0,
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.ops = &ls_pcie_host_ops,
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};
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static const struct of_device_id ls_pcie_of_match[] = {
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{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
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{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
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{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
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static int __init ls_add_pcie_port(struct pcie_port *pp,
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struct platform_device *pdev)
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{
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int ret;
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struct ls_pcie *pcie = to_ls_pcie(pp);
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pp->dev = &pdev->dev;
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pp->dbi_base = pcie->dbi;
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pp->root_bus_nr = -1;
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pp->ops = &ls_pcie_host_ops;
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pp->ops = pcie->drvdata->ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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@ -120,17 +228,19 @@ static int ls_add_pcie_port(struct ls_pcie *pcie)
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static int __init ls_pcie_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct ls_pcie *pcie;
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struct resource *dbi_base;
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u32 index[2];
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int ret;
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match = of_match_device(ls_pcie_of_match, &pdev->dev);
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if (!match)
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return -ENODEV;
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pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie->dev = &pdev->dev;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
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if (IS_ERR(pcie->dbi)) {
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@ -138,20 +248,13 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
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return PTR_ERR(pcie->dbi);
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}
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pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"fsl,pcie-scfg");
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if (IS_ERR(pcie->scfg)) {
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dev_err(&pdev->dev, "No syscfg phandle specified\n");
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return PTR_ERR(pcie->scfg);
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}
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pcie->drvdata = match->data;
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pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
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ret = of_property_read_u32_array(pdev->dev.of_node,
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"fsl,pcie-scfg", index, 2);
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if (ret)
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return ret;
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pcie->index = index[1];
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if (!ls_pcie_is_bridge(pcie))
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return -ENODEV;
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ret = ls_add_pcie_port(pcie);
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ret = ls_add_pcie_port(&pcie->pp, pdev);
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if (ret < 0)
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return ret;
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@ -160,12 +263,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id ls_pcie_of_match[] = {
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{ .compatible = "fsl,ls1021a-pcie" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
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static struct platform_driver ls_pcie_driver = {
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.driver = {
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.name = "layerscape-pcie",
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