From 62b8ede47a33ec1e6155424659d6c13d654011de Mon Sep 17 00:00:00 2001 From: Rohith M Date: Thu, 10 Jun 2021 20:44:48 +0530 Subject: [PATCH 1/6] msm: camera: cpas: Add support for new cpas version Added support for 520_110 CPAS version CRs-Fixed: 2948896 Change-Id: I03ee4e81a33f41d634f6162bc5043e9ad0dc6f1c Signed-off-by: Rohith M --- drivers/cam_cpas/cpas_top/cam_cpastop_hw.c | 7 +- drivers/cam_cpas/cpas_top/cpastop_v520_110.h | 244 +++++++++++++++++++ drivers/cam_cpas/include/cam_cpas_api.h | 1 + 3 files changed, 251 insertions(+), 1 deletion(-) create mode 100644 drivers/cam_cpas/cpas_top/cpastop_v520_110.h diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c index 01a376dd51c1..4baab87eec64 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -27,6 +27,7 @@ #include "cpastop_v580_custom.h" #include "cpastop_v540_100.h" #include "cpastop_v520_100.h" +#include "cpastop_v520_110.h" #include "cpastop_v545_100.h" #include "cpastop_v545_110.h" #include "cpastop_v570_200.h" @@ -101,7 +102,7 @@ static const uint32_t cam_cpas_hw_version_map { CAM_CPAS_TITAN_520_V100, 0, - 0, + CAM_CPAS_TITAN_520_V110, 0, 0, 0, @@ -931,6 +932,10 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, camnoc_info = &cam520_cpas100_camnoc_info; qchannel_info = &cam520_cpas100_qchannel_info; break; + case CAM_CPAS_TITAN_520_V110: + camnoc_info = &cam520_cpas110_camnoc_info; + qchannel_info = &cam520_cpas110_qchannel_info; + break; case CAM_CPAS_TITAN_545_V100: camnoc_info = &cam545_cpas100_camnoc_info; qchannel_info = &cam545_cpas100_qchannel_info; diff --git a/drivers/cam_cpas/cpas_top/cpastop_v520_110.h b/drivers/cam_cpas/cpas_top/cpastop_v520_110.h new file mode 100644 index 000000000000..f1328122e644 --- /dev/null +++ b/drivers/cam_cpas/cpas_top/cpastop_v520_110.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V520_110_H_ +#define _CPASTOP_V520_110_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v520_110_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA40, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + (TEST_IRQ_ENABLE ? + 0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */ + 0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */, + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x3 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v520_110_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + + +static struct cam_camnoc_specific + cam_cpas_v520_110_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE30, /* CDM_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE38, /* CDM_URGENCY_LOW */ + .value = 0x00000003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE40, /* CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE48, /* CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_TFE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x30, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x34, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x38, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x40, /* TFE_DANGERLUT_LOW */ + .value = 0xffff0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x48, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_OPE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* OPE_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* OPE_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x438, /* OPE_URGENCY_LOW */ + .value = 0x00000033, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* OPE_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* OPE_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam520_cpas110_err_logger_offsets = { + .mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_camnoc_info cam520_cpas110_camnoc_info = { + .specific = &cam_cpas_v520_110_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v520_110_camnoc_specific), + .irq_sbm = &cam_cpas_v520_110_irq_sbm, + .irq_err = &cam_cpas_v520_110_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v520_110_irq_err), + .err_logger = &cam520_cpas110_err_logger_offsets, + .errata_wa_list = NULL, +}; + +static struct cam_cpas_camnoc_qchannel cam520_cpas110_qchannel_info = { + .qchannel_ctrl = 0x14, + .qchannel_status = 0x18, +}; +#endif /* _CPASTOP_V520_110_H_ */ diff --git a/drivers/cam_cpas/include/cam_cpas_api.h b/drivers/cam_cpas/include/cam_cpas_api.h index 87fe72a42a64..158b4ba3c5e0 100644 --- a/drivers/cam_cpas/include/cam_cpas_api.h +++ b/drivers/cam_cpas/include/cam_cpas_api.h @@ -138,6 +138,7 @@ enum cam_cpas_hw_version { CAM_CPAS_TITAN_580_V100 = 0x580100, CAM_CPAS_TITAN_540_V100 = 0x540100, CAM_CPAS_TITAN_520_V100 = 0x520100, + CAM_CPAS_TITAN_520_V110 = 0x520110, CAM_CPAS_TITAN_545_V100 = 0x545100, CAM_CPAS_TITAN_545_V110 = 0x545110, CAM_CPAS_TITAN_570_V200 = 0x570200, From b77fca2cb0b85b57b758e574b8db627faf967055 Mon Sep 17 00:00:00 2001 From: Jigarkumar Zala Date: Mon, 14 Jun 2021 10:56:24 -0700 Subject: [PATCH 2/6] msm: camera: csiphy: Continue in case of unavailibility of CSIPHY hw During the common control register programming across csiphy hws, there can be chance that number of CSIPHY hw supported is differnt than max csiphy hw supported among various targets. This change make sure to continue to next available hardware index in case of unavailibility of csiphy hw soc index. CRs-Fixed: 2948896 Change-Id: I1572974226701dcd3aadeb3d9cf95924e05520a9 Signed-off-by: Jigarkumar Zala --- drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 4781285ea46d..210179307a9e 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -153,6 +153,12 @@ static void cam_csiphy_prgm_cmn_data( csiphybase = g_phy_data[csiphy_idx].base_address; is_3phase = g_phy_data[csiphy_idx].is_3phase; + if (!csiphybase) { + CAM_DBG(CAM_CSIPHY, "CSIPHY: %d is not available in platform", + csiphy_idx); + continue; + } + for (i = 0; i < size; i++) { csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_common_reg[i]; From 3273afefe75420434b64a356ba3743292d9d6bfb Mon Sep 17 00:00:00 2001 From: Wyes Karny Date: Tue, 1 Jun 2021 01:03:52 +0530 Subject: [PATCH 3/6] msm: camera: reqmgr: Reset sync mode for sync link in bubble Reset sync link in case of bubble recovery. When dual link is enabled, it is not required to re-apply the sync link request in bubble recovery as the sync link request is already applied and by the time reapply comes request would not be in pending list. Therefore set the sync mode to zero for that index, so that there would not be any dependency on the sync link. CRs-Fixed: 2978526 Change-Id: I327371baecfd6d378cb773bc27c412ba6d2ba42d Signed-off-by: Wyes Karny --- drivers/cam_req_mgr/cam_req_mgr_core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index c7d6e8252b02..beeb2ec07f3a 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -2900,6 +2900,13 @@ int cam_req_mgr_process_error(void *priv, void *data) in_q->rd_idx = idx; in_q->slot[idx].status = CRM_SLOT_STATUS_REQ_ADDED; + if (link->sync_link[0]) { + in_q->slot[idx].sync_mode = 0; + __cam_req_mgr_inc_idx(&idx, 1, + link->req.l_tbl->num_slots); + in_q->slot[idx].sync_mode = 0; + } + /* The next req may also be applied */ idx = in_q->rd_idx; __cam_req_mgr_inc_idx(&idx, 1, From 1666f6b6d481707a4b3b201f8944b2e6182a7eb4 Mon Sep 17 00:00:00 2001 From: zhuo Date: Fri, 9 Jul 2021 14:52:29 +0800 Subject: [PATCH 4/6] msm: camera: common: Change judgement condition Icc_get return value is IS_ERR type, so the commit change the judgement condition. CRs-Fixed: 2988670 Change-Id: I2c3375922bc42b598aa8872c756a47e881ccb80c Signed-off-by: zhuo --- drivers/cam_utils/cam_soc_icc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_utils/cam_soc_icc.c b/drivers/cam_utils/cam_soc_icc.c index c6b405b509c5..707ba5ab790d 100644 --- a/drivers/cam_utils/cam_soc_icc.c +++ b/drivers/cam_utils/cam_soc_icc.c @@ -103,7 +103,7 @@ int cam_soc_bus_client_register(struct platform_device *pdev, bus_client_data->icc_data = icc_get(&pdev->dev, bus_client->common_data->src_id, bus_client->common_data->dst_id); - if (!bus_client_data->icc_data) { + if (IS_ERR_OR_NULL(bus_client_data->icc_data)) { CAM_ERR(CAM_UTIL, "failed in register bus client"); rc = -EINVAL; goto error; From 8df447806563780219602a14ceaf5ee7f8526fd4 Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Thu, 22 Jul 2021 12:16:32 +0530 Subject: [PATCH 5/6] msm: camera: cpas: Enable Priority LUT for Blair OPE This change is to enable priority lut QoS settings in OPE Hw for Blair Camera. CRs-Fixed: 2944976 Change-Id: Icb7b457b96698669a260a589fb445e246a8d100a Signed-off-by: Ayush Kumar --- drivers/cam_cpas/cpas_top/cpastop_v545_110.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cam_cpas/cpas_top/cpastop_v545_110.h b/drivers/cam_cpas/cpas_top/cpastop_v545_110.h index d8833047c250..4a2509507acc 100644 --- a/drivers/cam_cpas/cpas_top/cpastop_v545_110.h +++ b/drivers/cam_cpas/cpas_top/cpastop_v545_110.h @@ -250,14 +250,14 @@ static struct cam_camnoc_specific .port_type = CAM_CAMNOC_OPE, .enable = true, .priority_lut_low = { - .enable = false, + .enable = true, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x430, /* OPE_PRIORITYLUT_LOW */ .value = 0x33333333, }, .priority_lut_high = { - .enable = false, + .enable = true, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x434, /* OPE_PRIORITYLUT_HIGH */ From 496cf578aad6c21c09bcab2f476734797e4aa373 Mon Sep 17 00:00:00 2001 From: Sujit Das Date: Thu, 22 Jul 2021 11:53:55 +0530 Subject: [PATCH 6/6] msm: camera: ife: Null pointer check for dump_data When pipeline is IFE_Lite and IFE_LITE doesn't define dump_data, Need to have null check for dump_data. CRs-Fixed: 2980840 Change-Id: Icb3322b82b265829e4a54271fa30260a00f90175 Signed-off-by: Sujit Das --- .../isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c index 44edd50295de..ba17011c61b3 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c @@ -405,6 +405,12 @@ static int cam_vfe_hw_dump( return -ENOSPC; } dump_data = top_priv->common_data.dump_data; + + if (!dump_data) { + CAM_ERR(CAM_ISP, "Dump data not available"); + return -EINVAL; + } + soc_info = top_priv->common_data.soc_info; /*Dump registers */