diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi
index d1d54be460b5..3c5999d267ac 100644
--- a/qcom/shima-qupv3.dtsi
+++ b/qcom/shima-qupv3.dtsi
@@ -60,6 +60,23 @@
 		status = "ok";
 	};
 
+	/* Debug UART Instance */
+	qupv3_se13_2uart: qcom,qup_uart@994000 {
+		compatible = "qcom,msm-geni-console";
+		reg = <0x994000 0x4000>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se13_2uart_active>;
+		pinctrl-1 = <&qupv3_se13_2uart_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "ok";
+	};
+
 	qupv3_se8_i2c: i2c@980000 {
 		compatible = "qcom,i2c-geni";
 		reg = <0x980000 0x4000>;
@@ -270,23 +287,6 @@
 		status = "disabled";
 	};
 
-	/* Debug UART Instance */
-	qupv3_se13_2uart: qcom,qup_uart@994000 {
-		compatible = "qcom,msm-geni-console";
-		reg = <0x994000 0x4000>;
-		reg-names = "se_phys";
-		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "se-clk", "m-ahb", "s-ahb";
-		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
-			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
-			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
-		pinctrl-names = "default", "sleep";
-		pinctrl-0 = <&qupv3_se13_2uart_active>;
-		pinctrl-1 = <&qupv3_se13_2uart_sleep>;
-		qcom,wrapper-core = <&qupv3_0>;
-		status = "ok";
-	};
-
 	qupv3_se14_i2c: i2c@998000 {
 		compatible = "qcom,i2c-geni";
 		reg = <0x998000 0x4000>;