coresight: tmc: Set flush cti for both etr and etb

Set flush cti for both etr and etb. Set FlushandStop bit to default
value of FFCR in enablement function. Config the correct trigger number
of flush and reset cti for both etr and etb.

Change-Id: Idee3802e5a69aca521a6259f9936ddb8361a87d4
Signed-off-by: Tao Zhang <taozha@codeaurora.org>
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
This commit is contained in:
Tao Zhang 2020-08-11 17:04:53 +08:00 • committed by Mao Jinlong
commit 72dd2a16b1
2 changed files with 4 additions and 4 deletions

View file

@ -26,7 +26,7 @@ static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
TMC_FFCR_TRIGON_TRIGIN,
TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH,
drvdata->base + TMC_FFCR);
writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);

View file

@ -1013,7 +1013,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
TMC_FFCR_TRIGON_TRIGIN,
TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH,
drvdata->base + TMC_FFCR);
writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
tmc_enable_hw(drvdata);
@ -1471,7 +1471,7 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
if (IS_ERR(new_buf))
return -ENOMEM;
coresight_cti_map_trigout(drvdata->cti_flush, 3, 0);
coresight_cti_map_trigin(drvdata->cti_reset, 2, 0);
coresight_cti_map_trigin(drvdata->cti_reset, 0, 0);
}
spin_lock_irqsave(&drvdata->spinlock, flags);
}
@ -2053,7 +2053,7 @@ static int _tmc_disable_etr_sink(struct coresight_device *csdev,
flush_workqueue(drvdata->byte_cntr->usb_wq);
drvdata->usbch = NULL;
}
coresight_cti_unmap_trigin(drvdata->cti_reset, 2, 0);
coresight_cti_unmap_trigin(drvdata->cti_reset, 0, 0);
coresight_cti_unmap_trigout(drvdata->cti_flush, 3, 0);
}
out: