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msm: venc: reject unsupported sessions with VPSS enabled
Reject any sessions with non-multiple 8 of resolution and rotation/flip is enabled. Change-Id: Ifac0cc8884461fe8d2502e92481643d9443aa527 Signed-off-by: Shi Zhongbo <zhongbos@codeaurora.org>
This commit is contained in:
parent
3de9db9637
commit
7377b0c454
6 changed files with 99 additions and 0 deletions
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@ -4039,6 +4039,9 @@ int msm_venc_check_dynamic_flip_constraints(struct msm_vidc_inst *inst)
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/* Reject dynamic flip with scalar enabled */
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s_vpr_e(inst->sid, "Unsupported dynamic flip with scalar\n");
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rc = -EINVAL;
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} else if (handle_vpss_restrictions(inst)) {
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s_vpr_e(inst->sid, "Unsupported resolution for dynamic flip\n");
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rc = -EINVAL;
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}
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return rc;
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@ -4825,6 +4828,69 @@ int check_blur_restrictions(struct msm_vidc_inst *inst)
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return 0;
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}
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int handle_vpss_restrictions(struct msm_vidc_inst *inst)
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{
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struct v4l2_ctrl *rotation = NULL;
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struct v4l2_ctrl *hflip = NULL;
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struct v4l2_ctrl *vflip = NULL;
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struct v4l2_format *f;
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struct msm_vidc_vpss_capability *vpss_caps;
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u32 vpss_caps_count;
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bool rotation_flip_enable = false;
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u32 i,input_height, input_width;
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if (!inst || !inst->core) {
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d_vpr_e("%s: invalid params %pK\n", __func__, inst);
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return -EINVAL;
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}
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f = &inst->fmts[INPUT_PORT].v4l2_fmt;
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input_height = f->fmt.pix_mp.height;
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input_width = f->fmt.pix_mp.width;
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vpss_caps = inst->core->resources.vpss_caps;
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vpss_caps_count = inst->core->resources.vpss_caps_count;
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/* check customer specified VPSS resolutions */
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if (vpss_caps) {
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for (i = 0; i < vpss_caps_count; i++) {
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if (input_width == vpss_caps[i].width &&
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input_height == vpss_caps[i].height) {
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s_vpr_h(inst->sid,
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"supported resolution found for VPSS, width = %d, height = %d\n",
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input_width, input_height);
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return 0;
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}
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}
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}
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/* check rotation and flip contraint for VPSS
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* any rotation or flip sessions with non-multiple of 8
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* resolution is rejected.
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*/
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rotation = get_ctrl(inst, V4L2_CID_ROTATE);
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hflip = get_ctrl(inst, V4L2_CID_HFLIP);
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vflip = get_ctrl(inst, V4L2_CID_VFLIP);
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if (rotation->val != 0 ||
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hflip->val != V4L2_MPEG_MSM_VIDC_DISABLE ||
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vflip->val != V4L2_MPEG_MSM_VIDC_DISABLE)
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rotation_flip_enable = true;
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if (rotation_flip_enable) {
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if ((input_width & 7) != 0) {
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s_vpr_e(inst->sid, "Unsupported width = %d for VPSS\n",
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input_width);
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return -ENOTSUPP;
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}
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if ((input_height & 7) != 0) {
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s_vpr_e(inst->sid, "Unsupported height = %d for VPSS\n",
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input_height);
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return -ENOTSUPP;
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}
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}
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return 0;
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}
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int msm_venc_set_properties(struct msm_vidc_inst *inst)
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{
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int rc = 0;
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@ -4836,6 +4902,9 @@ int msm_venc_set_properties(struct msm_vidc_inst *inst)
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if (rc)
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goto exit;
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rc = handle_all_intra_restrictions(inst);
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if (rc)
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goto exit;
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rc = handle_vpss_restrictions(inst);
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if (rc)
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goto exit;
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rc = msm_venc_set_frame_size(inst);
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@ -49,4 +49,5 @@ int check_blur_restrictions(struct msm_vidc_inst *inst);
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int msm_venc_set_frame_quality(struct msm_vidc_inst *inst);
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int msm_venc_set_image_grid(struct msm_vidc_inst *inst);
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int msm_venc_set_bitrate_boost_margin(struct msm_vidc_inst *inst, u32 enable);
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int handle_vpss_restrictions(struct msm_vidc_inst *inst);
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#endif
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@ -229,6 +229,11 @@ struct msm_vidc_codec_capability {
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u32 default_value;
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};
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struct msm_vidc_vpss_capability {
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u32 width;
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u32 height;
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};
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struct msm_vidc_codec {
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enum hal_domain domain;
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enum hal_video_codec codec;
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@ -296,6 +301,8 @@ struct msm_vidc_platform_data {
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uint32_t codecs_count;
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struct msm_vidc_codec_capability *codec_caps;
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uint32_t codec_caps_count;
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struct msm_vidc_vpss_capability *vpss_caps;
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uint32_t vpss_caps_count;
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struct msm_vidc_csc_coeff csc_data;
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struct msm_vidc_efuse_data *efuse_data;
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unsigned int efuse_data_length;
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@ -747,6 +747,16 @@ static struct msm_vidc_codec_capability shima_capabilities_v2[] = {
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V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
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};
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/* Generally Iris2 VPSS only support 8 multiple encoding if
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* rotation/flip is enabled, however customer can require specific
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* resolution supports and expand capabilities here.
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*/
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static struct msm_vidc_vpss_capability vpss_capabilities[] = {
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/* {supported width, supported height,} */
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{3840, 1644},
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{1644, 3840},
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};
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/*
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* Custom conversion coefficients for resolution: 176x144 negative
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* coeffs are converted to s4.9 format
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@ -1498,6 +1508,8 @@ static struct msm_vidc_platform_data lahaina_data = {
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.codecs_count = ARRAY_SIZE(default_codecs),
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.codec_caps = lahaina_capabilities,
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.codec_caps_count = ARRAY_SIZE(lahaina_capabilities),
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.vpss_caps = vpss_capabilities,
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.vpss_caps_count = ARRAY_SIZE(vpss_capabilities),
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};
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static struct msm_vidc_platform_data bengal_data = {
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@ -1520,6 +1532,8 @@ static struct msm_vidc_platform_data bengal_data = {
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.codecs_count = ARRAY_SIZE(bengal_codecs),
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.codec_caps = bengal_capabilities_v0,
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.codec_caps_count = ARRAY_SIZE(bengal_capabilities_v0),
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.vpss_caps = NULL,
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.vpss_caps_count = 0,
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};
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static struct msm_vidc_platform_data shima_data = {
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@ -1542,6 +1556,8 @@ static struct msm_vidc_platform_data shima_data = {
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.codecs_count = ARRAY_SIZE(shima_codecs),
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.codec_caps = shima_capabilities_v0,
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.codec_caps_count = ARRAY_SIZE(shima_capabilities_v0),
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.vpss_caps = vpss_capabilities,
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.vpss_caps_count = ARRAY_SIZE(vpss_capabilities),
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};
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static struct msm_vidc_platform_data holi_data = {
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@ -1564,6 +1580,8 @@ static struct msm_vidc_platform_data holi_data = {
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.codecs_count = ARRAY_SIZE(holi_codecs),
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.codec_caps = holi_capabilities,
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.codec_caps_count = ARRAY_SIZE(holi_capabilities),
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.vpss_caps = NULL,
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.vpss_caps_count = 0,
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};
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static const struct of_device_id msm_vidc_dt_device[] = {
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@ -733,6 +733,8 @@ int read_platform_resources_from_drv_data(
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res->codec_data = platform_data->codec_data;
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res->allowed_clks_tbl = platform_data->clock_data;
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res->allowed_clks_tbl_size = platform_data->clock_data_length;
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res->vpss_caps = platform_data->vpss_caps;
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res->vpss_caps_count = platform_data->vpss_caps_count;
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res->sku_version = platform_data->sku_version;
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res->mem_limit_tbl = memory_limit_tbl_mbytes;
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@ -194,6 +194,8 @@ struct msm_vidc_platform_resources {
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uint32_t codecs_count;
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struct msm_vidc_codec_capability *codec_caps;
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uint32_t codec_caps_count;
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struct msm_vidc_vpss_capability *vpss_caps;
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uint32_t vpss_caps_count;
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struct msm_vidc_csc_coeff *csc_coeff_data;
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struct msm_vidc_mem_cdsp mem_cdsp;
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uint32_t vpu_ver;
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