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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-13 08:07:32 -04:00
ARM: dts: msm: add 2nd UFS for Quin SA8195 LXC VM
enable 2nd UFS pass-through on SA8195 LXC VM. Change-Id: I71cbee302756cbcd2a664daa2f46b60d329cfeaf
This commit is contained in:
Yimin Peng
parent
99be538d76
commit
73ad2256e4
3 changed files with 224 additions and 0 deletions
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@ -59,3 +59,12 @@
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};
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#include "sa8195-vm-lv-cnss-lxc.dtsi"
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#include "sa8195-vm-ufs.dtsi"
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&ufs2phy_mem {
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status = "ok"
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};
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&ufshc2_mem {
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status = "ok"
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};
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211
qcom/sa8195-vm-ufs.dtsi
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211
qcom/sa8195-vm-ufs.dtsi
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@ -0,0 +1,211 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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®ulator {
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L17A: pm8195_1_l17: regulator-pm8195-1-l17 {
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regulator-name = "ldoa17";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3544000>;
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regulator-always-on;
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regulator-allow-set-load;
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};
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L5C: pm8195_2_l5: regulator-pm8195-2-l5 {
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regulator-name = "ldoc5";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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L10E: pm8195_3_l10: regulator-pm8195-3-l10 {
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regulator-name = "ldoe10";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <3544000>;
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regulator-always-on;
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};
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S4A: pm8195_1_s4: regulator-pm8195-1-s4 {
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regulator-name = "smpa4";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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};
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&soc {
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ufs2_ice: ufs2ice@1d70000 {
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compatible = "qcom,ice";
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reg = <0x1d70000 0x8000>;
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qcom,enable-ice-clk;
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clock-names = "ufs_core_clk",
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"iface_clk", "ice_core_clk";
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clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
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<&gcc GCC_UFS_CARD_2_AHB_CLK>,
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<&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>;
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qcom,op-freq-hz = <0>, <0>, <300000000>;
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vdd-hba-supply = <&ufs_card_2_gdsc>;
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qcom,msm-bus,name = "ufs_ice_noc";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<1 650 0 0>, /* No vote */
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<1 650 1000 0>; /* Max. bandwidth */
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qcom,bus-vector-names = "MIN",
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"MAX";
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qcom,instance-type = "ufs";
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status = "disabled";
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};
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ufs2phy_mem: ufsphy2_mem@1d67000 {
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compatible = "qcom,ufs-phy-qmp-v4";
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reg = <0x1d67000 0xe00>; /* PHY regs */
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reg-names = "phy_mem";
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#phy-cells = <0>;
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ufs-qcom-crypto = <&ufs2_ice>;
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lanes-per-direction = <2>;
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vdda-phy-supply = <&pm8195_3_l5>;
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vdda-pll-supply = <&pm8195_1_l9>;
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vdda-phy-max-microamp = <138000>;
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vdda-pll-max-microamp = <65100>;
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clock-names = "ref_clk_src",
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"ref_aux_clk";
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clocks = <&dummycc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_CARD_2_PHY_AUX_CLK>;
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status = "disabled";
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};
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ufshc2_mem: ufshc2@1d64000 {
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compatible = "qcom,ufshc";
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reg = <0x1d64000 0x3000>;
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interrupts = <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs2phy_mem>;
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phy-names = "ufsphy";
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ufs-qcom-crypto = <&ufs2_ice>;
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spm-level = <5>;
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rpm-level = <1>;
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lanes-per-direction = <2>;
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dev-ref-clk-freq = <0>; /* 19.2 MHz */
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vdd-hba-supply = <&ufs_card_2_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm8195_1_l17>;
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vcc-voltage-level = <2894000 2904000>;
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vcc-low-voltage-sup;
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vccq-supply = <&pm8195_2_l5>;
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vccq2-supply = <&pm8195_1_s4>;
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vcc-max-microamp = <750000>;
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vccq-max-microamp = <750000>;
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vccq2-max-microamp = <750000>;
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qcom,vddp-ref-clk-supply = <&pm8195_2_l5>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vccq-parent-supply = <&pm8195_1_s2>;
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qcom,vccq-parent-max-microamp = <210000>;
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qcom,disable-lpm;
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"core_clk_ice",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_CARD_2_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>,
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<&gcc GCC_UFS_CARD_2_AHB_CLK>,
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<&gcc GCC_UFS_CARD_2_UNIPRO_CORE_CLK>,
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<&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>,
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<&dummycc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_CARD_2_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_CARD_2_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_CARD_2_RX_SYMBOL_1_CLK>;
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freq-table-hz =
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<37500000 300000000>,
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>;
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qcom,msm-bus,name = "ufshc_mem";
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qcom,msm-bus,num-cases = <26>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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/*
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* During HS G3 UFS runs at nominal voltage corner, vote
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* higher bandwidth to push other buses in the data path
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* to run at nominal to achieve max throughput.
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* 4GBps pushes BIMC to run at nominal.
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* 200MBps pushes CNOC to run at nominal.
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* Vote for half of this bandwidth for HS G3 1-lane.
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* For max bandwidth, vote high enough to push the buses
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* to run in turbo voltage corner.
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*/
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<163 512 0 0>, <1 798 0 0>, /* No vote */
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<163 512 922 0>, <1 798 1000 0>, /* PWM G1 */
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<163 512 1844 0>, <1 798 1000 0>, /* PWM G2 */
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<163 512 3688 0>, <1 798 1000 0>, /* PWM G3 */
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<163 512 7376 0>, <1 798 1000 0>, /* PWM G4 */
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<163 512 1844 0>, <1 798 1000 0>, /* PWM G1 L2 */
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<163 512 3688 0>, <1 798 1000 0>, /* PWM G2 L2 */
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<163 512 7376 0>, <1 798 1000 0>, /* PWM G3 L2 */
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<163 512 14752 0>, <1 798 1000 0>, /* PWM G4 L2 */
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<163 512 127796 0>, <1 798 1000 0>, /* HS G1 RA */
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<163 512 255591 0>, <1 798 1000 0>, /* HS G2 RA */
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<163 512 2097152 0>, <1 798 102400 0>, /* HS G3 RA */
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<163 512 4194304 0>, <1 798 204800 0>, /* HS G4 RA */
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<163 512 255591 0>, <1 798 1000 0>, /* HS G1 RA L2 */
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<163 512 511181 0>, <1 798 1000 0>, /* HS G2 RA L2 */
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<163 512 4194304 0>, <1 798 204800 0>, /* HS G3 RA L2 */
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<163 512 8388608 0>, <1 798 409600 0>, /* HS G4 RA L2 */
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<163 512 149422 0>, <1 798 1000 0>, /* HS G1 RB */
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<163 512 298189 0>, <1 798 1000 0>, /* HS G2 RB */
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<163 512 2097152 0>, <1 798 102400 0>, /* HS G3 RB */
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<163 512 4194304 0>, <1 798 204800 0>, /* HS G4 RB */
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<163 512 298189 0>, <1 798 1000 0>, /* HS G1 RB L2 */
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<163 512 596378 0>, <1 798 1000 0>, /* HS G2 RB L2 */
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/* As UFS working in HS G3 RB L2 mode, aggregated
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* bandwidth (AB) should take care of providing
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* optimum throughput requested. However, as tested,
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* in order to scale up CNOC clock, instantaneous
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* bindwidth (IB) needs to be given a proper value too.
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*/
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<163 512 4194304 0>, <1 798 204800 409600>, /* HS G3 RB L2 */
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<163 512 8388608 0>, <1 798 409600 409600>, /* HS G4 RB L2 */
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<163 512 7643136 0>, <1 798 307200 0>; /* Max. bandwidth */
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qcom,bus-vector-names = "MIN",
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"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
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"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
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"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
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"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
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"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
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"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
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"MAX";
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/* PM QoS */
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qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
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qcom,pm-qos-cpu-group-latency-us = <44 44>;
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qcom,pm-qos-default-cpu = <0>;
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pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
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pinctrl-0 = <&ufs0_dev_reset_assert>;
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pinctrl-1 = <&ufs0_dev_reset_deassert>;
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resets = <&gcc GCC_UFS_CARD_2_BCR>;
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reset-names = "core_reset";
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status = "disabled";
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};
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};
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@ -770,6 +770,10 @@
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regulator-name = "pcie_3_gdsc";
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};
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ufs_card_2_gdsc: ufs_card_2_gdsc {
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regulator-name = "ufs_card_2_gdsc";
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};
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L2A: pm8195_1_l2: regulator-pm8195-1-l2 {
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regulator-name = "ldoa2";
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regulator-min-microvolt = <1800000>;
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