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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 16:46:15 -04:00
Merge "ARM: dts: msm: Add fmax support for holi GPU"
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qctecmdr
Gerrit - the friendly Code Review server
commit
73dd79b99a
1 changed files with 207 additions and 75 deletions
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@ -37,6 +37,12 @@ msm_gpu: qcom,kgsl-3d0@5900000 {
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <2>;
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/* Enable context aware freq. scaling */
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qcom,enable-ca-jump;
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/* Context aware jump busy penalty in us */
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qcom,ca-busy-penalty = <12000>;
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interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI>;
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interconnect-names = "gpu_icc_path";
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@ -83,94 +89,220 @@ msm_gpu: qcom,kgsl-3d0@5900000 {
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};
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};
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/* Power levels */
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qcom,gpu-pwrlevels {
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/*
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* Speed-bin zero is default speed bin.
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* For rest of the speed bins, speed-bin value
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* is calulated as FMAX/4.8 MHz (round up to zero
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* decimal places) + 2.
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*/
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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compatible = "qcom,gpu-pwrlevel-bins";
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <875000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,ca-target-pwrlevel = <5>;
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qcom,initial-pwrlevel = <6>;
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qcom,bus-freq-ddr7 = <9>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <9>;
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};
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <875000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <800000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq-ddr7 = <9>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <9>;
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};
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <9>;
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <800000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <9>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <650000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <7>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <9>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <565000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <6>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <8>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <430000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <355000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7= <5>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <253000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <1>;
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qcom,bus-max-ddr7 = <4>;
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};
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <650000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <138>;
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qcom,ca-target-pwrlevel = <3>;
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qcom,initial-pwrlevel = <4>;
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qcom,bus-freq-ddr7 = <7>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <9>;
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/* NOM_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <650000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <7>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <9>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <565000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <6>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <8>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <430000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <355000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7= <5>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <253000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <1>;
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qcom,bus-max-ddr7 = <4>;
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};
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <565000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <92>;
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qcom,ca-target-pwrlevel = <2>;
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qcom,initial-pwrlevel = <1>;
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qcom,bus-freq-ddr7 = <6>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <8>;
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/* SVS_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <430000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <355000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7= <5>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <253000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <1>;
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qcom,bus-max-ddr7 = <4>;
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};
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <430000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <355000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7= <5>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <253000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <1>;
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qcom,bus-max-ddr7 = <4>;
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@5940000 {
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