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Merge "clk: qcom: gpucc-shima: Keep POR enabled gpu_cc_cb_clk always ON"

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This commit is contained in:
qctecmdr 2020-09-21 23:57:21 -07:00 • committed by Gerrit - the friendly Code Review server
commit 74fea8b624
2 changed files with 14 additions and 16 deletions
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13
drivers/clk/qcom/debugcc-shima.c
View file

@ -552,7 +552,6 @@ static struct clk_debug_mux gcc_debug_mux = {
static const char *const gpu_cc_debug_mux_parent_names[] = {
"gpu_cc_ahb_clk",
"gpu_cc_cb_clk",
"gpu_cc_crc_ahb_clk",
"gpu_cc_cx_gmu_clk",
"gpu_cc_cx_snoc_dvm_clk",
@ -564,6 +563,7 @@ static const char *const gpu_cc_debug_mux_parent_names[] = {
"gpu_cc_mnd1x_0_gfx3d_clk",
"gpu_cc_mnd1x_1_gfx3d_clk",
"gpu_cc_sleep_clk",
"measure_only_gpu_cc_cb_clk",
"measure_only_gpu_cc_cx_gfx3d_clk",
"measure_only_gpu_cc_cx_gfx3d_slv_clk",
"measure_only_gpu_cc_gx_gfx3d_clk",
@ -571,7 +571,6 @@ static const char *const gpu_cc_debug_mux_parent_names[] = {
static int gpu_cc_debug_mux_sels[] = {
0x12, /* gpu_cc_ahb_clk */
0x26, /* gpu_cc_cb_clk */
0x13, /* gpu_cc_crc_ahb_clk */
0x1A, /* gpu_cc_cx_gmu_clk */
0x17, /* gpu_cc_cx_snoc_dvm_clk */
@ -583,6 +582,7 @@ static int gpu_cc_debug_mux_sels[] = {
0x21, /* gpu_cc_mnd1x_0_gfx3d_clk */
0x22, /* gpu_cc_mnd1x_1_gfx3d_clk */
0x18, /* gpu_cc_sleep_clk */
0x26, /* measure_only_gpu_cc_cb_clk */
0x1D, /* measure_only_gpu_cc_cx_gfx3d_clk */
0x1E, /* measure_only_gpu_cc_cx_gfx3d_slv_clk */
0xD, /* measure_only_gpu_cc_gx_gfx3d_clk */
@ -715,6 +715,14 @@ static struct clk_dummy measure_only_cnoc_clk = {
},
};
static struct clk_dummy measure_only_gpu_cc_cb_clk = {
.rrate = 1000,
.hw.init = &(struct clk_init_data){
.name = "measure_only_gpu_cc_cb_clk",
.ops = &clk_dummy_ops,
},
};
static struct clk_dummy measure_only_gpu_cc_cx_gfx3d_clk = {
.rrate = 1000,
.hw.init = &(struct clk_init_data){
@ -777,6 +785,7 @@ static struct clk_hw *debugcc_shima_hws[] = {
&measure_only_apcs_l3_post_acd_clk.hw,
&measure_only_apcs_silver_post_acd_clk.hw,
&measure_only_cnoc_clk.hw,
&measure_only_gpu_cc_cb_clk.hw,
&measure_only_gpu_cc_cx_gfx3d_clk.hw,
&measure_only_gpu_cc_cx_gfx3d_slv_clk.hw,
&measure_only_gpu_cc_gx_gfx3d_clk.hw,

17
drivers/clk/qcom/gpucc-shima.c
View file

@ -263,19 +263,6 @@ static struct clk_branch gpu_cc_ahb_clk = {
},
};
static struct clk_branch gpu_cc_cb_clk = {
.halt_reg = 0x1170,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1170,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_VOTED,
@ -460,7 +447,6 @@ static struct clk_branch gpu_cc_sleep_clk = {
static struct clk_regmap *gpu_cc_shima_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
@ -538,6 +524,9 @@ static int gpu_cc_shima_probe(struct platform_device *pdev)
clk_lucid_5lpe_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_5lpe_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/* gpu_cc_cb_clk */
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &gpu_cc_shima_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");