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msm: kgsl: configure macrotiling channels for A680

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For macrotiling change on a680, will affect RB, SP and TP
0 means UBWC 3.0, 1 means UBWC 3.1, this change configures
the RBBM hardware accordingly.

Change-Id: Ife8325a88e37b5b81ef6060c11edb7b7b2aab165
Signed-off-by: Hui Li <hul@codeaurora.org>
This commit is contained in:
Hui Li 2021-03-04 11:52:22 +08:00
commit 7523b0c37e
1 changed files with 7 additions and 0 deletions
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7
drivers/gpu/msm/adreno_a6xx.c
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@ -652,6 +652,13 @@ void a6xx_start(struct adreno_device *adreno_dev)
break;
}
/*
* For macrotiling change on a680, will affect RB, SP and TP
* 0 means UBWC 3.0, 1 means UBWC 3.1
*/
if (adreno_is_a680(adreno_dev))
kgsl_regwrite(device, A6XX_RBBM_NC_MODE_CNTL, 1);
if (!WARN_ON(!adreno_dev->highest_bank_bit)) {
hbb_lo = (adreno_dev->highest_bank_bit - 13) & 3;
hbb_hi = ((adreno_dev->highest_bank_bit - 13) >> 2) & 1;