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clk: qcom: gcc-lahaina: Add USB force_mem_core_on clocks

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The FORCE_MEM_CORE_ON bits default to 0 and this is fine for most use
cases. However, USB needs FORCE_MEM_CORE_ON=1 to properly retain its
memories when USB APM switches from CX to MX. This can't just be a
one-time setting since the FORCE_MEM_CORE_ON bits need to be set/cleared
upon USB cable connect/disconnect for power optimization. Add fake
clocks to allow the USB client to control them.

Change-Id: Ic7aac944feaa6a956a8892e0cf1f4dd465659302
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
This commit is contained in:
Mike Tipton 2020-06-02 18:13:47 -07:00
commit 75656695f4
1 changed files with 30 additions and 0 deletions
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30
drivers/clk/qcom/gcc-lahaina.c
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@ -3795,6 +3795,19 @@ static struct clk_branch gcc_usb30_prim_master_clk = {
},
};
static struct clk_branch gcc_usb30_prim_master_clk__force_mem_core_on = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk__force_mem_core_on",
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf01c,
.halt_check = BRANCH_HALT,
@ -3845,6 +3858,19 @@ static struct clk_branch gcc_usb30_sec_master_clk = {
},
};
static struct clk_branch gcc_usb30_sec_master_clk__force_mem_core_on = {
.halt_reg = 0x10010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10010,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk__force_mem_core_on",
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x1001c,
.halt_check = BRANCH_HALT,
@ -4244,6 +4270,8 @@ static struct clk_regmap *gcc_lahaina_clocks[] = {
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
&gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON] =
&gcc_usb30_prim_master_clk__force_mem_core_on.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
@ -4252,6 +4280,8 @@ static struct clk_regmap *gcc_lahaina_clocks[] = {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON] =
&gcc_usb30_sec_master_clk__force_mem_core_on.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =