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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 06:09:23 -04:00
msm: kgsl: Keep a copy of CP INIT cmdstream
This way, we don't have to do checks when composing the CP INIT cmdstream. This will also be used by eCP. Change-Id: I91dc54b18aee0443d5a2724daeaadc5224de1a92 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This commit is contained in:
Harshdeep Dhatt
parent
e9fad773e6
commit
75a9117cad
5 changed files with 149 additions and 95 deletions
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@ -1830,6 +1830,12 @@ static int adreno_init(struct kgsl_device *device)
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if (ret)
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return ret;
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if (gpudev->init != NULL) {
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ret = gpudev->init(adreno_dev);
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if (ret)
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return ret;
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}
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ret = gmu_core_init(device);
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if (ret)
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return ret;
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@ -1853,9 +1859,6 @@ static int adreno_init(struct kgsl_device *device)
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if (ADRENO_GPUREV(adreno_dev) < 600)
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kgsl_pwrctrl_change_state(device, KGSL_STATE_SLUMBER);
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if (gpudev->init != NULL)
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gpudev->init(adreno_dev);
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set_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);
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/*
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@ -536,7 +536,8 @@ struct adreno_device {
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* @critpkts: Memory descriptor for 5xx secure critical packets
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*/
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struct kgsl_memdesc *critpkts_secure;
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/** @cp_init_cmds: A copy of the CP INIT commands */
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const void *cp_init_cmds;
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};
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/**
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@ -776,7 +777,7 @@ struct adreno_gpudev {
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void (*snapshot)(struct adreno_device *adreno_dev,
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struct kgsl_snapshot *snapshot);
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void (*platform_setup)(struct adreno_device *adreno_dev);
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void (*init)(struct adreno_device *adreno_dev);
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int (*init)(struct adreno_device *adreno_dev);
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void (*remove)(struct adreno_device *adreno_dev);
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int (*rb_start)(struct adreno_device *adreno_dev);
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int (*microcode_read)(struct adreno_device *adreno_dev);
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/firmware.h>
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@ -124,6 +124,8 @@ static const unsigned int _a3xx_pwron_fixup_fs_instructions[] = {
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0x00000000, 0x03000000, 0x00000000, 0x00000000,
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};
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static int a3xx_get_cp_init_cmds(struct adreno_device *adreno_dev);
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static void a3xx_efuse_speed_bin(struct adreno_device *adreno_dev)
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{
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unsigned int val;
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@ -623,28 +625,7 @@ static int a3xx_send_me_init(struct adreno_device *adreno_dev,
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if (cmds == NULL)
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return -ENOSPC;
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*cmds++ = cp_type3_packet(CP_ME_INIT, 17);
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*cmds++ = 0x000003f7;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000080;
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*cmds++ = 0x00000100;
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*cmds++ = 0x00000180;
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*cmds++ = 0x00006600;
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*cmds++ = 0x00000150;
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*cmds++ = 0x0000014e;
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*cmds++ = 0x00000154;
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*cmds++ = 0x00000001;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000000;
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/* Enable protected mode registers for A3XX */
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*cmds++ = 0x20000000;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000000;
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memcpy(cmds, adreno_dev->cp_init_cmds, 18 << 2);
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ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
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if (ret) {
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@ -685,13 +666,56 @@ static int a3xx_rb_start(struct adreno_device *adreno_dev)
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return a3xx_send_me_init(adreno_dev, rb);
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}
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static int a3xx_get_cp_init_cmds(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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u32 *cmds;
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if (adreno_dev->cp_init_cmds)
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return 0;
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adreno_dev->cp_init_cmds = devm_kzalloc(&device->pdev->dev, 18 << 2,
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GFP_KERNEL);
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if (!adreno_dev->cp_init_cmds)
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return -ENOMEM;
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cmds = (u32 *)adreno_dev->cp_init_cmds;
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*cmds++ = cp_type3_packet(CP_ME_INIT, 17);
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*cmds++ = 0x000003f7;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000080;
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*cmds++ = 0x00000100;
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*cmds++ = 0x00000180;
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*cmds++ = 0x00006600;
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*cmds++ = 0x00000150;
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*cmds++ = 0x0000014e;
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*cmds++ = 0x00000154;
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*cmds++ = 0x00000001;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000000;
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/* Enable protected mode registers for A3XX */
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*cmds++ = 0x20000000;
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*cmds++ = 0x00000000;
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*cmds++ = 0x00000000;
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return 0;
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}
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/*
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* a3xx_init() - Initialize gpu specific data
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* @adreno_dev: Pointer to adreno device
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*/
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static void a3xx_init(struct adreno_device *adreno_dev)
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static int a3xx_init(struct adreno_device *adreno_dev)
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{
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_a3xx_pwron_fixup(adreno_dev);
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return a3xx_get_cp_init_cmds(adreno_dev);
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}
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/*
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@ -25,6 +25,7 @@ static int _read_fw2_block_header(struct kgsl_device *device,
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uint32_t id, uint32_t major, uint32_t minor);
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static void a5xx_gpmu_reset(struct work_struct *work);
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static int a5xx_gpmu_init(struct adreno_device *adreno_dev);
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static int a5xx_get_cp_init_cmds(struct adreno_device *adreno_dev);
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/**
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* Number of times to check if the regulator enabled before
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@ -185,7 +186,7 @@ static int a5xx_critical_packet_construct(struct adreno_device *adreno_dev)
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return 0;
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}
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static void a5xx_init(struct adreno_device *adreno_dev)
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static int a5xx_init(struct adreno_device *adreno_dev)
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{
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const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);
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@ -199,8 +200,9 @@ static void a5xx_init(struct adreno_device *adreno_dev)
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if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_CRITICAL_PACKETS))
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a5xx_critical_packet_construct(adreno_dev);
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a5xx_crashdump_init(adreno_dev);
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return a5xx_get_cp_init_cmds(adreno_dev);
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}
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const static struct {
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@ -1739,42 +1741,6 @@ static int _me_init_ucode_workarounds(struct adreno_device *adreno_dev)
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CP_INIT_DEFAULT_RESET_STATE | \
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CP_INIT_UCODE_WORKAROUND_MASK)
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static void _set_ordinals(struct adreno_device *adreno_dev,
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unsigned int *cmds, unsigned int count)
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{
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unsigned int *start = cmds;
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/* Enabled ordinal mask */
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*cmds++ = CP_INIT_MASK;
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if (CP_INIT_MASK & CP_INIT_MAX_CONTEXT)
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*cmds++ = 0x00000003;
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if (CP_INIT_MASK & CP_INIT_ERROR_DETECTION_CONTROL)
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*cmds++ = 0x20000000;
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if (CP_INIT_MASK & CP_INIT_HEADER_DUMP) {
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/* Header dump address */
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*cmds++ = 0x00000000;
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/* Header dump enable and dump size */
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*cmds++ = 0x00000000;
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}
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if (CP_INIT_MASK & CP_INIT_DRAWCALL_FILTER_RANGE) {
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/* Start range */
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*cmds++ = 0x00000000;
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/* End range (inclusive) */
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*cmds++ = 0x00000000;
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}
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if (CP_INIT_MASK & CP_INIT_UCODE_WORKAROUND_MASK)
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*cmds++ = _me_init_ucode_workarounds(adreno_dev);
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/* Pad rest of the cmds with 0's */
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while ((unsigned int)(cmds - start) < count)
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*cmds++ = 0x0;
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}
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static int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,
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struct adreno_ringbuffer *rb)
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{
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@ -1800,6 +1766,53 @@ static int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,
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return ret;
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}
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static int a5xx_get_cp_init_cmds(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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u32 *cmds, i = 0;
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if (adreno_dev->cp_init_cmds)
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return 0;
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adreno_dev->cp_init_cmds = devm_kzalloc(&device->pdev->dev, 9 << 2,
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GFP_KERNEL);
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if (!adreno_dev->cp_init_cmds)
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return -ENOMEM;
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cmds = (u32 *)adreno_dev->cp_init_cmds;
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cmds[i++] = cp_type7_packet(CP_ME_INIT, 8);
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/* Enabled ordinal mask */
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cmds[i++] = CP_INIT_MASK;
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if (CP_INIT_MASK & CP_INIT_MAX_CONTEXT)
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cmds[i++] = 0x00000003;
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if (CP_INIT_MASK & CP_INIT_ERROR_DETECTION_CONTROL)
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cmds[i++] = 0x20000000;
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if (CP_INIT_MASK & CP_INIT_HEADER_DUMP) {
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/* Header dump address */
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cmds[i++] = 0x00000000;
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/* Header dump enable and dump size */
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cmds[i++] = 0x00000000;
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}
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if (CP_INIT_MASK & CP_INIT_DRAWCALL_FILTER_RANGE) {
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/* Start range */
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cmds[i++] = 0x00000000;
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/* End range (inclusive) */
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cmds[i++] = 0x00000000;
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}
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if (CP_INIT_MASK & CP_INIT_UCODE_WORKAROUND_MASK)
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cmds[i++] = _me_init_ucode_workarounds(adreno_dev);
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return 0;
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}
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/*
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* a5xx_send_me_init() - Initialize ringbuffer
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* @adreno_dev: Pointer to adreno device
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@ -1819,9 +1832,7 @@ static int a5xx_send_me_init(struct adreno_device *adreno_dev,
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if (cmds == NULL)
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return -ENOSPC;
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*cmds++ = cp_type7_packet(CP_ME_INIT, 8);
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_set_ordinals(adreno_dev, cmds, 8);
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memcpy(cmds, adreno_dev->cp_init_cmds, 9 << 2);
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ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
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if (ret)
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@ -99,10 +99,11 @@ static u32 a612_pwrup_reglist[] = {
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A6XX_RBBM_PERFCTR_CNTL,
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};
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static void a6xx_init(struct adreno_device *adreno_dev)
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static int a6xx_get_cp_init_cmds(struct adreno_device *adreno_dev);
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static int a6xx_init(struct adreno_device *adreno_dev)
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{
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const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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adreno_dev->highest_bank_bit = a6xx_core->highest_bank_bit;
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@ -111,10 +112,16 @@ static void a6xx_init(struct adreno_device *adreno_dev)
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a6xx_crashdump_init(adreno_dev);
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if (IS_ERR_OR_NULL(adreno_dev->pwrup_reglist))
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adreno_dev->pwrup_reglist = kgsl_allocate_global(device,
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PAGE_SIZE, 0, KGSL_MEMDESC_PRIVILEGED,
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"powerup_register_list");
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if (IS_ERR_OR_NULL(adreno_dev->pwrup_reglist)) {
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adreno_dev->pwrup_reglist =
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kgsl_allocate_global(KGSL_DEVICE(adreno_dev),
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PAGE_SIZE, 0, KGSL_MEMDESC_PRIVILEGED,
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"powerup_register_list");
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if (IS_ERR(adreno_dev->pwrup_reglist))
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return PTR_ERR(adreno_dev->pwrup_reglist);
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}
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return a6xx_get_cp_init_cmds(adreno_dev);
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}
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static void a6xx_protect_init(struct adreno_device *adreno_dev)
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@ -663,44 +670,54 @@ static int a6xx_microcode_load(struct adreno_device *adreno_dev)
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CP_INIT_OPERATION_MODE_MASK | \
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CP_INIT_REGISTER_INIT_LIST_WITH_SPINLOCK)
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static void _set_ordinals(struct adreno_device *adreno_dev,
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unsigned int *cmds, unsigned int count)
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static int a6xx_get_cp_init_cmds(struct adreno_device *adreno_dev)
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{
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unsigned int *start = cmds;
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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u32 *cmds, i = 0;
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if (adreno_dev->cp_init_cmds)
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return 0;
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adreno_dev->cp_init_cmds = devm_kzalloc(&device->pdev->dev, 12 << 2,
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GFP_KERNEL);
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if (!adreno_dev->cp_init_cmds)
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return -ENOMEM;
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cmds = (u32 *)adreno_dev->cp_init_cmds;
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cmds[i++] = cp_type7_packet(CP_ME_INIT, 11);
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/* Enabled ordinal mask */
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*cmds++ = CP_INIT_MASK;
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cmds[i++] = CP_INIT_MASK;
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if (CP_INIT_MASK & CP_INIT_MAX_CONTEXT)
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*cmds++ = 0x00000003;
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cmds[i++] = 0x00000003;
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if (CP_INIT_MASK & CP_INIT_ERROR_DETECTION_CONTROL)
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*cmds++ = 0x20000000;
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cmds[i++] = 0x20000000;
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if (CP_INIT_MASK & CP_INIT_HEADER_DUMP) {
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/* Header dump address */
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*cmds++ = 0x00000000;
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cmds[i++] = 0x00000000;
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/* Header dump enable and dump size */
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*cmds++ = 0x00000000;
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cmds[i++] = 0x00000000;
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}
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if (CP_INIT_MASK & CP_INIT_UCODE_WORKAROUND_MASK)
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*cmds++ = 0x00000000;
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cmds[i++] = 0x00000000;
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if (CP_INIT_MASK & CP_INIT_OPERATION_MODE_MASK)
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*cmds++ = 0x00000002;
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cmds[i++] = 0x00000002;
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if (CP_INIT_MASK & CP_INIT_REGISTER_INIT_LIST_WITH_SPINLOCK) {
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uint64_t gpuaddr = adreno_dev->pwrup_reglist->gpuaddr;
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*cmds++ = lower_32_bits(gpuaddr);
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*cmds++ = upper_32_bits(gpuaddr);
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*cmds++ = 0;
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cmds[i++] = lower_32_bits(gpuaddr);
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cmds[i++] = upper_32_bits(gpuaddr);
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cmds[i++] = 0;
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}
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/* Pad rest of the cmds with 0's */
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while ((unsigned int)(cmds - start) < count)
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*cmds++ = 0x0;
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return 0;
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}
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/*
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@ -721,9 +738,7 @@ static int a6xx_send_cp_init(struct adreno_device *adreno_dev,
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if (IS_ERR(cmds))
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return PTR_ERR(cmds);
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*cmds++ = cp_type7_packet(CP_ME_INIT, 11);
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_set_ordinals(adreno_dev, cmds, 11);
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memcpy(cmds, adreno_dev->cp_init_cmds, 12 << 2);
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ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
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if (ret) {
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