From c802bb3a2338fcd728f4b664467faf2536b93133 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Wed, 20 Jan 2021 14:10:21 +0530 Subject: [PATCH] iommu: arm-smmu: optimize arch write sync delay With ARM_SMMU_POWER_ALWAYS_ON enabled, clocks are always on. There arch write sync is not required. Move arch write sync post checking for clock refcount. Arch write sync takes longer due to virtualized global register read. Use non virtuazlied global register to reduce read latency. Change-Id: Ic497c7ba75cc8ba2ed804f2c987e0c595487ce40 Signed-off-by: Prakash Gupta --- drivers/iommu/arm-smmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index e4335cdc995b..2303b82aedf4 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -365,7 +365,8 @@ static void arm_smmu_arch_write_sync(struct arm_smmu_device *smmu) return; /* Read to complete prior write transcations */ - id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID0); + id = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF0, 0); + /* Wait for read to complete before off */ rmb(); @@ -656,8 +657,6 @@ static void arm_smmu_power_off_atomic(struct arm_smmu_device *smmu, { unsigned long flags; - arm_smmu_arch_write_sync(smmu); - spin_lock_irqsave(&pwr->clock_refs_lock, flags); if (pwr->clock_refs_count == 0) { WARN(1, "%s: bad clock_ref_count\n", dev_name(pwr->dev)); @@ -670,6 +669,7 @@ static void arm_smmu_power_off_atomic(struct arm_smmu_device *smmu, return; } + arm_smmu_arch_write_sync(smmu); arm_smmu_disable_clocks(pwr); pwr->clock_refs_count = 0;