From 760bd4ab468761c1cf71887f75ddda4b33fe834b Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 22 Sep 2020 16:06:33 +0530 Subject: [PATCH] soc: swr-mstr: Check for fifo avail before bulk write Check for fifo availability before writing slave registers during swrm master bulk write so as to prevent swr overflow, underflow errors. Change-Id: I97a914cac289b3f1215ccf5c1abec88b959a9f21 Signed-off-by: Vatsal Bucha --- soc/swr-mstr-ctrl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index 6e9b7c1eec01..94325bea6307 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -129,6 +129,7 @@ static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm); static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr); static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val); static int swrm_runtime_resume(struct device *dev); +static void swrm_wait_for_fifo_avail(struct swr_mstr_ctrl *swrm, int swrm_rd_wr); static u64 swrm_phy_dev[] = { 0, @@ -678,6 +679,9 @@ static int swr_master_bulk_write(struct swr_mstr_ctrl *swrm, u32 *reg_addr, * This still meets the hardware spec */ usleep_range(50, 55); + if (reg_addr[i] == SWRM_CMD_FIFO_WR_CMD) + swrm_wait_for_fifo_avail(swrm, + SWRM_WR_CHECK_AVAIL); swr_master_write(swrm, reg_addr[i], val[i]); } usleep_range(100, 110);