From 76296974fd6d7da0540a39ec73a87cfbbbbe6ad6 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Wed, 9 Dec 2020 10:19:49 -0800 Subject: [PATCH] iommu/arm-smmu: Fix io-coherency enablement for clients using S1 bypass When a context bank's SCTLR is programmed for an SMMU client that wishes to bypass S1 translations and enable io-coherency, the SHCFG bitfield of the SCTLR is set to 0. This means that a client's transaction's shareability memory attribute will not be modified as it goes through the SMMU. This is problematic if the SMMU client's transaction is marked as non-shareable, as the attribute will not be modified to be classified as io-coherent, since io-coherent transactions should be cacheable and shareable. Instead, the transaction will not snoop the CPU caches, and will go to DDR, and may read incorrect data. Thus, program the SHCFG bitfield in the context bank's SCTLR to override the shareability attribute to outer shareable when enabling io-coherency for clients using S1 bypass. Change-Id: Ia4c1bbe7812ce7c2062c636e2b1bb39fa1ac516c Signed-off-by: Isaac J. Manjarres --- drivers/iommu/arm-smmu.c | 1 + drivers/iommu/arm-smmu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index ebca72dec632..56bf0c97237d 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1715,6 +1715,7 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx, reg |= FIELD_PREP(SCTLR_WACFG, SCTLR_WACFG_WA) | FIELD_PREP(SCTLR_RACFG, SCTLR_RACFG_RA) | + FIELD_PREP(SCTLR_SHCFG, SCTLR_SHCFG_OSH) | SCTLR_MTCFG | FIELD_PREP(SCTLR_MEM_ATTR, SCTLR_MEM_ATTR_OISH_WB_CACHE); } else { diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index 4f8127b2ee45..14a550ed6aa3 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -153,6 +153,7 @@ enum arm_smmu_cbar_type { #define SCTLR_RACFG GENMASK(25, 24) #define SCTLR_RACFG_RA 0x2 #define SCTLR_SHCFG GENMASK(23, 22) +#define SCTLR_SHCFG_OSH 0x1 #define SCTLR_SHCFG_NSH 0x3 #define SCTLR_MTCFG BIT(20) #define SCTLR_MEM_ATTR GENMASK(19, 16)