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qcacmn: Add antenna gain to per regdomain structure

Browse source 
Antenna gains are added to per regdomain structure. Howerver,
during parsing they are copied to per current reg rule and
finally to per channel.

Change-Id: Ib456248e2dee26ed3b2a9878d1b27fc5c9827e81
CRs-Fixed: 2002892
This commit is contained in:
Pradhan, Abhijit 2017-05-04 19:48:31 +05:30 • committed by Gerrit - the friendly Code Review server
commit 7644ff44b0
4 changed files with 58 additions and 38 deletions
Download patch file Download diff file Expand all files Collapse all files

72
umac/regulatory/core/src/reg_db.c
View file

@ -663,15 +663,15 @@ const struct regulatory_rule reg_rules_2g[] = {
const struct regdomain regdomains_2g[] = {
[FCCA] = {CTL_FCC, DFS_UNINIT_REG, 0, 1, {CHAN_1_11_1} },
[WORLD] = {CTL_ETSI, DFS_UNINIT_REG, 0, 1, {CHAN_1_13_1} },
[MKKA] = {CTL_MKK, DFS_UNINIT_REG, 0, 2, {CHAN_1_13_1, CHAN_14_1} },
[MKKC] = {CTL_MKK, DFS_UNINIT_REG, 0, 1, {CHAN_1_13_1} },
[ETSIC] = {CTL_ETSI, DFS_UNINIT_REG, 0, 1, {CHAN_1_13_2} },
[WORLD_2G_1] = {CTL_FCC, DFS_UNINIT_REG, 0, 1, {CHAN_1_11_2} },
[WORLD_2G_2] = {CTL_FCC, DFS_UNINIT_REG, 0, 2,
[FCCA] = {CTL_FCC, DFS_UNINIT_REG, 0, 6, 1, {CHAN_1_11_1} },
[WORLD] = {CTL_ETSI, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_1} },
[MKKA] = {CTL_MKK, DFS_UNINIT_REG, 0, 0, 2, {CHAN_1_13_1, CHAN_14_1} },
[MKKC] = {CTL_MKK, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_1} },
[ETSIC] = {CTL_ETSI, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_2} },
[WORLD_2G_1] = {CTL_FCC, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_11_2} },
[WORLD_2G_2] = {CTL_FCC, DFS_UNINIT_REG, 0, 0, 2,
{CHAN_1_11_2, CHAN_12_13_1} },
[WORLD_2G_3] = {CTL_FCC, DFS_UNINIT_REG, 0, 3,
[WORLD_2G_3] = {CTL_FCC, DFS_UNINIT_REG, 0, 0, 3,
{CHAN_1_11_2, CHAN_12_13_1, CHAN_14_2} },
};
@ -745,115 +745,115 @@ const struct regulatory_rule reg_rules_5g[] = {
const struct regdomain regdomains_5g[] = {
[FCC1] = {CTL_FCC, DFS_FCC_REG, 2, 3, {CHAN_5170_5250_1,
[FCC1] = {CTL_FCC, DFS_FCC_REG, 2, 6, 3, {CHAN_5170_5250_1,
CHAN_5250_5330_1,
CHAN_5735_5835_1} },
[FCC2] = {CTL_FCC, DFS_CN_REG, 2, 3, {CHAN_5170_5250_2,
[FCC2] = {CTL_FCC, DFS_CN_REG, 2, 6, 3, {CHAN_5170_5250_2,
CHAN_5250_5330_1,
CHAN_5735_5835_1} },
[FCC3] = {CTL_FCC, DFS_FCC_REG, 2, 4, {CHAN_5170_5250_2,
[FCC3] = {CTL_FCC, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_2,
CHAN_5250_5330_1,
CHAN_5490_5730_1,
CHAN_5735_5835_1} },
[FCC4] = {CTL_FCC, DFS_FCC_REG, 2, 4, {CHAN_4940_4990_1,
[FCC4] = {CTL_FCC, DFS_FCC_REG, 2, 6, 4, {CHAN_4940_4990_1,
CHAN_5170_5250_1,
CHAN_5250_5330_1,
CHAN_5735_5835_1} },
[FCC6] = {CTL_FCC, DFS_FCC_REG, 2, 5, {CHAN_5170_5250_2,
[FCC6] = {CTL_FCC, DFS_FCC_REG, 2, 6, 5, {CHAN_5170_5250_2,
CHAN_5250_5330_1,
CHAN_5490_5590_1,
CHAN_5650_5730_1,
CHAN_5735_5835_1} },
[FCC8] = {CTL_FCC, DFS_FCC_REG, 2, 4, {CHAN_5170_5250_4,
[FCC8] = {CTL_FCC, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_4,
CHAN_5250_5330_1,
CHAN_5490_5730_1,
CHAN_5735_5835_1} },
[ETSI1] = {CTL_ETSI, DFS_ETSI_REG, 5, 3, {CHAN_5170_5250_2,
[ETSI1] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 3, {CHAN_5170_5250_2,
CHAN_5250_5330_1,
CHAN_5490_5710_1} },
[ETSI3] = {CTL_ETSI, DFS_ETSI_REG, 5, 2, {CHAN_5170_5250_3,
[ETSI3] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 2, {CHAN_5170_5250_3,
CHAN_5250_5330_2} },
[ETSI4] = {CTL_ETSI, DFS_ETSI_REG, 5, 2, {CHAN_5170_5250_1,
[ETSI4] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 2, {CHAN_5170_5250_1,
CHAN_5250_5330_3} },
[ETSI8] = {CTL_ETSI, DFS_ETSI_REG, 20, 4, {CHAN_5170_5250_3,
[ETSI8] = {CTL_ETSI, DFS_ETSI_REG, 20, 0, 4, {CHAN_5170_5250_3,
CHAN_5250_5330_2,
CHAN_5490_5730_2,
CHAN_5735_5835_2} },
[ETSI9] = {CTL_ETSI, DFS_ETSI_REG, 20, 4, {CHAN_5170_5250_3,
[ETSI9] = {CTL_ETSI, DFS_ETSI_REG, 20, 0, 4, {CHAN_5170_5250_3,
CHAN_5250_5330_2,
CHAN_5490_5670_1,
CHAN_5735_5835_3} },
[APL1] = {CTL_ETSI, DFS_UNINIT_REG, 2, 1, {CHAN_5735_5835_2} },
[APL1] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5735_5835_2} },
[APL2] = {CTL_ETSI, DFS_UNINIT_REG, 2, 1, {CHAN_5735_5815_1} },
[APL2] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5735_5815_1} },
[APL4] = {CTL_ETSI, DFS_UNINIT_REG, 2, 2, {CHAN_5170_5250_2,
[APL4] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 2, {CHAN_5170_5250_2,
CHAN_5735_5835_1} },
[APL6] = {CTL_ETSI, DFS_ETSI_REG, 2, 3, {CHAN_5170_5250_3,
[APL6] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 3, {CHAN_5170_5250_3,
CHAN_5250_5330_2,
CHAN_5735_5835_3} },
[APL8] = {CTL_ETSI, DFS_ETSI_REG, 2, 2, {CHAN_5250_5330_4,
[APL8] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 2, {CHAN_5250_5330_4,
CHAN_5735_5835_2} },
[APL9] = {CTL_ETSI, DFS_KR_REG, 2, 4, {CHAN_5170_5250_3,
[APL9] = {CTL_ETSI, DFS_KR_REG, 2, 6, 4, {CHAN_5170_5250_3,
CHAN_5250_5330_2,
CHAN_5490_5630_1,
CHAN_5735_5815_1} },
[APL10] = {CTL_ETSI, DFS_ETSI_REG, 2, 4, {CHAN_5170_5250_3,
[APL10] = {CTL_ETSI, DFS_ETSI_REG, 2, 6, 4, {CHAN_5170_5250_3,
CHAN_5250_5330_2,
CHAN_5490_5710_1,
CHAN_5735_5815_1} },
[APL12] = {CTL_ETSI, DFS_ETSI_REG, 2, 3, {CHAN_5170_5250_1,
[APL12] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 3, {CHAN_5170_5250_1,
CHAN_5490_5570_1,
CHAN_5735_5775_1} },
[APL14] = {CTL_FCC, DFS_CN_REG, 2, 3, {CHAN_5170_5250_2,
[APL14] = {CTL_FCC, DFS_CN_REG, 2, 0, 3, {CHAN_5170_5250_2,
CHAN_5250_5330_1,
CHAN_5735_5835_4} },
[MKK3] = {CTL_MKK, DFS_UNINIT_REG, 2, 1, {CHAN_5170_5250_3} },
[MKK3] = {CTL_MKK, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5170_5250_3} },
[MKK4] = {CTL_MKK, DFS_MKK_REG, 2, 2, {CHAN_5170_5250_3,
[MKK4] = {CTL_MKK, DFS_MKK_REG, 2, 0, 2, {CHAN_5170_5250_3,
CHAN_5250_5330_2} },
[MKK5] = {CTL_MKK, DFS_MKK_REG, 2, 3, {CHAN_5170_5250_3,
[MKK5] = {CTL_MKK, DFS_MKK_REG, 2, 0, 3, {CHAN_5170_5250_3,
CHAN_5250_5330_2,
CHAN_5490_5710_2} },
[MKK9] = {CTL_MKK, DFS_UNINIT_REG, 2, 3, {CHAN_5170_5250_3,
[MKK9] = {CTL_MKK, DFS_UNINIT_REG, 2, 0, 3, {CHAN_5170_5250_3,
CHAN_4910_4990_1,
CHAN_5030_5090_1} },
[MKK10] = {CTL_MKK, DFS_MKK_REG, 2, 4, {CHAN_5170_5250_3,
[MKK10] = {CTL_MKK, DFS_MKK_REG, 2, 0, 4, {CHAN_5170_5250_3,
CHAN_5250_5330_2,
CHAN_4910_4990_1,
CHAN_5030_5090_1} },
[MKK11] = {CTL_MKK, DFS_MKK_REG, 2, 5, {CHAN_5170_5250_3,
[MKK11] = {CTL_MKK, DFS_MKK_REG, 2, 0, 5, {CHAN_5170_5250_3,
CHAN_5250_5330_2,
CHAN_5490_5710_2,
CHAN_4910_4990_1,
CHAN_5030_5090_1} },
[WORLD_5G_1] = {CTL_FCC, DFS_UNINIT_REG, 2, 2, {CHAN_5170_5330_1,
[WORLD_5G_1] = {CTL_FCC, DFS_UNINIT_REG, 2, 0, 2, {CHAN_5170_5330_1,
CHAN_5735_5835_5} },
[WORLD_5G_2] = {CTL_FCC, DFS_UNINIT_REG, 2, 3, {CHAN_5170_5330_1,
[WORLD_5G_2] = {CTL_FCC, DFS_UNINIT_REG, 2, 0, 3, {CHAN_5170_5330_1,
CHAN_5490_5730_3,
CHAN_5735_5835_5} },
};

1
umac/regulatory/core/src/reg_db.h
View file

@ -95,6 +95,7 @@ struct regdomain {
uint8_t ctl_val;
enum dfs_reg dfs_region;
uint16_t min_bw;
uint8_t ant_gain;
uint8_t num_reg_rules;
uint8_t reg_rule_id[MAX_REG_RULES];
};

21
umac/regulatory/core/src/reg_db_parser.c
View file

@ -47,6 +47,8 @@ QDF_STATUS reg_is_country_code_valid(uint8_t alpha[3])
QDF_STATUS reg_regrules_assign(uint8_t dmn_id_2g,
uint8_t dmn_id_5g,
uint8_t ant_gain_2g,
uint8_t ant_gain_5g,
struct cur_regulatory_info *reg_info)
{
@ -62,6 +64,7 @@ QDF_STATUS reg_regrules_assign(uint8_t dmn_id_2g,
r_r_2g->max_bw = reg_rules_2g[rule_index].max_bw;
r_r_2g->reg_power = reg_rules_2g[rule_index].reg_power;
r_r_2g->flags = reg_rules_2g[rule_index].flags;
r_r_2g->ant_gain = ant_gain_2g;
r_r_2g++;
}
@ -72,6 +75,7 @@ QDF_STATUS reg_regrules_assign(uint8_t dmn_id_2g,
r_r_5g->max_bw = reg_rules_5g[rule_index].max_bw;
r_r_5g->reg_power = reg_rules_5g[rule_index].reg_power;
r_r_5g->flags = reg_rules_5g[rule_index].flags;
r_r_2g->ant_gain = ant_gain_5g;
r_r_5g++;
}
@ -186,6 +190,7 @@ static inline QDF_STATUS reg_get_reginfo_form_country_code_and_regdmn_pair(
{
uint8_t rule_size_2g, rule_size_5g;
uint8_t dmn_id_5g, dmn_id_2g;
uint8_t ant_gain_2g, ant_gain_5g;
dmn_id_5g = g_reg_dmn_pairs[regdmn_pair].dmn_id_5g;
dmn_id_2g = g_reg_dmn_pairs[regdmn_pair].dmn_id_2g;
@ -204,12 +209,16 @@ static inline QDF_STATUS reg_get_reginfo_form_country_code_and_regdmn_pair(
reg_info->dfs_region = regdomains_5g[dmn_id_5g].dfs_region;
reg_info->phybitmap =
g_all_countries[country_index].phymode_bitmap;
reg_info->max_bw_2g = g_all_countries[country_index].max_bw_2g;
reg_info->max_bw_5g = g_all_countries[country_index].max_bw_5g;
reg_info->min_bw_2g = regdomains_2g[dmn_id_2g].min_bw;
reg_info->min_bw_5g = regdomains_5g[dmn_id_5g].min_bw;
ant_gain_2g = regdomains_2g[dmn_id_2g].ant_gain;
ant_gain_5g = regdomains_5g[dmn_id_5g].ant_gain;
reg_info->num_2g_reg_rules =
regdomains_2g[dmn_id_2g].num_reg_rules;
reg_info->num_5g_reg_rules =
@ -222,7 +231,8 @@ static inline QDF_STATUS reg_get_reginfo_form_country_code_and_regdmn_pair(
qdf_mem_malloc((reg_info->num_5g_reg_rules) *
sizeof(struct cur_reg_rule));
reg_regrules_assign(dmn_id_2g, dmn_id_5g, reg_info);
reg_regrules_assign(dmn_id_2g, dmn_id_5g,
ant_gain_2g, ant_gain_5g, reg_info);
return QDF_STATUS_SUCCESS;
} else if (!(((rule_size_2g + rule_size_5g) >=
@ -239,6 +249,7 @@ static inline QDF_STATUS reg_get_reginfo_form_regdmn_pair(
{
uint8_t rule_size_2g, rule_size_5g;
uint8_t dmn_id_5g, dmn_id_2g;
uint8_t ant_gain_2g, ant_gain_5g;
dmn_id_5g = g_reg_dmn_pairs[regdmn_pair].dmn_id_5g;
dmn_id_2g = g_reg_dmn_pairs[regdmn_pair].dmn_id_2g;
@ -254,11 +265,16 @@ static inline QDF_STATUS reg_get_reginfo_form_regdmn_pair(
reg_info->dfs_region = regdomains_5g[dmn_id_5g].dfs_region;
reg_info->phybitmap = 0;
reg_info->max_bw_2g = 40;
reg_info->max_bw_5g = 160;
reg_info->min_bw_2g = regdomains_2g[dmn_id_2g].min_bw;
reg_info->min_bw_5g = regdomains_5g[dmn_id_5g].min_bw;
ant_gain_2g = regdomains_2g[dmn_id_2g].ant_gain;
ant_gain_5g = regdomains_5g[dmn_id_5g].ant_gain;
reg_info->num_2g_reg_rules =
regdomains_2g[dmn_id_2g].num_reg_rules;
reg_info->num_5g_reg_rules =
@ -271,7 +287,8 @@ static inline QDF_STATUS reg_get_reginfo_form_regdmn_pair(
qdf_mem_malloc((reg_info->num_5g_reg_rules) *
sizeof(struct cur_reg_rule));
reg_regrules_assign(dmn_id_2g, dmn_id_5g, reg_info);
reg_regrules_assign(dmn_id_2g, dmn_id_5g,
ant_gain_2g, ant_gain_5g, reg_info);
return QDF_STATUS_SUCCESS;
} else if (!(((rule_size_2g + rule_size_5g) >=

2
umac/regulatory/core/src/reg_db_parser.h
View file

@ -35,6 +35,8 @@ QDF_STATUS reg_is_country_code_valid(uint8_t alpha[3]);
QDF_STATUS reg_regrules_assign(uint8_t dmn_id_2g,
uint8_t dmn_id_5g,
uint8_t ant_gain_2g,
uint8_t ant_gain_5g,
struct cur_regulatory_info *reg_info);
QDF_STATUS reg_get_cur_reginfo(struct cur_regulatory_info *reg_info,