From ee63c069ee5f44c89c2cb5d63407f9deb543860f Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Fri, 5 Mar 2021 13:33:03 -0800 Subject: [PATCH 1/2] ARM: dts: msm: Update load factor for PCIe rail on sdxlemur Changes to the devicetree property to reflect the updated load factor for the 1.2V PCIe rail. Change-Id: Id8ce153b810b25f4620daeddddb3c300efab9e8f --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a90d8dd61418..23e309427507 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -926,7 +926,7 @@ vreg-1p8-supply = <&pmx65_l1>; vreg-0p9-supply = <&pmx65_l4>; - qcom,vreg-1p8-voltage-level = <1200000 1200000 3000>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; qcom,vreg-0p9-voltage-level = <912000 912000 132000>; clocks = <&gcc GCC_PCIE_PIPE_CLK>, From 13734717cbeca1f058057d95f517a499c010f898 Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Tue, 9 Mar 2021 14:45:17 -0800 Subject: [PATCH 2/2] ARM: dts: msm: Add MX property for PCIe on sdxlemur Update the bindings document to include the devicetree property needed to scale the MX voltage to support the PCIe Gen4 controller for sdxlemur. Change-Id: I9b5b9f9cda70456a9c7af06adee498fa713d1f39 --- bindings/pci/msm_ep_pcie.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/pci/msm_ep_pcie.txt b/bindings/pci/msm_ep_pcie.txt index c364f472cc0b..425bddc9533d 100644 --- a/bindings/pci/msm_ep_pcie.txt +++ b/bindings/pci/msm_ep_pcie.txt @@ -33,6 +33,8 @@ Required properties: Optional Properties: - qcom,-voltage-level: specifies voltage levels for supply. Should be specified in pairs (max, min, optimal), units uV. + - qcom,vreg-mx-voltage-level: Support PCIe Gen4 on sdxlemur by scaling MX to + appropriate voltage. - clock-names: list of names of clock inputs. Should be "pcie_pipe_clk", "pcie_aux_clk", "pcie_cfg_ahb_clk",