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msm: vidc: Amend DCVS handling for encoder

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For DCVS, there are mainly 3 buffer count watermarks
i.e low, normal, high. When the buffers held with firmware
goes above high or below low, DCVS changes the clock to
high or low respectively.
At this state, to come back to normal clock, it needs the buffer
in firmware to come back to normal count. For cases, when DCVS
decides to decrease the clock, the clock remains lowered till
the buffer count in firmware is back to normal. During this
phase, the clock remains low and impacts performance. Since
encode usecase always desire more clock, keeping low for them
leads to measurable impact.
The fix considers a case for encoder to bring back to normal
clock when the buffer count is more than low watermark.

CRs-Fixed: 2845570
Change-Id: I426a17f7b16db544ea09ec072c77e95198634c84
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
This commit is contained in:
Vikash Garodia 2021-01-07 12:44:31 +05:30
commit 76cae5a345
1 changed files with 4 additions and 1 deletions
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5
msm/vidc/msm_vidc_clocks.c
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@ -525,7 +525,10 @@ static int msm_dcvs_scale_clocks(struct msm_vidc_inst *inst,
} else if ((dcvs->dcvs_flags & MSM_VIDC_DCVS_DECR &&
bufs_with_fw >= dcvs->nom_threshold) ||
(dcvs->dcvs_flags & MSM_VIDC_DCVS_INCR &&
bufs_with_fw <= dcvs->nom_threshold))
bufs_with_fw <= dcvs->nom_threshold) ||
(inst->session_type == MSM_VIDC_ENCODER &&
dcvs->dcvs_flags & MSM_VIDC_DCVS_DECR &&
bufs_with_fw >= dcvs->min_threshold))
dcvs->dcvs_flags = 0;
s_vpr_p(inst->sid, "DCVS: bufs_with_fw %d Th[%d %d %d] Flag %#x\n",