Merge "clk: qcom: gcc: Add support for GCC clock Driver for sdxnightjar"

drivers/clk/qcom/debugcc-sdxnightjar.c

@@ -103,6 +103,8 @@ static const char *const gcc_debug_mux_parent_names[] = {
 	"gcc_usb3_pipe_clk",
 	"gcc_usb_phy_cfg_ahb_clk",
 	"gcc_xo_div4_clk",
+	"gcc_mss_q6_bimc_axi_clk",
+	"gcc_mss_cfg_ahb_clk",
 	"measure_only_bimc_clk",
 	"measure_only_ce_clk",
 	"measure_only_ipa_clk",
@@ -156,6 +158,8 @@ static int gcc_debug_mux_sels[] = {
 	0x234,		/* gcc_usb3_pipe_clk */
 	0x233,		/* gcc_usb_phy_cfg_ahb_clk */
 	0x14A,		/* gcc_xo_div4_clk */
+	0x31,		/* gcc_mss_q6_bimc_axi_clk */
+	0x30,		/* gcc_mss_cfg_ahb_clk */
 	0x155,		/* measure_only_bimc_clk */
 	0x138,		/* measure_only_ce_clk */
 	0x218,		/* measure_only_ipa_clk */

drivers/clk/qcom/gcc-sdxnightjar.c

@@ -1444,6 +1444,32 @@ static struct clk_branch gcc_xo_div4_clk = {
 	},
 };
 
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+	.halt_reg = 0x49004,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x49004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_mss_q6_bimc_axi_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
+	.halt_reg = 0x49000,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x49000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_mss_cfg_ahb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_regmap *gcc_sdxnightjar_clocks[] = {
 	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
 	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
@@ -1503,6 +1529,8 @@ static struct clk_regmap *gcc_sdxnightjar_clocks[] = {
 	[GCC_USB_PHY_CFG_AHB_CLK] = &gcc_usb_phy_cfg_ahb_clk.clkr,
 	[GCC_USB_SS_REF_CLK] = &gcc_usb_ss_ref_clk.clkr,
 	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
+	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
+	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
 	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
 	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
 	[GP3_CLK_SRC] = &gp3_clk_src.clkr,

include/dt-bindings/clock/qcom,gcc-sdxnightjar.h

@@ -78,6 +78,8 @@
 #define USB30_MOCK_UTMI_CLK_SRC					68
 #define USB3_AUX_CLK_SRC					69
 #define APSS_AHB_CLK_SRC					70
+#define GCC_MSS_Q6_BIMC_AXI_CLK					71
+#define GCC_MSS_CFG_AHB_CLK					72
 
 /* GCC resets */
 #define GCC_PCIEPHY_PHY_BCR					0