From 77b9ca9416b791cd4a9b5ace397a3fb3bd2c7b4f Mon Sep 17 00:00:00 2001
From: Mao Jinlong <jinlmao@qti.qualcomm.com>
Date: Tue, 11 Aug 2020 10:43:09 +0800
Subject: [PATCH] ARM: dts: msm: Add correct cti config to tmc etr/etf for
 lahaina

Add correct cti config for the tmc etr/etf reset cti trigin and cti flush
trigout.

Change-Id: I54088b890d24799a040f0951e41e98be0cc393a6
---
 qcom/lahaina-coresight.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi
index cac602552fcf..b4f244d5cc9e 100644
--- a/qcom/lahaina-coresight.dtsi
+++ b/qcom/lahaina-coresight.dtsi
@@ -107,6 +107,7 @@
 
 		coresight-name = "coresight-tmc-etf";
 		coresight-csr = <&swao_csr>;
+		coresight-ctis = <&cti0_swao &cti3_swao>;
 		clocks = <&clock_aop QDSS_CLK>;
 		clock-names = "apb_pclk";
 
@@ -153,7 +154,7 @@
 
 		qcom,sw-usb;
 		coresight-name = "coresight-tmc-etr";
-		coresight-ctis = <&cti0 &cti0>;
+		coresight-ctis = <&cti0 &cti3_swao>;
 		coresight-csr = <&csr>;
 
 		clocks = <&clock_aop QDSS_CLK>;