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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 23:24:22 -04:00
PM / devfreq: bw_hwmon: Split out sw and hw paths
Let's split out the sw and hw counter configuration code paths indicated by has_hw_sampling() into inline functions for the two different types of monitors. This allows us to add different types of monitors in the future with minimal changes. Change-Id: I5cf6a1fe4d84ee0958fe68601cb1e76836d10256 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [avajid@codeaurora.org: minor change to check ret < 0] Signed-off-by: Amir Vajid <avajid@codeaurora.org>
This commit is contained in:
Stephen Boyd
Amir Vajid
parent
e1b5bffc44
commit
77d4c0bb9c
1 changed files with 302 additions and 115 deletions
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@ -46,6 +46,11 @@
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#define MON2_ZONE_CNT(m) ((m)->base + 0x2D8)
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#define MON2_ZONE_MAX(m, zone) ((m)->base + 0x2E0 + 0x4 * zone)
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enum mon_reg_type {
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MON1,
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MON2,
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};
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struct bwmon_spec {
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bool wrap_on_thres;
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bool overflow;
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@ -68,7 +73,6 @@ struct bwmon {
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};
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#define to_bwmon(ptr) container_of(ptr, struct bwmon, hw)
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#define has_hw_sampling(m) (m->spec->hw_sampling)
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#define ENABLE_MASK BIT(0)
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#define THROTTLE_MASK 0x1F
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@ -78,20 +82,29 @@ struct bwmon {
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#define INT_STATUS_MASK_HWS 0xF0
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static DEFINE_SPINLOCK(glb_lock);
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static void mon_enable(struct bwmon *m)
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static __always_inline void mon_enable(struct bwmon *m, enum mon_reg_type type)
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{
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if (has_hw_sampling(m))
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writel_relaxed((ENABLE_MASK | m->throttle_adj), MON2_EN(m));
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else
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writel_relaxed((ENABLE_MASK | m->throttle_adj), MON_EN(m));
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switch (type) {
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case MON1:
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writel_relaxed(ENABLE_MASK | m->throttle_adj, MON_EN(m));
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break;
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case MON2:
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writel_relaxed(ENABLE_MASK | m->throttle_adj, MON2_EN(m));
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break;
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}
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}
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static void mon_disable(struct bwmon *m)
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static __always_inline void mon_disable(struct bwmon *m, enum mon_reg_type type)
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{
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if (has_hw_sampling(m))
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writel_relaxed(m->throttle_adj, MON2_EN(m));
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else
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switch (type) {
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case MON1:
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writel_relaxed(m->throttle_adj, MON_EN(m));
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break;
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case MON2:
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writel_relaxed(m->throttle_adj, MON2_EN(m));
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break;
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}
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/*
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* mon_disable() and mon_irq_clear(),
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* If latter goes first and count happen to trigger irq, we would
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@ -102,24 +115,25 @@ static void mon_disable(struct bwmon *m)
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#define MON_CLEAR_BIT 0x1
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#define MON_CLEAR_ALL_BIT 0x2
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static void mon_clear(struct bwmon *m, bool clear_all)
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static __always_inline
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void mon_clear(struct bwmon *m, bool clear_all, enum mon_reg_type type)
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{
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if (!has_hw_sampling(m)) {
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switch (type) {
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case MON1:
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writel_relaxed(MON_CLEAR_BIT, MON_CLEAR(m));
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goto out;
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break;
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case MON2:
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if (clear_all)
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writel_relaxed(MON_CLEAR_ALL_BIT, MON2_CLEAR(m));
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else
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writel_relaxed(MON_CLEAR_BIT, MON2_CLEAR(m));
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break;
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}
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if (clear_all)
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writel_relaxed(MON_CLEAR_ALL_BIT, MON2_CLEAR(m));
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else
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writel_relaxed(MON_CLEAR_BIT, MON2_CLEAR(m));
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/*
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* The counter clear and IRQ clear bits are not in the same 4KB
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* region. So, we need to make sure the counter clear is completed
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* before we try to clear the IRQ or do any other counter operations.
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*/
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out:
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mb();
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}
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@ -140,74 +154,141 @@ static void mon_set_hw_sampling_window(struct bwmon *m, unsigned int sample_ms)
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}
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}
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static void mon_irq_enable(struct bwmon *m)
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static void mon_glb_irq_enable(struct bwmon *m)
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{
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u32 val;
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spin_lock(&glb_lock);
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val = readl_relaxed(GLB_INT_EN(m));
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val |= 1 << m->mport;
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writel_relaxed(val, GLB_INT_EN(m));
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val = readl_relaxed(MON_INT_EN(m));
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val |= has_hw_sampling(m) ? INT_STATUS_MASK_HWS : INT_ENABLE_V1;
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writel_relaxed(val, MON_INT_EN(m));
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spin_unlock(&glb_lock);
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/*
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* make Sure irq enable complete for local and global
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* to avoid race with other monitor calls
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*/
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mb();
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}
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static void mon_irq_disable(struct bwmon *m)
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static __always_inline
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void mon_irq_enable(struct bwmon *m, enum mon_reg_type type)
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{
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u32 val;
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spin_lock(&glb_lock);
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val = readl_relaxed(GLB_INT_EN(m));
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val &= ~(1 << m->mport);
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writel_relaxed(val, GLB_INT_EN(m));
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val = readl_relaxed(MON_INT_EN(m));
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val &= has_hw_sampling(m) ? ~INT_STATUS_MASK_HWS : ~INT_ENABLE_V1;
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writel_relaxed(val, MON_INT_EN(m));
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switch (type) {
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case MON1:
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mon_glb_irq_enable(m);
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val = readl_relaxed(MON_INT_EN(m));
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val |= INT_ENABLE_V1;
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writel_relaxed(val, MON_INT_EN(m));
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break;
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case MON2:
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mon_glb_irq_enable(m);
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val = readl_relaxed(MON_INT_EN(m));
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val |= INT_STATUS_MASK_HWS;
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writel_relaxed(val, MON_INT_EN(m));
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break;
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}
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spin_unlock(&glb_lock);
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/*
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* make Sure irq disable complete for local and global
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* make sure irq enable complete for local and global
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* to avoid race with other monitor calls
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*/
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mb();
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}
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static unsigned int mon_irq_status(struct bwmon *m)
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static void mon_glb_irq_disable(struct bwmon *m)
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{
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u32 val;
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val = readl_relaxed(GLB_INT_EN(m));
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val &= ~(1 << m->mport);
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writel_relaxed(val, GLB_INT_EN(m));
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}
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static __always_inline
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void mon_irq_disable(struct bwmon *m, enum mon_reg_type type)
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{
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u32 val;
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spin_lock(&glb_lock);
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switch (type) {
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case MON1:
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mon_glb_irq_disable(m);
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val = readl_relaxed(MON_INT_EN(m));
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val &= ~INT_ENABLE_V1;
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writel_relaxed(val, MON_INT_EN(m));
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break;
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case MON2:
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mon_glb_irq_disable(m);
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val = readl_relaxed(MON_INT_EN(m));
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val &= ~INT_STATUS_MASK_HWS;
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writel_relaxed(val, MON_INT_EN(m));
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break;
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}
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spin_unlock(&glb_lock);
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/*
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* make sure irq disable complete for local and global
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* to avoid race with other monitor calls
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*/
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mb();
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}
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static __always_inline
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unsigned int mon_irq_status(struct bwmon *m, enum mon_reg_type type)
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{
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u32 mval;
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mval = readl_relaxed(MON_INT_STATUS(m));
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dev_dbg(m->dev, "IRQ status p:%x, g:%x\n", mval,
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readl_relaxed(GLB_INT_STATUS(m)));
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mval &= has_hw_sampling(m) ? INT_STATUS_MASK_HWS : INT_STATUS_MASK;
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switch (type) {
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case MON1:
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mval = readl_relaxed(MON_INT_STATUS(m));
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dev_dbg(m->dev, "IRQ status p:%x, g:%x\n", mval,
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readl_relaxed(GLB_INT_STATUS(m)));
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mval &= INT_STATUS_MASK;
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break;
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case MON2:
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mval = readl_relaxed(MON_INT_STATUS(m));
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dev_dbg(m->dev, "IRQ status p:%x, g:%x\n", mval,
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readl_relaxed(GLB_INT_STATUS(m)));
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mval &= INT_STATUS_MASK_HWS;
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break;
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}
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return mval;
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}
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static void mon_irq_clear(struct bwmon *m)
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static void mon_glb_irq_clear(struct bwmon *m)
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{
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u32 intclr;
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intclr = has_hw_sampling(m) ? INT_STATUS_MASK_HWS : INT_STATUS_MASK;
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writel_relaxed(intclr, MON_INT_CLR(m));
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/* Ensure the monitor IRQ is clear before clearing GLB IRQ */
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/*
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* Synchronize the local interrupt clear in mon_irq_clear()
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* with the global interrupt clear here. Otherwise, the CPU
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* may reorder the two writes and clear the global interrupt
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* before the local interrupt, causing the global interrupt
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* to be retriggered by the local interrupt still being high.
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*/
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mb();
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writel_relaxed(1 << m->mport, GLB_INT_CLR(m));
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/* Ensure the GLB IRQ clear is complete */
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/*
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* Similarly, because the global registers are in a different
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* region than the local registers, we need to ensure any register
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* writes to enable the monitor after this call are ordered with the
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* clearing here so that local writes don't happen before the
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* interrupt is cleared.
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*/
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mb();
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}
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static __always_inline
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void mon_irq_clear(struct bwmon *m, enum mon_reg_type type)
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{
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switch (type) {
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case MON1:
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writel_relaxed(INT_STATUS_MASK, MON_INT_CLR(m));
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mon_glb_irq_clear(m);
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break;
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case MON2:
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writel_relaxed(INT_STATUS_MASK_HWS, MON_INT_CLR(m));
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mon_glb_irq_clear(m);
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break;
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}
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}
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static int mon_set_throttle_adj(struct bw_hwmon *hw, uint adj)
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{
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struct bwmon *m = to_bwmon(hw);
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@ -325,12 +406,12 @@ static u32 mon_get_limit(struct bwmon *m)
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#define THRES_HIT(status) (status & BIT(0))
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#define OVERFLOW(status) (status & BIT(1))
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static unsigned long mon_get_count(struct bwmon *m)
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static unsigned long mon_get_count1(struct bwmon *m)
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{
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unsigned long count, status;
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count = readl_relaxed(MON_CNT(m));
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status = mon_irq_status(m);
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status = mon_irq_status(m, MON1);
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dev_dbg(m->dev, "Counter: %08lx\n", count);
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@ -379,6 +460,23 @@ static unsigned long mon_get_zone_stats(struct bwmon *m)
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return count;
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}
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static __always_inline
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unsigned long mon_get_count(struct bwmon *m, enum mon_reg_type type)
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{
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unsigned long count;
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switch (type) {
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case MON1:
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count = mon_get_count1(m);
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break;
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case MON2:
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count = mon_get_zone_stats(m);
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break;
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}
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return count;
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}
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/* ********** CPUBW specific code ********** */
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/* Returns MBps of read/writes for the sampling window. */
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@ -392,30 +490,41 @@ static unsigned int mbps_to_bytes(unsigned long mbps, unsigned int ms,
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return mbps;
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}
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static unsigned long get_bytes_and_clear(struct bw_hwmon *hw)
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static __always_inline
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unsigned long __get_bytes_and_clear(struct bw_hwmon *hw, enum mon_reg_type type)
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{
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struct bwmon *m = to_bwmon(hw);
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unsigned long count;
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mon_disable(m);
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count = has_hw_sampling(m) ? mon_get_zone_stats(m) : mon_get_count(m);
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mon_clear(m, false);
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mon_irq_clear(m);
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mon_enable(m);
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mon_disable(m, type);
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count = mon_get_count(m, type);
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mon_clear(m, false, type);
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mon_irq_clear(m, type);
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mon_enable(m, type);
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return count;
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}
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static unsigned long get_bytes_and_clear(struct bw_hwmon *hw)
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{
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return __get_bytes_and_clear(hw, MON1);
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}
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static unsigned long get_bytes_and_clear2(struct bw_hwmon *hw)
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{
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return __get_bytes_and_clear(hw, MON2);
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}
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static unsigned long set_thres(struct bw_hwmon *hw, unsigned long bytes)
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{
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unsigned long count;
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u32 limit;
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struct bwmon *m = to_bwmon(hw);
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mon_disable(m);
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count = mon_get_count(m);
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mon_clear(m, false);
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mon_irq_clear(m);
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mon_disable(m, MON1);
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count = mon_get_count1(m);
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mon_clear(m, false, MON1);
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mon_irq_clear(m, MON1);
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if (likely(!m->spec->wrap_on_thres))
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limit = bytes;
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@ -423,7 +532,7 @@ static unsigned long set_thres(struct bw_hwmon *hw, unsigned long bytes)
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limit = max(bytes, 500000UL);
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mon_set_limit(m, limit);
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mon_enable(m);
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mon_enable(m, MON1);
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return count;
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}
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@ -432,21 +541,22 @@ static unsigned long set_hw_events(struct bw_hwmon *hw, unsigned int sample_ms)
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{
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struct bwmon *m = to_bwmon(hw);
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mon_disable(m);
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mon_clear(m, false);
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mon_irq_clear(m);
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mon_disable(m, MON2);
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mon_clear(m, false, MON2);
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mon_irq_clear(m, MON2);
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mon_set_zones(m, sample_ms);
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mon_enable(m);
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mon_enable(m, MON2);
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return 0;
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}
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static irqreturn_t bwmon_intr_handler(int irq, void *dev)
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static irqreturn_t
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__bwmon_intr_handler(int irq, void *dev, enum mon_reg_type type)
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{
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struct bwmon *m = dev;
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m->intr_status = mon_irq_status(m);
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m->intr_status = mon_irq_status(m, type);
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if (!m->intr_status)
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return IRQ_NONE;
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@ -456,6 +566,16 @@ static irqreturn_t bwmon_intr_handler(int irq, void *dev)
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return IRQ_HANDLED;
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}
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static irqreturn_t bwmon_intr_handler(int irq, void *dev)
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{
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return __bwmon_intr_handler(irq, dev, MON1);
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}
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static irqreturn_t bwmon_intr_handler2(int irq, void *dev)
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{
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return __bwmon_intr_handler(irq, dev, MON2);
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}
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static irqreturn_t bwmon_intr_thread(int irq, void *dev)
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{
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struct bwmon *m = dev;
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@ -464,85 +584,150 @@ static irqreturn_t bwmon_intr_thread(int irq, void *dev)
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return IRQ_HANDLED;
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}
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static int start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps)
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static __always_inline int __start_bw_hwmon(struct bw_hwmon *hw,
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unsigned long mbps, enum mon_reg_type type)
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{
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struct bwmon *m = to_bwmon(hw);
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u32 limit;
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u32 zone_actions = calc_zone_actions();
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u32 limit, zone_actions;
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int ret;
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irq_handler_t handler;
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ret = request_threaded_irq(m->irq, bwmon_intr_handler,
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bwmon_intr_thread,
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switch (type) {
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case MON1:
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handler = bwmon_intr_handler;
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limit = mbps_to_bytes(mbps, hw->df->profile->polling_ms, 0);
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break;
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case MON2:
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zone_actions = calc_zone_actions();
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handler = bwmon_intr_handler2;
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break;
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}
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ret = request_threaded_irq(m->irq, handler, bwmon_intr_thread,
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IRQF_ONESHOT | IRQF_SHARED,
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dev_name(m->dev), m);
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if (ret < 0) {
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dev_err(m->dev, "Unable to register interrupt handler! (%d)\n",
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ret);
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ret);
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return ret;
|
||||
}
|
||||
|
||||
mon_disable(m);
|
||||
mon_disable(m, type);
|
||||
|
||||
mon_clear(m, true);
|
||||
limit = mbps_to_bytes(mbps, hw->df->profile->polling_ms, 0);
|
||||
if (has_hw_sampling(m)) {
|
||||
mon_clear(m, false, type);
|
||||
|
||||
switch (type) {
|
||||
case MON1:
|
||||
mon_set_limit(m, limit);
|
||||
break;
|
||||
case MON2:
|
||||
mon_set_zones(m, hw->df->profile->polling_ms);
|
||||
/* Set the zone actions to increment appropriate counters */
|
||||
writel_relaxed(zone_actions, MON2_ZONE_ACTIONS(m));
|
||||
} else {
|
||||
mon_set_limit(m, limit);
|
||||
break;
|
||||
}
|
||||
|
||||
mon_irq_clear(m);
|
||||
mon_irq_enable(m);
|
||||
mon_enable(m);
|
||||
mon_irq_clear(m, type);
|
||||
mon_irq_enable(m, type);
|
||||
mon_enable(m, type);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stop_bw_hwmon(struct bw_hwmon *hw)
|
||||
static int start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps)
|
||||
{
|
||||
return __start_bw_hwmon(hw, mbps, MON1);
|
||||
}
|
||||
|
||||
static int start_bw_hwmon2(struct bw_hwmon *hw, unsigned long mbps)
|
||||
{
|
||||
return __start_bw_hwmon(hw, mbps, MON2);
|
||||
}
|
||||
|
||||
static __always_inline
|
||||
void __stop_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type)
|
||||
{
|
||||
struct bwmon *m = to_bwmon(hw);
|
||||
|
||||
mon_irq_disable(m);
|
||||
mon_irq_disable(m, type);
|
||||
free_irq(m->irq, m);
|
||||
mon_disable(m);
|
||||
mon_clear(m, true);
|
||||
mon_irq_clear(m);
|
||||
mon_disable(m, type);
|
||||
mon_clear(m, true, type);
|
||||
mon_irq_clear(m, type);
|
||||
}
|
||||
|
||||
static void stop_bw_hwmon(struct bw_hwmon *hw)
|
||||
{
|
||||
return __stop_bw_hwmon(hw, MON1);
|
||||
}
|
||||
|
||||
static void stop_bw_hwmon2(struct bw_hwmon *hw)
|
||||
{
|
||||
return __stop_bw_hwmon(hw, MON2);
|
||||
}
|
||||
|
||||
static __always_inline
|
||||
int __suspend_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type)
|
||||
{
|
||||
struct bwmon *m = to_bwmon(hw);
|
||||
|
||||
mon_irq_disable(m, type);
|
||||
free_irq(m->irq, m);
|
||||
mon_disable(m, type);
|
||||
mon_irq_clear(m, type);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int suspend_bw_hwmon(struct bw_hwmon *hw)
|
||||
{
|
||||
struct bwmon *m = to_bwmon(hw);
|
||||
return __suspend_bw_hwmon(hw, MON1);
|
||||
}
|
||||
|
||||
mon_irq_disable(m);
|
||||
free_irq(m->irq, m);
|
||||
mon_disable(m);
|
||||
mon_irq_clear(m);
|
||||
static int suspend_bw_hwmon2(struct bw_hwmon *hw)
|
||||
{
|
||||
return __suspend_bw_hwmon(hw, MON2);
|
||||
}
|
||||
|
||||
static int __resume_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type)
|
||||
{
|
||||
struct bwmon *m = to_bwmon(hw);
|
||||
int ret;
|
||||
irq_handler_t handler;
|
||||
|
||||
switch (type) {
|
||||
case MON1:
|
||||
handler = bwmon_intr_handler;
|
||||
break;
|
||||
case MON2:
|
||||
handler = bwmon_intr_handler2;
|
||||
break;
|
||||
}
|
||||
|
||||
mon_clear(m, false, type);
|
||||
ret = request_threaded_irq(m->irq, handler, bwmon_intr_thread,
|
||||
IRQF_ONESHOT | IRQF_SHARED,
|
||||
dev_name(m->dev), m);
|
||||
if (ret < 0) {
|
||||
dev_err(m->dev, "Unable to register interrupt handler! (%d)\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
mon_irq_enable(m, type);
|
||||
mon_enable(m, type);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int resume_bw_hwmon(struct bw_hwmon *hw)
|
||||
{
|
||||
struct bwmon *m = to_bwmon(hw);
|
||||
int ret;
|
||||
return __resume_bw_hwmon(hw, MON1);
|
||||
}
|
||||
|
||||
mon_clear(m, false);
|
||||
ret = request_threaded_irq(m->irq, bwmon_intr_handler,
|
||||
bwmon_intr_thread,
|
||||
IRQF_ONESHOT | IRQF_SHARED,
|
||||
dev_name(m->dev), m);
|
||||
if (ret < 0) {
|
||||
dev_err(m->dev, "Unable to register interrupt handler! (%d)\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
mon_irq_enable(m);
|
||||
mon_enable(m);
|
||||
|
||||
return 0;
|
||||
static int resume_bw_hwmon2(struct bw_hwmon *hw)
|
||||
{
|
||||
return __resume_bw_hwmon(hw, MON2);
|
||||
}
|
||||
|
||||
/*************************************************************************/
|
||||
|
|
@ -608,17 +793,6 @@ static int bimc_bwmon_driver_probe(struct platform_device *pdev)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (has_hw_sampling(m)) {
|
||||
ret = of_property_read_u32(dev->of_node, "qcom,hw-timer-hz",
|
||||
&data);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "HW sampling rate not specified! (%d)\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
m->hw_timer_hz = data;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
|
||||
if (!res) {
|
||||
dev_err(dev, "base not found!\n");
|
||||
|
|
@ -651,15 +825,28 @@ static int bimc_bwmon_driver_probe(struct platform_device *pdev)
|
|||
if (!m->hw.of_node)
|
||||
return -EINVAL;
|
||||
|
||||
m->hw.start_hwmon = start_bw_hwmon;
|
||||
m->hw.stop_hwmon = stop_bw_hwmon;
|
||||
m->hw.suspend_hwmon = suspend_bw_hwmon;
|
||||
m->hw.resume_hwmon = resume_bw_hwmon;
|
||||
m->hw.get_bytes_and_clear = get_bytes_and_clear;
|
||||
m->hw.set_thres = set_thres;
|
||||
if (m->spec->hw_sampling) {
|
||||
ret = of_property_read_u32(dev->of_node, "qcom,hw-timer-hz",
|
||||
&m->hw_timer_hz);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "HW sampling rate not specified!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (has_hw_sampling(m))
|
||||
m->hw.start_hwmon = start_bw_hwmon2;
|
||||
m->hw.stop_hwmon = stop_bw_hwmon2;
|
||||
m->hw.suspend_hwmon = suspend_bw_hwmon2;
|
||||
m->hw.resume_hwmon = resume_bw_hwmon2;
|
||||
m->hw.get_bytes_and_clear = get_bytes_and_clear2;
|
||||
m->hw.set_hw_events = set_hw_events;
|
||||
} else {
|
||||
m->hw.start_hwmon = start_bw_hwmon;
|
||||
m->hw.stop_hwmon = stop_bw_hwmon;
|
||||
m->hw.suspend_hwmon = suspend_bw_hwmon;
|
||||
m->hw.resume_hwmon = resume_bw_hwmon;
|
||||
m->hw.get_bytes_and_clear = get_bytes_and_clear;
|
||||
m->hw.set_thres = set_thres;
|
||||
}
|
||||
|
||||
if (m->spec->throt_adj) {
|
||||
m->hw.set_throttle_adj = mon_set_throttle_adj;
|
||||
|
|
|
|||
Loading…
Reference in a new issue