A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-09 13:49:24 -04:00
Code Issues Projects Releases Packages Wiki Activity

Merge b770fe0aa5 on remote branch

Browse source 
Change-Id: Idbfb76d04540edf7de02c60fb7c06aa68975bfa7
This commit is contained in:
Linux Build Service Account 2022-01-27 07:40:27 -08:00
commit 77e4fcfe54
7 changed files with 202 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

10
config/dataipa.h
View file

@ -1,10 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define CONFIG_GSI 1
#define CONFIG_GSI_REGISTER_VERSION_2 1
#define CONFIG_RMNET_IPA3 1
#define CONFIG_RNDIS_IPA 1
#define CONFIG_IPA_WDI_UNIFIED_API 1
#define CONFIG_IPA3_REGDUMP 1
#define CONFIG_IPA3_APPS_REGDUMP 1
#define CONFIG_IPA3_REGDUMP_IPA_4_5 1
#define CONFIG_IPA3_4_5_RGSTR 0
#define CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS 0

4
config/dataipa_GKI.conf
View file

@ -4,3 +4,7 @@ export CONFIG_IPA_CLIENTS_MANAGER=m
export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y
export CONFIG_RNDIS_IPA=m
export CONFIG_IPA3_REGDUMP=y
export CONFIG_IPA3_APPS_REGDUMP=y
export CONFIG_IPA3_REGDUMP_IPA_4_5=y
export CONFIG_IPA3_4_5_RGSTR=n

4
config/dataipa_QGKI.conf
View file

@ -4,3 +4,7 @@ export CONFIG_IPA_CLIENTS_MANAGER=y
export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y
export CONFIG_RNDIS_IPA=y
export CONFIG_IPA3_REGDUMP=y
export CONFIG_IPA3_APPS_REGDUMP=y
export CONFIG_IPA3_REGDUMP_IPA_4_5=y
export CONFIG_IPA3_4_5_RGSTR=n

64
drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hw_common_ex.h
View file

@ -1,4 +1,6 @@
/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -412,6 +414,20 @@ enum ipa_hw_irq_srcs_e {
*/
#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES 23
/*
* Total number of channel contexts that need to be saved for q6
*/
#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6 11
/*
* Total number of event ring contexts that need to be saved for Q6
*/
#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6 11
/*
* Macro to set the active flag for all active pipe indexed register
*/
@ -511,7 +527,29 @@ enum ipa_hw_irq_srcs_e {
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 4), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[4].var_name }
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[10].var_name }
#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
@ -545,7 +583,29 @@ enum ipa_hw_irq_srcs_e {
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 2), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[3].var_name }
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[10].var_name }
/*
* Macro to define a particular register cfg entry for all pipe

68
drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h
View file

@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
*/
#if !defined(_IPA_HW_COMMON_EX_H_)
#define _IPA_HW_COMMON_EX_H_
@ -447,6 +449,11 @@ enum ipa_hw_irq_srcs_e {
*/
#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC 2
/*
* Total number of channel contexts that need to be saved for q6
*/
#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6 11
/*
* Total number of event ring contexts that need to be saved for APPS
*/
@ -456,6 +463,10 @@ enum ipa_hw_irq_srcs_e {
* Total number of event ring contexts that need to be saved for UC
*/
#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC 1
/*
* Total number of event ring contexts that need to be saved for Q6
*/
#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6 11
/*
* Total number of endpoints for which ipa_reg_save.pipes[endp_number]
@ -562,7 +573,31 @@ enum ipa_hw_irq_srcs_e {
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[10].var_name }
#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
@ -604,14 +639,39 @@ enum ipa_hw_irq_srcs_e {
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[10].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 11), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[11].var_name }
/*
* Macro to define a particular register cfg entry for all pipe
* indexed register
*/
#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name) \
({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
(u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name }, \
@ -672,7 +732,7 @@ enum ipa_hw_irq_srcs_e {
{ GEN_1xVECTOR_REG_OFST(reg_name, 29), \
(u32 *)&ipa_reg_save.ipa.pipes[29].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 30), \
(u32 *)&ipa_reg_save.ipa.pipes[30].endp.var_name })
(u32 *)&ipa_reg_save.ipa.pipes[30].endp.var_name }
/*
* Macro to define a particular register cfg entry for the remaining

44
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ipa_reg_dump.h"
#include "ipa_access_control.h"
@ -306,6 +307,8 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
* because the following registers are not scaler, rather
* they are register arrays...
*/
/* Below are accessable only by VMID0 domain. */
#ifndef CONFIG_IPA3_APPS_REGDUMP
IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_STTS_EE_n,
ipa_irq_stts_ee_n),
IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_EN_EE_n,
@ -322,6 +325,7 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ipa_suspend_irq_info_ee_n),
IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SUSPEND_IRQ_EN_EE_n,
ipa_suspend_irq_en_ee_n),
#endif /* CONFIG_IPA3_APPS_REGDUMP */
/* Pipe Endp Registers */
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_n,
@ -370,38 +374,45 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ipa_src_rsrc_grp_01_rsrc_type_n),
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n,
ipa_src_rsrc_grp_23_rsrc_type_n),
#ifdef CONFIG_IPA3_4_5_RGSTR
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n,
ipa_src_rsrc_grp_45_rsrc_type_n),
#endif
#endif /* CONFIG_IPA3_REGDUMP_IPA_4_5 */
#endif /* CONFIG_IPA3_4_5_RGSTR */
/* Destination Resource Group Config Registers */
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n,
ipa_dst_rsrc_grp_01_rsrc_type_n),
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n,
ipa_dst_rsrc_grp_23_rsrc_type_n),
#ifdef CONFIG_IPA3_4_5_RGSTR
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n,
ipa_dst_rsrc_grp_45_rsrc_type_n),
#endif
#endif /* CONFIG_IPA3_REGDUMP_IPA_4_5 */
#endif /* CONFIG_IPA3_4_5_RGSTR */
/* Source Resource Group Count Registers */
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(
IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n,
ipa_src_rsrc_grp_0123_rsrc_type_cnt_n),
#ifdef CONFIG_IPA3_4_5_RGSTR
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(
IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n,
ipa_src_rsrc_grp_4567_rsrc_type_cnt_n),
#endif
#endif /* CONFIG_IPA3_REGDUMP_IPA_4_5 */
#endif /* CONFIG_IPA3_4_5_RGSTR */
/* Destination Resource Group Count Registers */
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(
IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n,
ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n),
#ifdef CONFIG_IPA3_4_5_RGSTR
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(
IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n,
ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n),
#endif
#endif /* CONFIG_IPA3_REGDUMP_IPA_4_5 */
#endif /* CONFIG_IPA3_4_5_RGSTR */
/*
* =====================================================================
* GSI register definitions begin here...
@ -409,6 +420,9 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
*/
/* GSI General Registers */
/* Can access only through VMID_0 domain. */
#ifndef CONFIG_IPA3_APPS_REGDUMP
GEN_SRC_DST_ADDR_MAP(GSI_CFG,
gsi.gen,
gsi_cfg),
@ -419,7 +433,9 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
IPA_GSI_TOP_GSI_INST_RAM_n,
ipa_gsi_top_gsi_inst_ram_n),
/* GSI Debug Registers */
/* can access only through VMID_0 domain. */
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_BUSY_REG,
gsi.debug,
ipa_gsi_top_gsi_debug_busy_reg),
@ -449,6 +465,8 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GSI_DEBUG_QSB_LOG_LAST_MISC_IDn, qsb_log_last_misc),
/* GSI IRAM pointers Registers */
/* can access only through VMID_0 domain */
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD,
gsi.debug.gsi_iram_ptrs,
ipa_gsi_top_gsi_iram_ptr_ch_cmd),
@ -488,8 +506,10 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED,
gsi.debug.gsi_iram_ptrs,
ipa_gsi_top_gsi_iram_ptr_int_mod_stopped),
/* GSI SHRAM pointers Registers */
/* can access only through VMID_0 domain */
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR,
gsi.debug.gsi_shram_ptrs,
ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr),
@ -508,7 +528,6 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR,
gsi.debug.gsi_shram_ptrs,
ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr),
/*
* NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is
* because the following registers are not scaler, rather
@ -516,8 +535,12 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
*/
/* GSI General EE Registers */
/* can access only through VMID_0 domain */
IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(GSI_MANAGER_EE_QOS_n,
gsi_manager_ee_qos_n),
#endif /* CONFIG_IPA3_APPS_REGDUMP */
IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_GSI_STATUS,
ee_n_gsi_status),
IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ,
@ -659,12 +682,17 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ipa_endp_init_rsrc_grp_n),
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_SEQ_n,
ipa_endp_init_seq_n),
/* can access only through VMID_0 domain */
#ifndef CONFIG_IPA3_APPS_REGDUMP
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_TLV_n,
ipa_endp_gsi_cfg_tlv_n),
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_AOS_n,
ipa_endp_gsi_cfg_aos_n),
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG1_n,
ipa_endp_gsi_cfg1_n),
#endif /* CONFIG_IPA3_APPS_REGDUMP */
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA
(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n,
ipa_endp_filter_router_hsh_cfg_n),
@ -1490,7 +1518,7 @@ int ipa_reg_save_init(u32 value)
if (ipa3_ctx->do_testbus_collection_on_crash) {
memset(ipa_testbus_mem, value, sizeof(ipa_testbus_mem));
ipa_reg_save.ipa.testbus =
(struct ipa_reg_save_ipa_testbus_s *) ipa_testbus_mem;
(struct ipa_reg_save_ipa_testbus_s *) ipa_testbus_mem;
}
/* setup access for register collection/dump on crash */

26
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#if !defined(_IPA_REG_DUMP_H_)
#define _IPA_REG_DUMP_H_
@ -242,18 +243,33 @@ struct map_src_dst_addr_s {
#define IPA_REG_SAVE_GSI_VER(reg_name, var_name) \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.gsi.gen.var_name }
/*
* Macro to define a particular register cfg entry for all 3 EE
* indexed register
*/
#ifdef CONFIG_IPA3_APPS_REGDUMP
#define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name }
#else
#define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \
(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name }
#endif /* CONFIG_IPA3_APPS_REGDUMP */
#define IPA_REG_SAVE_CFG_ENTRY_GSI_FIFO(reg_name, var_name, index) \
{ GEN_SCALER_REG_OFST(reg_name), \
(u32 *)&ipa_reg_save.ipa.gsi_fifo_status[index].var_name }
@ -1115,6 +1131,9 @@ struct ipa_reg_save_gsi_ch_cntxt_s {
a7[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7];
struct ipa_reg_save_gsi_ch_cntxt_per_ep_s
uc[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC];
struct ipa_reg_save_gsi_ch_cntxt_per_ep_s
q6[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6];
};
/* GSI Event Context register save top level data struct */
@ -1123,6 +1142,9 @@ struct ipa_reg_save_gsi_evt_cntxt_s {
a7[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7];
struct ipa_reg_save_gsi_evt_cntxt_per_ep_s
uc[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC];
struct ipa_reg_save_gsi_evt_cntxt_per_ep_s
q6[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6];
};
/* Top level IPA register save data struct */