From 77fa5c31ca713ecf76d21f6ed19d61ac33b4161c Mon Sep 17 00:00:00 2001
From: Pratham Pratap <ppratap@qti.qualcomm.com>
Date: Tue, 8 Aug 2023 11:49:08 +0530
Subject: [PATCH] ARM: dts: msm: Set refclock base address for sdxnightjar

This change adds refclock base address and sets the clock scheme to cml.
Also make major_rev of the phy to 1 and disable susphy for controller
during phy initialization as recommended in controller data book.

Change-Id: Idb293c7fe67c0c37ec85f7807ba487685af2a461
---
 qcom/sdxnightjar-usb.dtsi | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/qcom/sdxnightjar-usb.dtsi b/qcom/sdxnightjar-usb.dtsi
index 8ecf7008ec32..1f30f6e566f4 100644
--- a/qcom/sdxnightjar-usb.dtsi
+++ b/qcom/sdxnightjar-usb.dtsi
@@ -68,6 +68,7 @@
 			snps,usb2-gadget-lpm-disable;
 			snps,dis-u1-entry-quirk;
 			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
 			xhci-imod-value = <4000>;
 			maximum-speed = "super-speed";
 			dr_mode = "otg";
@@ -106,8 +107,10 @@
 
 	qusb_phy: qusb@79000 {
 		compatible = "qcom,qusb2phy";
-		reg = <0x00079000 0x180>;
-		reg-names = "qusb_phy_base";
+		reg = <0x00079000 0x180>,
+		      <0x01841030 0x4>;
+		reg-names = "qusb_phy_base",
+			    "ref_clk_addr";
 		vdd-supply = <&pmd9650_l4>;
 		vdda18-supply = <&pmd9650_l5>;
 		vdda33-supply = <&pmd9650_l10>;
@@ -123,6 +126,8 @@
 					0x9f 0x1c
 					0x00 0x18>;
 		phy_type = "utmi";
+		qcom,phy-clk-scheme = "cml";
+		qcom,major-rev = <1>;
 
 		USB3_GDSC-supply = <&gdsc_usb30>;
 		qcom,secure-level-shifter;