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PCIe: ASPM: Save/restore ASPM-L1SS controls in reverse order

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Commit 54fdb1e448 ("PCIe: ASPM: Save/restore ASPM-L1SS
controls for suspend/resume") restores PCI_L1SS_CTL1, then
PCI_L1SS_CTL2. It should do those in the reverse order, since
the Enable bits are in PCI_L1SS_CTL1.  It also restores L1SS
state before we restore the PCIe Capability potentially enabling
ASPM as a whole. Fix the issue by changing order for both save
and restore.

Change-Id: I84e3db25b651b93dd4c037fa287f58edde90407a
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
This commit is contained in:
Hemant Kumar 2021-05-05 13:52:20 -07:00
commit 787d287d9e
1 changed files with 2 additions and 2 deletions
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4
drivers/pci/pcie/aspm.c
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@ -761,8 +761,8 @@ void pci_save_aspm_l1ss_state(struct pci_dev *dev)
return;
cap = (u32 *)&save_state->cap.data[0];
pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, cap++);
pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, cap++);
pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, cap);
}
void pci_restore_aspm_l1ss_state(struct pci_dev *dev)
@ -780,8 +780,8 @@ void pci_restore_aspm_l1ss_state(struct pci_dev *dev)
return;
cap = (u32 *)&save_state->cap.data[0];
pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, *cap++);
pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, *cap++);
pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, *cap);
}
#endif