From 788e2f8e33abc002c77cde476c33b46b9bcba2b9 Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Mon, 17 Aug 2020 13:07:16 +0530 Subject: [PATCH] usb: dwc3: Set FORCE_MEM_CORE_ON bit of GCC_USB30_MASTER_CLK USB FORCE_MEM_CORE_ON retains the USB controller CSR when system goes into and comes out from CXPC (i.e. using MX instead of CX). This change sets the FORCE_MEM_CORE_ON bit of GCC_USB30_MASTER_CLK by calling qcom_clk_set_flags API exposed by clock driver. Change-Id: Ifb83b1b02214b034be53d2b443ae101688b4a97e Signed-off-by: Pratham Pratap --- drivers/usb/dwc3/dwc3-msm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index e0122b85ab6a..02fb367c09f9 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -2187,6 +2188,7 @@ static int dwc3_msm_config_gdsc(struct dwc3_msm *mdwc, int on) return ret; } + qcom_clk_set_flags(mdwc->core_clk, CLKFLAG_RETAIN_MEM); ret = clk_prepare_enable(mdwc->core_csr_clk); if (ret) { regulator_disable(mdwc->dwc3_gdsc); @@ -2194,6 +2196,7 @@ static int dwc3_msm_config_gdsc(struct dwc3_msm *mdwc, int on) return ret; } } else { + qcom_clk_set_flags(mdwc->core_clk, CLKFLAG_NORETAIN_MEM); clk_disable_unprepare(mdwc->core_csr_clk); ret = regulator_disable(mdwc->dwc3_gdsc); if (ret) {