mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-31 04:01:48 -04:00
Merge git://git.infradead.org/mtd-2.6
* git://git.infradead.org/mtd-2.6: (82 commits) mtd: fix build error in m25p80.c mtd: Remove redundant mutex from mtd_blkdevs.c MTD: Fix wrong check register_blkdev return value Revert "mtd: cleanup Kconfig dependencies" mtd: cfi_cmdset_0002: make sector erase command variable mtd: cfi_cmdset_0002: add CFI detection for SST 38VF640x chips mtd: cfi_util: add support for switching SST 39VF640xB chips into QRY mode mtd: cfi_cmdset_0001: use defined value of P_ID_INTEL_PERFORMANCE instead of hardcoded one block2mtd: dubious assignment P4080/mtd: Fix the freescale lbc issue with 36bit mode P4080/eLBC: Make Freescale elbc interrupt common to elbc devices mtd: phram: use KBUILD_MODNAME mtd: OneNAND: S5PC110: Fix double call suspend & resume function mtd: nand: fix MTD_MODE_RAW writes jffs2: use kmemdup mtd: sm_ftl: cosmetic, use bool when possible mtd: r852: remove useless pci powerup/down from suspend/resume routines mtd: blktrans: fix a race vs kthread_stop mtd: blktrans: kill BKL mtd: allow to unload the mtdtrans module if its block devices aren't open ... Fix up trivial whitespace-introduced conflict in drivers/mtd/mtdchar.c
This commit is contained in:
Linus Torvalds
commit
79346507ad
71 changed files with 3412 additions and 1159 deletions
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@ -682,9 +682,12 @@ config 4xx_SOC
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bool
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config FSL_LBC
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bool
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bool "Freescale Local Bus support"
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depends on FSL_SOC
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help
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Freescale Localbus support
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Enables reporting of errors from the Freescale local bus
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controller. Also contains some common code used by
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drivers for specific local bus peripherals.
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config FSL_GTM
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bool
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@ -1,9 +1,10 @@
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/* Freescale Local Bus Controller
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*
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* Copyright (c) 2006-2007 Freescale Semiconductor
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* Copyright © 2006-2007, 2010 Freescale Semiconductor
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*
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* Authors: Nick Spence <nick.spence@freescale.com>,
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* Scott Wood <scottwood@freescale.com>
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* Jack Lan <jack.lan@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -26,6 +27,8 @@
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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struct fsl_lbc_bank {
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__be32 br; /**< Base Register */
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@ -125,13 +128,23 @@ struct fsl_lbc_regs {
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#define LTESR_ATMW 0x00800000
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#define LTESR_ATMR 0x00400000
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#define LTESR_CS 0x00080000
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#define LTESR_UPM 0x00000002
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#define LTESR_CC 0x00000001
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#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
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#define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
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| LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
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| LTESR_CC)
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#define LTESR_CLEAR 0xFFFFFFFF
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#define LTECCR_CLEAR 0xFFFFFFFF
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#define LTESR_STATUS LTESR_MASK
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#define LTEIR_ENABLE LTESR_MASK
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#define LTEDR_ENABLE 0x00000000
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__be32 ltedr; /**< Transfer Error Disable Register */
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__be32 lteir; /**< Transfer Error Interrupt Register */
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__be32 lteatr; /**< Transfer Error Attributes Register */
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__be32 ltear; /**< Transfer Error Address Register */
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u8 res6[0xC];
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__be32 lteccr; /**< Transfer Error ECC Register */
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u8 res6[0x8];
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__be32 lbcr; /**< Configuration Register */
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#define LBCR_LDIS 0x80000000
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#define LBCR_LDIS_SHIFT 31
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@ -235,6 +248,7 @@ struct fsl_upm {
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int width;
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};
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extern u32 fsl_lbc_addr(phys_addr_t addr_base);
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extern int fsl_lbc_find(phys_addr_t addr_base);
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extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
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@ -265,7 +279,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
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cpu_relax();
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}
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/* overview of the fsl lbc controller */
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struct fsl_lbc_ctrl {
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/* device info */
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struct device *dev;
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struct fsl_lbc_regs __iomem *regs;
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int irq;
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wait_queue_head_t irq_wait;
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spinlock_t lock;
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void *nand;
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/* status read from LTESR by irq handler */
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unsigned int irq_status;
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};
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extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
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u32 mar);
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extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
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#endif /* __ASM_FSL_LBC_H */
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@ -1,9 +1,12 @@
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/*
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* Freescale LBC and UPM routines.
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*
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* Copyright (c) 2007-2008 MontaVista Software, Inc.
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* Copyright © 2007-2008 MontaVista Software, Inc.
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* Copyright © 2010 Freescale Semiconductor
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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* Author: Jack Lan <Jack.Lan@freescale.com>
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* Author: Roy Zang <tie-fei.zang@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -19,39 +22,37 @@
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/mod_devicetable.h>
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#include <asm/prom.h>
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#include <asm/fsl_lbc.h>
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static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
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static struct fsl_lbc_regs __iomem *fsl_lbc_regs;
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struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
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EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
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static char __initdata *compat_lbc[] = {
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"fsl,pq2-localbus",
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"fsl,pq2pro-localbus",
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"fsl,pq3-localbus",
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"fsl,elbc",
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};
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static int __init fsl_lbc_init(void)
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/**
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* fsl_lbc_addr - convert the base address
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* @addr_base: base address of the memory bank
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*
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* This function converts a base address of lbc into the right format for the
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* BR register. If the SOC has eLBC then it returns 32bit physical address
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* else it convers a 34bit local bus physical address to correct format of
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* 32bit address for BR register (Example: MPC8641).
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*/
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u32 fsl_lbc_addr(phys_addr_t addr_base)
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{
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struct device_node *lbus;
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int i;
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struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
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u32 addr = addr_base & 0xffff8000;
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for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
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lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
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if (lbus)
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goto found;
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}
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return -ENODEV;
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if (of_device_is_compatible(np, "fsl,elbc"))
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return addr;
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found:
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fsl_lbc_regs = of_iomap(lbus, 0);
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of_node_put(lbus);
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if (!fsl_lbc_regs)
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return -ENOMEM;
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return 0;
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return addr | ((addr_base & 0x300000000ull) >> 19);
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}
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arch_initcall(fsl_lbc_init);
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EXPORT_SYMBOL(fsl_lbc_addr);
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/**
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* fsl_lbc_find - find Localbus bank
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@ -65,15 +66,17 @@ arch_initcall(fsl_lbc_init);
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int fsl_lbc_find(phys_addr_t addr_base)
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{
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int i;
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struct fsl_lbc_regs __iomem *lbc;
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if (!fsl_lbc_regs)
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if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
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return -ENODEV;
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for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
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__be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
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__be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
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lbc = fsl_lbc_ctrl_dev->regs;
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for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
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__be32 br = in_be32(&lbc->bank[i].br);
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__be32 or = in_be32(&lbc->bank[i].or);
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if (br & BR_V && (br & or & BR_BA) == addr_base)
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if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
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return i;
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}
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@ -94,22 +97,27 @@ int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
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{
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int bank;
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__be32 br;
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struct fsl_lbc_regs __iomem *lbc;
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bank = fsl_lbc_find(addr_base);
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if (bank < 0)
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return bank;
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br = in_be32(&fsl_lbc_regs->bank[bank].br);
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if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
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return -ENODEV;
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lbc = fsl_lbc_ctrl_dev->regs;
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br = in_be32(&lbc->bank[bank].br);
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switch (br & BR_MSEL) {
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case BR_MS_UPMA:
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upm->mxmr = &fsl_lbc_regs->mamr;
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upm->mxmr = &lbc->mamr;
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break;
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case BR_MS_UPMB:
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upm->mxmr = &fsl_lbc_regs->mbmr;
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upm->mxmr = &lbc->mbmr;
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break;
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case BR_MS_UPMC:
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upm->mxmr = &fsl_lbc_regs->mcmr;
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upm->mxmr = &lbc->mcmr;
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break;
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default:
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return -EINVAL;
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@ -148,9 +156,12 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
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int ret = 0;
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unsigned long flags;
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if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
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return -ENODEV;
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spin_lock_irqsave(&fsl_lbc_lock, flags);
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out_be32(&fsl_lbc_regs->mar, mar);
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out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
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switch (upm->width) {
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case 8:
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@ -172,3 +183,166 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
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return ret;
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}
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EXPORT_SYMBOL(fsl_upm_run_pattern);
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static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
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{
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
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/* clear event registers */
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setbits32(&lbc->ltesr, LTESR_CLEAR);
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out_be32(&lbc->lteatr, 0);
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out_be32(&lbc->ltear, 0);
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out_be32(&lbc->lteccr, LTECCR_CLEAR);
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out_be32(&lbc->ltedr, LTEDR_ENABLE);
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/* Enable interrupts for any detected events */
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out_be32(&lbc->lteir, LTEIR_ENABLE);
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return 0;
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}
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/*
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* NOTE: This interrupt is used to report localbus events of various kinds,
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* such as transaction errors on the chipselects.
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*/
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static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
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{
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struct fsl_lbc_ctrl *ctrl = data;
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
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u32 status;
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status = in_be32(&lbc->ltesr);
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if (!status)
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return IRQ_NONE;
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out_be32(&lbc->ltesr, LTESR_CLEAR);
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out_be32(&lbc->lteatr, 0);
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out_be32(&lbc->ltear, 0);
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ctrl->irq_status = status;
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if (status & LTESR_BM)
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dev_err(ctrl->dev, "Local bus monitor time-out: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_WP)
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dev_err(ctrl->dev, "Write protect error: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_ATMW)
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dev_err(ctrl->dev, "Atomic write error: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_ATMR)
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dev_err(ctrl->dev, "Atomic read error: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_CS)
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dev_err(ctrl->dev, "Chip select error: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_UPM)
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;
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if (status & LTESR_FCT) {
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dev_err(ctrl->dev, "FCM command time-out: "
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"LTESR 0x%08X\n", status);
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smp_wmb();
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wake_up(&ctrl->irq_wait);
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}
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if (status & LTESR_PAR) {
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dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
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"LTESR 0x%08X\n", status);
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smp_wmb();
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wake_up(&ctrl->irq_wait);
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}
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if (status & LTESR_CC) {
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smp_wmb();
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wake_up(&ctrl->irq_wait);
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}
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if (status & ~LTESR_MASK)
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dev_err(ctrl->dev, "Unknown error: "
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"LTESR 0x%08X\n", status);
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return IRQ_HANDLED;
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}
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/*
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* fsl_lbc_ctrl_probe
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*
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* called by device layer when it finds a device matching
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* one our driver can handled. This code allocates all of
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* the resources needed for the controller only. The
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* resources for the NAND banks themselves are allocated
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* in the chip probe function.
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*/
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static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
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{
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int ret;
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if (!dev->dev.of_node) {
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dev_err(&dev->dev, "Device OF-Node is NULL");
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return -EFAULT;
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}
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fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
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if (!fsl_lbc_ctrl_dev)
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return -ENOMEM;
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dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
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spin_lock_init(&fsl_lbc_ctrl_dev->lock);
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init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
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fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
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if (!fsl_lbc_ctrl_dev->regs) {
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dev_err(&dev->dev, "failed to get memory region\n");
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ret = -ENODEV;
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||||
goto err;
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}
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fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
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if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
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dev_err(&dev->dev, "failed to get irq resource\n");
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ret = -ENODEV;
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goto err;
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}
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fsl_lbc_ctrl_dev->dev = &dev->dev;
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ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev);
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if (ret < 0)
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goto err;
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||||
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ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
|
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"fsl-lbc", fsl_lbc_ctrl_dev);
|
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if (ret != 0) {
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dev_err(&dev->dev, "failed to install irq (%d)\n",
|
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fsl_lbc_ctrl_dev->irq);
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||||
ret = fsl_lbc_ctrl_dev->irq;
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||||
goto err;
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||||
}
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||||
|
||||
return 0;
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||||
|
||||
err:
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||||
iounmap(fsl_lbc_ctrl_dev->regs);
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kfree(fsl_lbc_ctrl_dev);
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return ret;
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||||
}
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|
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static const struct of_device_id fsl_lbc_match[] = {
|
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{ .compatible = "fsl,elbc", },
|
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{ .compatible = "fsl,pq3-localbus", },
|
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{ .compatible = "fsl,pq2-localbus", },
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{ .compatible = "fsl,pq2pro-localbus", },
|
||||
{},
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||||
};
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||||
|
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static struct platform_driver fsl_lbc_ctrl_driver = {
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||||
.driver = {
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||||
.name = "fsl-lbc",
|
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.of_match_table = fsl_lbc_match,
|
||||
},
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.probe = fsl_lbc_ctrl_probe,
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||||
};
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|
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static int __init fsl_lbc_init(void)
|
||||
{
|
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return platform_driver_register(&fsl_lbc_ctrl_driver);
|
||||
}
|
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module_init(fsl_lbc_init);
|
||||
|
|
|
|||
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