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Merge "ARM: dts: msm: add dispcc clock reference for dsi-display nodes"

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This commit is contained in:
qctecmdr 2021-02-20 04:28:22 -08:00 • committed by Gerrit - the friendly Code Review server
commit 79797251f4
2 changed files with 56 additions and 6 deletions
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41
display/shima-sde-display.dtsi
View file

@ -1,4 +1,5 @@
#include "shima-sde-display-common.dtsi"
#include <dt-bindings/clock/qcom,dispcc-shima.h>
&soc {
sde_wb: qcom,wb-display@0 {
@ -24,7 +25,22 @@
<&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 PCLK_SRC_1_CLK>,
<&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>;
<&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
@ -32,7 +48,8 @@
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1",
"src_byte_clk1", "src_pixel_clk1",
"shadow_byte_clk1", "shadow_pixel_clk1";
"shadow_byte_clk1", "shadow_pixel_clk1",
"mdp_core_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@ -55,11 +72,27 @@
<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1";
"cphy_byte_clk1", "cphy_pixel_clk1",
"mdp_core_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;

21
display/yupik-sde-display.dtsi
View file

@ -1,4 +1,5 @@
#include "yupik-sde-display-common.dtsi"
#include <dt-bindings/clock/qcom,dispcc-yupik.h>
&soc {
sde_wb: qcom,wb-display@0 {
@ -18,12 +19,28 @@
<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>;
<&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0",
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0";
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0",
"mdp_core_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;