From 7a0971c78d37a396ea99f137356d7223a89d2176 Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Tue, 2 Jun 2020 09:21:02 +0530 Subject: [PATCH] cpufreq: qcom: Set the register for GT Limits Management interrupt Set the GT_IRQ_CLR bit of EPSS_INTR_CLEAR register to generate the EPSS hardware GT interrupt when LMH throttle occurs. Change-Id: I1ba6faf1a28f2d8d06c8d91f3046bb064263cb67 Signed-off-by: Naveen Yadav --- drivers/cpufreq/qcom-cpufreq-hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index b8ec12c5b4a2..975943b43459 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -317,6 +317,8 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) } c->is_irq_requested = true; + writel_relaxed(GT_IRQ_STATUS, c->base + offsets[REG_INTR_EN]); + writel_relaxed(0x0, c->base + offsets[REG_INTR_CLR]); c->is_irq_enabled = true; c->freq_limit_attr.attr.name = "dcvsh_freq_limit"; c->freq_limit_attr.show = dcvsh_freq_limit_show;