From 7a0c8e97da72039f4b90217ae0288625e7f3ae53 Mon Sep 17 00:00:00 2001
From: Shreyas K K <shrekk@qti.qualcomm.com>
Date: Thu, 21 Jan 2021 18:43:48 +0530
Subject: [PATCH] ARM: dts: msm: Add PMU device nodes to SM6150

Add LLCC PMU, CPU PMU and DSU PMU device nodes
to SM6150.

Change-Id: I8985e8c8bcdd76bf2babacbf60c47c7f46b7c3d1
---
 qcom/sm6150.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi
index 653ea995e5e8..211d20ade731 100644
--- a/qcom/sm6150.dtsi
+++ b/qcom/sm6150.dtsi
@@ -637,6 +637,12 @@
 		};
 	};
 
+	llcc_pmu: llcc-pmu@90cc000 {
+		compatible = "qcom,llcc-pmu-ver2";
+		reg = <0x090cc000 0x300>;
+		reg-names = "lagg-base";
+	};
+
 	llcc_bw_opp_table: llcc-bw-opp-table {
 		compatible = "operating-points-v2";
 		BW_OPP_ENTRY( 150, 16); /*  2288 MB/s */
@@ -928,6 +934,19 @@
 		};
 	};
 
+	cpu_pmu: cpu-pmu {
+		compatible = "arm,armv8-pmuv3";
+		qcom,irq-is-percpu;
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	dsu_pmu@0 {
+		compatible = "arm,dsu-pmu";
+		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+		cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+		<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
+	};
+
 	qcom,msm-imem@146aa000 {
 		compatible = "qcom,msm-imem";
 		reg = <0x146aa000 0x1000>;