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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 07:03:09 -04:00
clk: qcom: Add debug cc clk measure nodes for SDXLEMUR
Add debug cc measure nodes for Sdxlemur to support debugfs clk measure. Change-Id: I634b6e2914e13ad829cb4887028802047383ccea Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>
This commit is contained in:
Naveen Yadav
parent
980059328b
commit
7a3d42b67b
3 changed files with 328 additions and 0 deletions
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@ -492,4 +492,13 @@ config SDX_GCC_LEMUR
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Say Y if you want to use peripheral devices such as UART, SPI, I2C,
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USB, UFS, SD/eMMC, PCIe, etc.
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config SDX_DEBUGCC_LEMUR
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tristate "SDXLEMUR Debug Clock Controller"
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depends on COMMON_CLK_QCOM
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help
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Support for the debug clock controller on Qualcomm Technologies, Inc.
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sdxlemur devices.
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Say Y if you want to support the debug clocks such as
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clock measurement functionality.
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endif
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@ -61,6 +61,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
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obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
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obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
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obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
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obj-$(CONFIG_SDX_DEBUGCC_SDXLEMUR) += debugcc-sdxlemur.o
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obj-$(CONFIG_SDX_GCC_SDXLEMUR) += gcc-sdxlemur.o
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obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o
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obj-$(CONFIG_SM_DEBUGCC_HOLI) += debugcc-holi.o
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318
drivers/clk/qcom/debugcc-sdxlemur.c
Normal file
318
drivers/clk/qcom/debugcc-sdxlemur.c
Normal file
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@ -0,0 +1,318 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "clk: %s: " fmt, __func__
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "clk-debug.h"
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#include "common.h"
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static struct measure_clk_data debug_mux_priv = {
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.ctl_reg = 0x69004,
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.status_reg = 0x69008,
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.xo_div4_cbcr = 0x1E010,
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};
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static const char *const apss_cc_debug_mux_parent_names[] = {
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"measure_only_apcs_clk",
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};
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static int apss_cc_debug_mux_sels[] = {
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0x3, /* measure_only_apcs_clk */
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};
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static int apss_cc_debug_mux_pre_divs[] = {
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0x1, /* measure_only_apcs_clk */
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};
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static struct clk_debug_mux apss_cc_debug_mux = {
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.priv = &debug_mux_priv,
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.debug_offset = 0x18,
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.post_div_offset = 0x18,
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.cbcr_offset = 0x0,
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.src_sel_mask = 0x38,
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.src_sel_shift = 3,
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.post_div_mask = 0x0,
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.post_div_shift = 0x0,
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.post_div_val = 1,
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.mux_sels = apss_cc_debug_mux_sels,
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.pre_div_vals = apss_cc_debug_mux_pre_divs,
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.hw.init = &(struct clk_init_data){
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.name = "apss_cc_debug_mux",
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.ops = &clk_debug_mux_ops,
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.parent_names = apss_cc_debug_mux_parent_names,
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.num_parents = ARRAY_SIZE(apss_cc_debug_mux_parent_names),
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.flags = CLK_IS_MEASURE,
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},
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};
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static const char *const gcc_debug_mux_parent_names[] = {
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"apss_cc_debug_mux",
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"gcc_ahb_pcie_link_clk",
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"gcc_blsp1_ahb_clk",
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"gcc_blsp1_qup1_i2c_apps_clk",
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"gcc_blsp1_qup1_spi_apps_clk",
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"gcc_blsp1_qup2_i2c_apps_clk",
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"gcc_blsp1_qup2_spi_apps_clk",
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"gcc_blsp1_qup3_i2c_apps_clk",
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"gcc_blsp1_qup3_spi_apps_clk",
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"gcc_blsp1_qup4_i2c_apps_clk",
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"gcc_blsp1_qup4_spi_apps_clk",
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"gcc_blsp1_sleep_clk",
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"gcc_blsp1_uart1_apps_clk",
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"gcc_blsp1_uart2_apps_clk",
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"gcc_blsp1_uart3_apps_clk",
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"gcc_blsp1_uart4_apps_clk",
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"gcc_boot_rom_ahb_clk",
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"gcc_cpuss_ahb_clk",
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"gcc_cpuss_gnoc_clk",
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"gcc_gp1_clk",
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"gcc_gp2_clk",
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"gcc_gp3_clk",
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"gcc_pcie_aux_clk",
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"gcc_pcie_cfg_ahb_clk",
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"gcc_pcie_mstr_axi_clk",
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"gcc_pcie_pipe_clk",
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"gcc_pcie_rchng_phy_clk",
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"gcc_pcie_sleep_clk",
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"gcc_pcie_slv_axi_clk",
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"gcc_pcie_slv_q2a_axi_clk",
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"gcc_pdm2_clk",
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"gcc_pdm_ahb_clk",
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"gcc_pdm_xo4_clk",
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"gcc_sdcc1_ahb_clk",
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"gcc_sdcc1_apps_clk",
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"gcc_sys_noc_cpuss_ahb_clk",
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"gcc_usb30_master_clk",
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"gcc_usb30_mock_utmi_clk",
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"gcc_usb30_mstr_axi_clk",
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"gcc_usb30_sleep_clk",
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"gcc_usb30_slv_ahb_clk",
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"gcc_usb3_phy_aux_clk",
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"gcc_usb3_phy_pipe_clk",
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"gcc_usb_phy_cfg_ahb2phy_clk",
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"gcc_xo_div4_clk",
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"gcc_xo_pcie_link_clk",
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"measure_only_ipa_2x_clk",
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"measure_only_snoc_clk",
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};
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static int gcc_debug_mux_sels[] = {
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0x7C, /* apss_cc_debug_mux */
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0xCF, /* gcc_ahb_pcie_link_clk */
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0x34, /* gcc_blsp1_ahb_clk */
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0x37, /* gcc_blsp1_qup1_i2c_apps_clk */
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0x36, /* gcc_blsp1_qup1_spi_apps_clk */
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0x3B, /* gcc_blsp1_qup2_i2c_apps_clk */
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0x3A, /* gcc_blsp1_qup2_spi_apps_clk */
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0x3F, /* gcc_blsp1_qup3_i2c_apps_clk */
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0x3E, /* gcc_blsp1_qup3_spi_apps_clk */
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0x43, /* gcc_blsp1_qup4_i2c_apps_clk */
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0x42, /* gcc_blsp1_qup4_spi_apps_clk */
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0x35, /* gcc_blsp1_sleep_clk */
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0x38, /* gcc_blsp1_uart1_apps_clk */
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0x3C, /* gcc_blsp1_uart2_apps_clk */
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0x40, /* gcc_blsp1_uart3_apps_clk */
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0x44, /* gcc_blsp1_uart4_apps_clk */
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0x4B, /* gcc_boot_rom_ahb_clk */
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0x74, /* gcc_cpuss_ahb_clk */
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0x75, /* gcc_cpuss_gnoc_clk */
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0x85, /* gcc_gp1_clk */
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0x86, /* gcc_gp2_clk */
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0x87, /* gcc_gp3_clk */
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0x99, /* gcc_pcie_aux_clk */
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0x98, /* gcc_pcie_cfg_ahb_clk */
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0x97, /* gcc_pcie_mstr_axi_clk */
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0x9A, /* gcc_pcie_pipe_clk */
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0xB9, /* gcc_pcie_rchng_phy_clk */
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0x9C, /* gcc_pcie_sleep_clk */
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0x96, /* gcc_pcie_slv_axi_clk */
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0x95, /* gcc_pcie_slv_q2a_axi_clk */
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0x48, /* gcc_pdm2_clk */
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0x46, /* gcc_pdm_ahb_clk */
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0x47, /* gcc_pdm_xo4_clk */
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0x33, /* gcc_sdcc1_ahb_clk */
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0x32, /* gcc_sdcc1_apps_clk */
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0x10B, /* gcc_sys_noc_cpuss_ahb_clk */
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0x28, /* gcc_usb30_master_clk */
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0x2A, /* gcc_usb30_mock_utmi_clk */
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0x4F, /* gcc_usb30_mstr_axi_clk */
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0x29, /* gcc_usb30_sleep_clk */
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0x6B, /* gcc_usb30_slv_ahb_clk */
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0x2B, /* gcc_usb3_phy_aux_clk */
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0x2D, /* gcc_usb3_phy_pipe_clk */
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0x31, /* gcc_usb_phy_cfg_ahb2phy_clk */
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0x63, /* gcc_xo_div4_clk */
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0x77, /* gcc_xo_pcie_link_clk */
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0xAC, /* measure_only_ipa_2x_clk */
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0x109, /* measure_only_snoc_clk */
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};
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static struct clk_debug_mux gcc_debug_mux = {
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.priv = &debug_mux_priv,
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.debug_offset = 0x69000,
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.post_div_offset = 0x25000,
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.cbcr_offset = 0x25004,
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.src_sel_mask = 0x3FF,
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.src_sel_shift = 0,
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.post_div_mask = 0xF,
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.post_div_shift = 0,
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.post_div_val = 4,
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.mux_sels = gcc_debug_mux_sels,
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.hw.init = &(struct clk_init_data){
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.name = "gcc_debug_mux",
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.ops = &clk_debug_mux_ops,
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.parent_names = gcc_debug_mux_parent_names,
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.num_parents = ARRAY_SIZE(gcc_debug_mux_parent_names),
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.flags = CLK_IS_MEASURE,
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},
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};
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static const char *const mc_cc_debug_mux_parent_names[] = {
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"measure_only_mccc_clk",
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};
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static struct clk_debug_mux mc_cc_debug_mux = {
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.period_offset = 0x50,
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.hw.init = &(struct clk_init_data){
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.name = "mc_cc_debug_mux",
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.ops = &clk_debug_mux_ops,
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.parent_names = mc_cc_debug_mux_parent_names,
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.num_parents = ARRAY_SIZE(mc_cc_debug_mux_parent_names),
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.flags = CLK_IS_MEASURE,
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},
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};
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static struct mux_regmap_names mux_list[] = {
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{ .mux = &apss_cc_debug_mux, .regmap_name = "qcom,apsscc" },
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{ .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" },
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{ .mux = &mc_cc_debug_mux, .regmap_name = "qcom,mccc" },
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};
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static struct clk_dummy measure_only_apcs_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_apcs_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_ipa_2x_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_ipa_2x_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_snoc_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_snoc_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_mccc_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_mccc_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_hw *debugcc_sdxlemur_hws[] = {
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&measure_only_ipa_2x_clk.hw,
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&measure_only_snoc_clk.hw,
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&measure_only_mccc_clk.hw,
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&measure_only_apcs_clk.hw,
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};
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static const struct of_device_id clk_debug_match_table[] = {
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{ .compatible = "qcom,sdxlemur-debugcc" },
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{ }
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};
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static int clk_debug_sdxlemur_probe(struct platform_device *pdev)
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{
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struct clk *clk;
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int ret = 0, i;
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BUILD_BUG_ON(ARRAY_SIZE(gcc_debug_mux_parent_names) !=
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ARRAY_SIZE(gcc_debug_mux_sels));
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clk = devm_clk_get(&pdev->dev, "xo_clk_src");
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get xo clock\n");
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return PTR_ERR(clk);
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}
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debug_mux_priv.cxo = clk;
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for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
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ret = map_debug_bases(pdev, mux_list[i].regmap_name,
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mux_list[i].mux);
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if (ret == -EBADR)
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continue;
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else if (ret)
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return ret;
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clk = devm_clk_register(&pdev->dev, &mux_list[i].mux->hw);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
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clk_hw_get_name(&mux_list[i].mux->hw),
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PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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}
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for (i = 0; i < ARRAY_SIZE(debugcc_sdxlemur_hws); i++) {
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clk = devm_clk_register(&pdev->dev, debugcc_sdxlemur_hws[i]);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
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clk_hw_get_name(debugcc_sdxlemur_hws[i]),
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PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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}
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ret = clk_debug_measure_register(&gcc_debug_mux.hw);
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if (ret) {
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dev_err(&pdev->dev, "Could not register Measure clocks\n");
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return ret;
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}
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dev_info(&pdev->dev, "Registered debug measure clocks\n");
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return ret;
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}
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static struct platform_driver clk_debug_driver = {
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.probe = clk_debug_sdxlemur_probe,
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.driver = {
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.name = "sdxlemur-debugcc",
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.of_match_table = clk_debug_match_table,
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},
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};
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static int __init clk_debug_sdxlemur_init(void)
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{
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return platform_driver_register(&clk_debug_driver);
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}
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fs_initcall(clk_debug_sdxlemur_init);
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MODULE_DESCRIPTION("QTI DEBUG CC SDXLEMUR Driver");
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MODULE_LICENSE("GPL v2");
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