From 5cb46307a4122c8856c9a0bd093b589f0ae313c3 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Fri, 11 Sep 2020 22:12:13 +0530 Subject: [PATCH 1/5] ARM: dts: msm: Add SMMU devices for SM6150 Add the device tree nodes that describe the APPS and graphics SMMU for SM6150. Change-Id: I1e8af4c7297294165a60d9acdf6ac450d5b0fd3f --- qcom/msm-arm-smmu-sm6150.dtsi | 249 ++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 2 + 2 files changed, 251 insertions(+) create mode 100644 qcom/msm-arm-smmu-sm6150.dtsi diff --git a/qcom/msm-arm-smmu-sm6150.dtsi b/qcom/msm-arm-smmu-sm6150.dtsi new file mode 100644 index 000000000000..ebf2aaeeaf3d --- /dev/null +++ b/qcom/msm-arm-smmu-sm6150.dtsi @@ -0,0 +1,249 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x50a0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x50a0000 0x10000>, + <0x50c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,dynamic; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x50c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x50c5000 0x1000>, + <0x50c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@0x50c9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x50c9000 0x1000>, + <0x50c2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x80000>, + <0x150c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + qcom,active-only; + + anoc_1_tbu: anoc_1_tbu@0x150c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150c5000 0x1000>, + <0x150c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + anoc_2_tbu: anoc_2_tbu@0x150c9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150c9000 0x1000>, + <0x150c2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150cd000 0x1000>, + <0x150c2210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_MDP0 + &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d1000 0x1000>, + <0x150c2218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,active-only; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mmss_noc SLAVE_MNOC_SF_MEM_NOC>; + }; + + compute_dsp_tbu: compute_dsp_tbu@0x150d5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d5000 0x1000>, + <0x150c2220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + /* No GDSC */ + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + + adsp_tbu: adsp_tbu@0x150d9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d9000 0x1000>, + <0x150c2228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,active-only; + interconnects = <&system_noc MASTER_GEM_NOC_SNOC + &config_noc SLAVE_IMEM_CFG>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x9 0>; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + dma-coherent; + }; +}; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x7ff 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* HF and SF TBUs: +3 deep PF */ + <0x800 0x7ff 0x103>; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 3d2a49cb91a4..a11584c45c7f 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1663,3 +1663,5 @@ &venus_gdsc { status = "ok"; }; + +#include "msm-arm-smmu-sm6150.dtsi" From 4cd166d1dbf3c7196a168839ad240664d7121dbc Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Mon, 12 Oct 2020 18:17:07 +0530 Subject: [PATCH 2/5] ARM: dts: msm: Add lpass device node for PIL on SM6150 Add PIL device tree node to load firmware images of lpass on SM6150. Change-Id: Ifd99f607bed9da77494d0b0f188bf4e23bfb5711 --- qcom/sa6155-pmic.dtsi | 6 ++++++ qcom/sm6150.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/qcom/sa6155-pmic.dtsi b/qcom/sa6155-pmic.dtsi index a8824ad1c37c..313bd701ba65 100644 --- a/qcom/sa6155-pmic.dtsi +++ b/qcom/sa6155-pmic.dtsi @@ -39,5 +39,11 @@ /delete-node/ rpmh-regulator-bobc1; }; +&soc { + qcom,lpass@62400000 { + vdd_cx-supply = <&VDD_CX_LEVEL>; + }; +}; + #include "sa6155-regulator.dtsi" #include "pm6155.dtsi" diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index a11584c45c7f..d5a5e22c57c6 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. SM6150"; @@ -1560,6 +1561,50 @@ #interrupt-cells = <2>; }; }; + + qcom,lpass@62400000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x62400000 0x00100>; + + vdd_cx-supply = <&L8A_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; }; #include "sm6150-qupv3.dtsi" From a5872a70b20f83ccd3b3ad6ae5e254297f4df0e3 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Tue, 13 Oct 2020 19:01:13 +0530 Subject: [PATCH 3/5] ARM: dts: msm: Add turing device node for PIL on SM6150 Add PIL device tree node to load firmware image of turing on SM6150. Change-Id: Id3f7b5aa613ff71eef4e6ec7588b72f97c5788cd --- qcom/sm6150.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index d5a5e22c57c6..a178bd4df490 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1605,6 +1605,50 @@ mboxes = <&qmp_aop 0>; mbox-names = "adsp-pil"; }; + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>, + <&cdsp_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; }; #include "sm6150-qupv3.dtsi" From 3a6586d2701788d788a3bd3a12b3965f1e021611 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Tue, 13 Oct 2020 19:15:06 +0530 Subject: [PATCH 4/5] ARM: dts: msm: Add venus device node for PIL on SM6150 Add PIL device tree node to load firmware images of venus on SM6150. Change-Id: I53e95d989f1a8e56d89cee5c9c15e3e5e03b7cc1 --- qcom/sm6150.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index a178bd4df490..ecf2201756e0 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1649,6 +1649,28 @@ mboxes = <&qmp_aop 0>; mbox-names = "cdsp-pil"; }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_clk"; + qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk"; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; }; #include "sm6150-qupv3.dtsi" From 876d50d754f2066212f167caff6b92b8d00ad1a1 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Thu, 15 Oct 2020 19:19:46 +0530 Subject: [PATCH 5/5] ARM: dts: msm: Enable device nodes for PIL on SM6150 Enable PIL device tree nodes to load firmware images of venus, lpasss, turing on SM6150. Change-Id: I64ce4f777adf264c060ba2dab777bc690c90efef --- qcom/sa6155-adp-common.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index c2d9e07465c0..3cd8585afb01 100644 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -3,3 +3,17 @@ &qupv3_0 { status = "ok"; }; + +&soc { + qcom,lpass@62400000 { + status = "ok"; + }; + + qcom,venus@aae0000 { + status = "ok"; + }; + + qcom,turing@8300000 { + status = "ok"; + }; +};