mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
arm-soc: pin muxing for sh-mobile
This is another cleanup series, containing the move of the Renesas SH-Mobile pin controller code from arch/arm/mach-shmobile over to the generic pinctrl subsystem, changing it over to the common interfaces in the process. Based on agreement between Olof, Paul Mundt, Linus Walleij and Simon, we're merging this large branch of pinctrl conversion through arm-soc, even though it contains the corresponding conversions for arch/sh. Main reason for this is tight dependencies (that will now mostly be broken) between the arch/sh and mach-shmobile implementations. There will be more of this in 3.10 to do device-tree bindings, but this is the initial conversion. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUSaEl2CrR//JCVInAQI82RAAjpctH6C0WSrbGU0JvK37UARADhIEExBU DkmKV7i6yZHMZ11L0u2W5DvO+VPMN/hyIQlHmIJzxXQx/yGysnbshgapRkLKNXPx BNOrswOHAuILxxl78b6Wi5DwR0AgLNz2uC8jPFo7FWKjIEIFMV6XTtotc1Je51Cy yTetSIuHjWAYYb2cGcYCoN2DLXq6d+RA1vXebyAWOCfZJqtF0DhMAw14gDuxjyMb 2y5cBZte1ym/mSYtg5JiJGiSnhcl3y5QzUSgIbFJIhnS4DQgztnVXnn5/iAaw0/i 5f/9brGaVsUYlugZ5zA8NY2UUAiwlilN4W8M42Fe5rOJ6bPrwSbSWkFdwEZpZsMU kpV4urrwWVNJAJFCQZx+Cioh1zVxyPdNXtwOwOO73kwf7jSYwr+Kc0K//emw6iOp sCUzTHupgL+TWPlYm5SCG8UcM3Cj8TVxmPJ84n/TqhEiejT+lYHMQs6wVNz/xyMX +1eX+ZAh+gshY/9tnAMDyYDJTFhNJ33yraKW3a/V/ve/3eaf8yJ8vCKaL1ZqN7jt XXbZE26N/Mw8/zazMxfq3NHXpNAiDVVUmMcA8UBUwrRWsVIE/tu4SjmnpFN8BI/j L9NsscehKZEZjyZ2CW4NiPx4VsGncStCsMcYkwk4CMHs5k7lgv0+ptRVekDX8COF oVodlV4ua3w= =U+ce -----END PGP SIGNATURE----- Merge tag 'sh-pinmux' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull sh-mobile pinctrl conversion from Arnd Bergmann: "This is another cleanup series, containing the move of the Renesas SH-Mobile pin controller code from arch/arm/mach-shmobile over to the generic pinctrl subsystem, changing it over to the common interfaces in the process. Based on agreement between Olof, Paul Mundt, Linus Walleij and Simon, we're merging this large branch of pinctrl conversion through arm-soc, even though it contains the corresponding conversions for arch/sh. Main reason for this is tight dependencies (that will now mostly be broken) between the arch/sh and mach-shmobile implementations. There will be more of this in 3.10 to do device-tree bindings, but this is the initial conversion." * tag 'sh-pinmux' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (81 commits) sh-pfc: sh_pfc_probe() sizeof() fix sh-pfc: Move sh_pfc.h from include/linux/ to driver directory sh-pfc: Remove pinmux_info definition sh: Remove unused sh_pfc_register_info() function sh: shx3: pinmux: Use driver-provided pinmux info sh: sh7786: pinmux: Use driver-provided pinmux info sh: sh7785: pinmux: Use driver-provided pinmux info sh: sh7757: pinmux: Use driver-provided pinmux info sh: sh7734: pinmux: Use driver-provided pinmux info sh: sh7724: pinmux: Use driver-provided pinmux info sh: sh7723: pinmux: Use driver-provided pinmux info sh: sh7722: pinmux: Use driver-provided pinmux info sh: sh7720: pinmux: Use driver-provided pinmux info sh: sh7269: pinmux: Use driver-provided pinmux info sh: sh7264: pinmux: Use driver-provided pinmux info sh: sh7203: pinmux: Use driver-provided pinmux info ARM: shmobile: sh73a0: Use driver-provided pinmux info ARM: shmobile: sh7372: Use driver-provided pinmux info ARM: shmobile: r8a7779: Use driver-provided pinmux info ARM: shmobile: r8a7740: Use driver-provided pinmux info ...
This commit is contained in:
Linus Torvalds
commit
7ae1c76ee5
54 changed files with 21897 additions and 21520 deletions
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@ -227,7 +227,7 @@ config PINCTRL_EXYNOS5440
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select PINCONF
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source "drivers/pinctrl/mvebu/Kconfig"
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source "drivers/pinctrl/sh-pfc/Kconfig"
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source "drivers/pinctrl/spear/Kconfig"
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config PINCTRL_XWAY
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@ -49,4 +49,6 @@ obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
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obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
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obj-$(CONFIG_PLAT_ORION) += mvebu/
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obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
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obj-$(CONFIG_SUPERH) += sh-pfc/
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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116
drivers/pinctrl/sh-pfc/Kconfig
Normal file
116
drivers/pinctrl/sh-pfc/Kconfig
Normal file
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@ -0,0 +1,116 @@
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#
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# Renesas SH and SH Mobile PINCTRL drivers
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#
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if ARCH_SHMOBILE || SUPERH
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config PINCTRL_SH_PFC
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# XXX move off the gpio dependency
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depends on GENERIC_GPIO
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select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
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select PINMUX
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select PINCONF
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def_bool y
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help
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This enables pin control drivers for SH and SH Mobile platforms
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config GPIO_SH_PFC
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bool "SuperH PFC GPIO support"
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depends on PINCTRL_SH_PFC && GPIOLIB
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help
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This enables support for GPIOs within the SoC's pin function
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controller.
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config PINCTRL_PFC_R8A7740
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def_bool y
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depends on ARCH_R8A7740
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A7779
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def_bool y
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depends on ARCH_R8A7779
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7203
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def_bool y
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depends on CPU_SUBTYPE_SH7203
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7264
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def_bool y
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depends on CPU_SUBTYPE_SH7264
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7269
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def_bool y
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depends on CPU_SUBTYPE_SH7269
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7372
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def_bool y
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depends on ARCH_SH7372
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH73A0
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def_bool y
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depends on ARCH_SH73A0
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7720
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def_bool y
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depends on CPU_SUBTYPE_SH7720
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7722
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def_bool y
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depends on CPU_SUBTYPE_SH7722
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7723
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def_bool y
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depends on CPU_SUBTYPE_SH7723
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7724
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def_bool y
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depends on CPU_SUBTYPE_SH7724
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7734
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def_bool y
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depends on CPU_SUBTYPE_SH7734
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7757
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def_bool y
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depends on CPU_SUBTYPE_SH7757
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7785
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def_bool y
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depends on CPU_SUBTYPE_SH7785
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7786
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def_bool y
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depends on CPU_SUBTYPE_SH7786
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SHX3
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def_bool y
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depends on CPU_SUBTYPE_SHX3
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depends on GENERIC_GPIO
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select PINCTRL_SH_PFC
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endif
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21
drivers/pinctrl/sh-pfc/Makefile
Normal file
21
drivers/pinctrl/sh-pfc/Makefile
Normal file
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@ -0,0 +1,21 @@
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sh-pfc-objs = core.o pinctrl.o
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ifeq ($(CONFIG_GPIO_SH_PFC),y)
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sh-pfc-objs += gpio.o
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endif
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obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
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obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
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obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
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obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
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obj-$(CONFIG_PINCTRL_PFC_SH7372) += pfc-sh7372.o
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obj-$(CONFIG_PINCTRL_PFC_SH73A0) += pfc-sh73a0.o
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obj-$(CONFIG_PINCTRL_PFC_SH7720) += pfc-sh7720.o
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obj-$(CONFIG_PINCTRL_PFC_SH7722) += pfc-sh7722.o
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obj-$(CONFIG_PINCTRL_PFC_SH7723) += pfc-sh7723.o
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obj-$(CONFIG_PINCTRL_PFC_SH7724) += pfc-sh7724.o
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obj-$(CONFIG_PINCTRL_PFC_SH7734) += pfc-sh7734.o
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obj-$(CONFIG_PINCTRL_PFC_SH7757) += pfc-sh7757.o
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obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o
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obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o
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obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o
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635
drivers/pinctrl/sh-pfc/core.c
Normal file
635
drivers/pinctrl/sh-pfc/core.c
Normal file
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@ -0,0 +1,635 @@
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/*
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* SuperH Pin Function Controller support.
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*
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* Copyright (C) 2008 Magnus Damm
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* Copyright (C) 2009 - 2012 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define DRV_NAME "sh-pfc"
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "core.h"
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static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
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{
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struct resource *res;
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int k;
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if (pdev->num_resources == 0) {
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pfc->num_windows = 0;
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return 0;
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}
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pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
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sizeof(*pfc->window), GFP_NOWAIT);
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if (!pfc->window)
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return -ENOMEM;
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pfc->num_windows = pdev->num_resources;
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for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
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WARN_ON(resource_type(res) != IORESOURCE_MEM);
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pfc->window[k].phys = res->start;
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pfc->window[k].size = resource_size(res);
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pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
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resource_size(res));
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if (!pfc->window[k].virt)
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return -ENOMEM;
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}
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return 0;
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}
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static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
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unsigned long address)
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{
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struct sh_pfc_window *window;
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int k;
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/* scan through physical windows and convert address */
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for (k = 0; k < pfc->num_windows; k++) {
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window = pfc->window + k;
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if (address < window->phys)
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continue;
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if (address >= (window->phys + window->size))
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continue;
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return window->virt + (address - window->phys);
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}
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/* no windows defined, register must be 1:1 mapped virt:phys */
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return (void __iomem *)address;
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}
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static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
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{
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if (enum_id < r->begin)
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return 0;
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if (enum_id > r->end)
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return 0;
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return 1;
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}
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static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
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unsigned long reg_width)
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{
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switch (reg_width) {
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case 8:
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return ioread8(mapped_reg);
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case 16:
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return ioread16(mapped_reg);
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case 32:
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return ioread32(mapped_reg);
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}
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BUG();
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return 0;
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}
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static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
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unsigned long reg_width, unsigned long data)
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{
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switch (reg_width) {
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case 8:
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iowrite8(data, mapped_reg);
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return;
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case 16:
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iowrite16(data, mapped_reg);
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return;
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case 32:
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iowrite32(data, mapped_reg);
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return;
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}
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BUG();
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}
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int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
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{
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unsigned long pos;
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pos = dr->reg_width - (in_pos + 1);
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pr_debug("read_bit: addr = %lx, pos = %ld, "
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"r_width = %ld\n", dr->reg, pos, dr->reg_width);
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return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
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}
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void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
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unsigned long value)
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{
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unsigned long pos;
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pos = dr->reg_width - (in_pos + 1);
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pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
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"r_width = %ld\n",
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dr->reg, !!value, pos, dr->reg_width);
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if (value)
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set_bit(pos, &dr->reg_shadow);
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else
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clear_bit(pos, &dr->reg_shadow);
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sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
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}
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static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
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struct pinmux_cfg_reg *crp,
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unsigned long in_pos,
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void __iomem **mapped_regp,
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unsigned long *maskp,
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unsigned long *posp)
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{
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int k;
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*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
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if (crp->field_width) {
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*maskp = (1 << crp->field_width) - 1;
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*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
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} else {
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*maskp = (1 << crp->var_field_width[in_pos]) - 1;
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*posp = crp->reg_width;
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for (k = 0; k <= in_pos; k++)
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*posp -= crp->var_field_width[k];
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}
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}
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static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
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struct pinmux_cfg_reg *crp,
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unsigned long field)
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{
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void __iomem *mapped_reg;
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unsigned long mask, pos;
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sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
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pr_debug("read_reg: addr = %lx, field = %ld, "
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"r_width = %ld, f_width = %ld\n",
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crp->reg, field, crp->reg_width, crp->field_width);
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return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
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}
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static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
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struct pinmux_cfg_reg *crp,
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unsigned long field, unsigned long value)
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{
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void __iomem *mapped_reg;
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unsigned long mask, pos, data;
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sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
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|
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pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
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"r_width = %ld, f_width = %ld\n",
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crp->reg, value, field, crp->reg_width, crp->field_width);
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mask = ~(mask << pos);
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value = value << pos;
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data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
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data &= mask;
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data |= value;
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|
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(
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sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
|
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~data);
|
||||
|
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sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
|
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}
|
||||
|
||||
static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
|
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{
|
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struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
|
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struct pinmux_data_reg *data_reg;
|
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int k, n;
|
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|
||||
if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
|
||||
return -1;
|
||||
|
||||
k = 0;
|
||||
while (1) {
|
||||
data_reg = pfc->info->data_regs + k;
|
||||
|
||||
if (!data_reg->reg_width)
|
||||
break;
|
||||
|
||||
data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
|
||||
|
||||
for (n = 0; n < data_reg->reg_width; n++) {
|
||||
if (data_reg->enum_ids[n] == gpiop->enum_id) {
|
||||
gpiop->flags &= ~PINMUX_FLAG_DREG;
|
||||
gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
|
||||
gpiop->flags &= ~PINMUX_FLAG_DBIT;
|
||||
gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
k++;
|
||||
}
|
||||
|
||||
BUG();
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
|
||||
{
|
||||
struct pinmux_data_reg *drp;
|
||||
int k;
|
||||
|
||||
for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++)
|
||||
sh_pfc_setup_data_reg(pfc, k);
|
||||
|
||||
k = 0;
|
||||
while (1) {
|
||||
drp = pfc->info->data_regs + k;
|
||||
|
||||
if (!drp->reg_width)
|
||||
break;
|
||||
|
||||
drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
|
||||
drp->reg_width);
|
||||
k++;
|
||||
}
|
||||
}
|
||||
|
||||
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
|
||||
struct pinmux_data_reg **drp, int *bitp)
|
||||
{
|
||||
struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
|
||||
int k, n;
|
||||
|
||||
if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
|
||||
return -1;
|
||||
|
||||
k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
|
||||
n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
|
||||
*drp = pfc->info->data_regs + k;
|
||||
*bitp = n;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
|
||||
struct pinmux_cfg_reg **crp, int *fieldp,
|
||||
int *valuep, unsigned long **cntp)
|
||||
{
|
||||
struct pinmux_cfg_reg *config_reg;
|
||||
unsigned long r_width, f_width, curr_width, ncomb;
|
||||
int k, m, n, pos, bit_pos;
|
||||
|
||||
k = 0;
|
||||
while (1) {
|
||||
config_reg = pfc->info->cfg_regs + k;
|
||||
|
||||
r_width = config_reg->reg_width;
|
||||
f_width = config_reg->field_width;
|
||||
|
||||
if (!r_width)
|
||||
break;
|
||||
|
||||
pos = 0;
|
||||
m = 0;
|
||||
for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
|
||||
if (f_width)
|
||||
curr_width = f_width;
|
||||
else
|
||||
curr_width = config_reg->var_field_width[m];
|
||||
|
||||
ncomb = 1 << curr_width;
|
||||
for (n = 0; n < ncomb; n++) {
|
||||
if (config_reg->enum_ids[pos + n] == enum_id) {
|
||||
*crp = config_reg;
|
||||
*fieldp = m;
|
||||
*valuep = n;
|
||||
*cntp = &config_reg->cnt[m];
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
pos += ncomb;
|
||||
m++;
|
||||
}
|
||||
k++;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
|
||||
pinmux_enum_t *enum_idp)
|
||||
{
|
||||
pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id;
|
||||
pinmux_enum_t *data = pfc->info->gpio_data;
|
||||
int k;
|
||||
|
||||
if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) {
|
||||
if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) {
|
||||
pr_err("non data/mark enum_id for gpio %d\n", gpio);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if (pos) {
|
||||
*enum_idp = data[pos + 1];
|
||||
return pos + 1;
|
||||
}
|
||||
|
||||
for (k = 0; k < pfc->info->gpio_data_size; k++) {
|
||||
if (data[k] == enum_id) {
|
||||
*enum_idp = data[k + 1];
|
||||
return k + 1;
|
||||
}
|
||||
}
|
||||
|
||||
pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
|
||||
int cfg_mode)
|
||||
{
|
||||
struct pinmux_cfg_reg *cr = NULL;
|
||||
pinmux_enum_t enum_id;
|
||||
struct pinmux_range *range;
|
||||
int in_range, pos, field, value;
|
||||
unsigned long *cntp;
|
||||
|
||||
switch (pinmux_type) {
|
||||
|
||||
case PINMUX_TYPE_FUNCTION:
|
||||
range = NULL;
|
||||
break;
|
||||
|
||||
case PINMUX_TYPE_OUTPUT:
|
||||
range = &pfc->info->output;
|
||||
break;
|
||||
|
||||
case PINMUX_TYPE_INPUT:
|
||||
range = &pfc->info->input;
|
||||
break;
|
||||
|
||||
case PINMUX_TYPE_INPUT_PULLUP:
|
||||
range = &pfc->info->input_pu;
|
||||
break;
|
||||
|
||||
case PINMUX_TYPE_INPUT_PULLDOWN:
|
||||
range = &pfc->info->input_pd;
|
||||
break;
|
||||
|
||||
default:
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
pos = 0;
|
||||
enum_id = 0;
|
||||
field = 0;
|
||||
value = 0;
|
||||
while (1) {
|
||||
pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
|
||||
if (pos <= 0)
|
||||
goto out_err;
|
||||
|
||||
if (!enum_id)
|
||||
break;
|
||||
|
||||
/* first check if this is a function enum */
|
||||
in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
|
||||
if (!in_range) {
|
||||
/* not a function enum */
|
||||
if (range) {
|
||||
/*
|
||||
* other range exists, so this pin is
|
||||
* a regular GPIO pin that now is being
|
||||
* bound to a specific direction.
|
||||
*
|
||||
* for this case we only allow function enums
|
||||
* and the enums that match the other range.
|
||||
*/
|
||||
in_range = sh_pfc_enum_in_range(enum_id, range);
|
||||
|
||||
/*
|
||||
* special case pass through for fixed
|
||||
* input-only or output-only pins without
|
||||
* function enum register association.
|
||||
*/
|
||||
if (in_range && enum_id == range->force)
|
||||
continue;
|
||||
} else {
|
||||
/*
|
||||
* no other range exists, so this pin
|
||||
* must then be of the function type.
|
||||
*
|
||||
* allow function type pins to select
|
||||
* any combination of function/in/out
|
||||
* in their MARK lists.
|
||||
*/
|
||||
in_range = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (!in_range)
|
||||
continue;
|
||||
|
||||
if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
|
||||
&field, &value, &cntp) != 0)
|
||||
goto out_err;
|
||||
|
||||
switch (cfg_mode) {
|
||||
case GPIO_CFG_DRYRUN:
|
||||
if (!*cntp ||
|
||||
(sh_pfc_read_config_reg(pfc, cr, field) != value))
|
||||
continue;
|
||||
break;
|
||||
|
||||
case GPIO_CFG_REQ:
|
||||
sh_pfc_write_config_reg(pfc, cr, field, value);
|
||||
*cntp = *cntp + 1;
|
||||
break;
|
||||
|
||||
case GPIO_CFG_FREE:
|
||||
*cntp = *cntp - 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
out_err:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int sh_pfc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_pfc_soc_info *info;
|
||||
struct sh_pfc *pfc;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Ensure that the type encoding fits
|
||||
*/
|
||||
BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
|
||||
|
||||
info = pdev->id_entry->driver_data
|
||||
? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
|
||||
if (info == NULL)
|
||||
return -ENODEV;
|
||||
|
||||
pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
|
||||
if (pfc == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
pfc->info = info;
|
||||
pfc->dev = &pdev->dev;
|
||||
|
||||
ret = sh_pfc_ioremap(pfc, pdev);
|
||||
if (unlikely(ret < 0))
|
||||
return ret;
|
||||
|
||||
spin_lock_init(&pfc->lock);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
sh_pfc_setup_data_regs(pfc);
|
||||
|
||||
/*
|
||||
* Initialize pinctrl bindings first
|
||||
*/
|
||||
ret = sh_pfc_register_pinctrl(pfc);
|
||||
if (unlikely(ret != 0))
|
||||
return ret;
|
||||
|
||||
#ifdef CONFIG_GPIO_SH_PFC
|
||||
/*
|
||||
* Then the GPIO chip
|
||||
*/
|
||||
ret = sh_pfc_register_gpiochip(pfc);
|
||||
if (unlikely(ret != 0)) {
|
||||
/*
|
||||
* If the GPIO chip fails to come up we still leave the
|
||||
* PFC state as it is, given that there are already
|
||||
* extant users of it that have succeeded by this point.
|
||||
*/
|
||||
pr_notice("failed to init GPIO chip, ignoring...\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
platform_set_drvdata(pdev, pfc);
|
||||
|
||||
pr_info("%s support registered\n", info->name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_pfc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_pfc *pfc = platform_get_drvdata(pdev);
|
||||
|
||||
#ifdef CONFIG_GPIO_SH_PFC
|
||||
sh_pfc_unregister_gpiochip(pfc);
|
||||
#endif
|
||||
sh_pfc_unregister_pinctrl(pfc);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_device_id sh_pfc_id_table[] = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7740
|
||||
{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7779
|
||||
{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7203
|
||||
{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7264
|
||||
{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7269
|
||||
{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7372
|
||||
{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH73A0
|
||||
{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7720
|
||||
{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7722
|
||||
{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7723
|
||||
{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7724
|
||||
{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7734
|
||||
{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7757
|
||||
{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7785
|
||||
{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH7786
|
||||
{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SHX3
|
||||
{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
|
||||
#endif
|
||||
{ "sh-pfc", 0 },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
|
||||
|
||||
static struct platform_driver sh_pfc_driver = {
|
||||
.probe = sh_pfc_probe,
|
||||
.remove = sh_pfc_remove,
|
||||
.id_table = sh_pfc_id_table,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init sh_pfc_init(void)
|
||||
{
|
||||
return platform_driver_register(&sh_pfc_driver);
|
||||
}
|
||||
postcore_initcall(sh_pfc_init);
|
||||
|
||||
static void __exit sh_pfc_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sh_pfc_driver);
|
||||
}
|
||||
module_exit(sh_pfc_exit);
|
||||
|
||||
MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
|
||||
MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
72
drivers/pinctrl/sh-pfc/core.h
Normal file
72
drivers/pinctrl/sh-pfc/core.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* SuperH Pin Function Controller support.
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __SH_PFC_CORE_H__
|
||||
#define __SH_PFC_CORE_H__
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
struct sh_pfc_window {
|
||||
phys_addr_t phys;
|
||||
void __iomem *virt;
|
||||
unsigned long size;
|
||||
};
|
||||
|
||||
struct sh_pfc_chip;
|
||||
struct sh_pfc_pinctrl;
|
||||
|
||||
struct sh_pfc {
|
||||
struct device *dev;
|
||||
struct sh_pfc_soc_info *info;
|
||||
spinlock_t lock;
|
||||
|
||||
unsigned int num_windows;
|
||||
struct sh_pfc_window *window;
|
||||
|
||||
struct sh_pfc_chip *gpio;
|
||||
struct sh_pfc_pinctrl *pinctrl;
|
||||
};
|
||||
|
||||
int sh_pfc_register_gpiochip(struct sh_pfc *pfc);
|
||||
int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
|
||||
|
||||
int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
|
||||
int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
|
||||
|
||||
int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
|
||||
void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
|
||||
unsigned long value);
|
||||
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
|
||||
struct pinmux_data_reg **drp, int *bitp);
|
||||
int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
|
||||
pinmux_enum_t *enum_idp);
|
||||
int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
|
||||
int cfg_mode);
|
||||
|
||||
extern struct sh_pfc_soc_info r8a7740_pinmux_info;
|
||||
extern struct sh_pfc_soc_info r8a7779_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7203_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7264_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7269_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7372_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh73a0_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7720_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7722_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7723_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7724_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7734_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7757_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7785_pinmux_info;
|
||||
extern struct sh_pfc_soc_info sh7786_pinmux_info;
|
||||
extern struct sh_pfc_soc_info shx3_pinmux_info;
|
||||
|
||||
#endif /* __SH_PFC_CORE_H__ */
|
||||
178
drivers/pinctrl/sh-pfc/gpio.c
Normal file
178
drivers/pinctrl/sh-pfc/gpio.c
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* SuperH Pin Function Controller GPIO driver.
|
||||
*
|
||||
* Copyright (C) 2008 Magnus Damm
|
||||
* Copyright (C) 2009 - 2012 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "core.h"
|
||||
|
||||
struct sh_pfc_chip {
|
||||
struct sh_pfc *pfc;
|
||||
struct gpio_chip gpio_chip;
|
||||
};
|
||||
|
||||
static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
|
||||
{
|
||||
return container_of(gc, struct sh_pfc_chip, gpio_chip);
|
||||
}
|
||||
|
||||
static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
|
||||
{
|
||||
return gpio_to_pfc_chip(gc)->pfc;
|
||||
}
|
||||
|
||||
static int sh_gpio_request(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
return pinctrl_request_gpio(offset);
|
||||
}
|
||||
|
||||
static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
pinctrl_free_gpio(offset);
|
||||
}
|
||||
|
||||
static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value)
|
||||
{
|
||||
struct pinmux_data_reg *dr = NULL;
|
||||
int bit = 0;
|
||||
|
||||
if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
|
||||
BUG();
|
||||
else
|
||||
sh_pfc_write_bit(dr, bit, value);
|
||||
}
|
||||
|
||||
static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio)
|
||||
{
|
||||
struct pinmux_data_reg *dr = NULL;
|
||||
int bit = 0;
|
||||
|
||||
if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
|
||||
return -EINVAL;
|
||||
|
||||
return sh_pfc_read_bit(dr, bit);
|
||||
}
|
||||
|
||||
static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
return pinctrl_gpio_direction_input(offset);
|
||||
}
|
||||
|
||||
static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
|
||||
int value)
|
||||
{
|
||||
sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
|
||||
|
||||
return pinctrl_gpio_direction_output(offset);
|
||||
}
|
||||
|
||||
static int sh_gpio_get(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
return sh_gpio_get_value(gpio_to_pfc(gc), offset);
|
||||
}
|
||||
|
||||
static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
|
||||
{
|
||||
sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
|
||||
}
|
||||
|
||||
static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
struct sh_pfc *pfc = gpio_to_pfc(gc);
|
||||
pinmux_enum_t enum_id;
|
||||
pinmux_enum_t *enum_ids;
|
||||
int i, k, pos;
|
||||
|
||||
pos = 0;
|
||||
enum_id = 0;
|
||||
while (1) {
|
||||
pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
|
||||
if (pos <= 0 || !enum_id)
|
||||
break;
|
||||
|
||||
for (i = 0; i < pfc->info->gpio_irq_size; i++) {
|
||||
enum_ids = pfc->info->gpio_irq[i].enum_ids;
|
||||
for (k = 0; enum_ids[k]; k++) {
|
||||
if (enum_ids[k] == enum_id)
|
||||
return pfc->info->gpio_irq[i].irq;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
|
||||
{
|
||||
struct sh_pfc *pfc = chip->pfc;
|
||||
struct gpio_chip *gc = &chip->gpio_chip;
|
||||
|
||||
gc->request = sh_gpio_request;
|
||||
gc->free = sh_gpio_free;
|
||||
gc->direction_input = sh_gpio_direction_input;
|
||||
gc->get = sh_gpio_get;
|
||||
gc->direction_output = sh_gpio_direction_output;
|
||||
gc->set = sh_gpio_set;
|
||||
gc->to_irq = sh_gpio_to_irq;
|
||||
|
||||
WARN_ON(pfc->info->first_gpio != 0); /* needs testing */
|
||||
|
||||
gc->label = pfc->info->name;
|
||||
gc->owner = THIS_MODULE;
|
||||
gc->base = pfc->info->first_gpio;
|
||||
gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1;
|
||||
}
|
||||
|
||||
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
|
||||
{
|
||||
struct sh_pfc_chip *chip;
|
||||
int ret;
|
||||
|
||||
chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
|
||||
if (unlikely(!chip))
|
||||
return -ENOMEM;
|
||||
|
||||
chip->pfc = pfc;
|
||||
|
||||
sh_pfc_gpio_setup(chip);
|
||||
|
||||
ret = gpiochip_add(&chip->gpio_chip);
|
||||
if (unlikely(ret < 0))
|
||||
return ret;
|
||||
|
||||
pfc->gpio = chip;
|
||||
|
||||
pr_info("%s handling gpio %d -> %d\n",
|
||||
pfc->info->name, pfc->info->first_gpio,
|
||||
pfc->info->last_gpio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
|
||||
{
|
||||
struct sh_pfc_chip *chip = pfc->gpio;
|
||||
int ret;
|
||||
|
||||
ret = gpiochip_remove(&chip->gpio_chip);
|
||||
if (unlikely(ret < 0))
|
||||
return ret;
|
||||
|
||||
pfc->gpio = NULL;
|
||||
return 0;
|
||||
}
|
||||
2612
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
Normal file
2612
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
Normal file
File diff suppressed because it is too large
Load diff
2624
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
Normal file
2624
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
Normal file
File diff suppressed because it is too large
Load diff
1592
drivers/pinctrl/sh-pfc/pfc-sh7203.c
Normal file
1592
drivers/pinctrl/sh-pfc/pfc-sh7203.c
Normal file
File diff suppressed because it is too large
Load diff
2131
drivers/pinctrl/sh-pfc/pfc-sh7264.c
Normal file
2131
drivers/pinctrl/sh-pfc/pfc-sh7264.c
Normal file
File diff suppressed because it is too large
Load diff
2834
drivers/pinctrl/sh-pfc/pfc-sh7269.c
Normal file
2834
drivers/pinctrl/sh-pfc/pfc-sh7269.c
Normal file
File diff suppressed because it is too large
Load diff
1658
drivers/pinctrl/sh-pfc/pfc-sh7372.c
Normal file
1658
drivers/pinctrl/sh-pfc/pfc-sh7372.c
Normal file
File diff suppressed because it is too large
Load diff
2798
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
Normal file
2798
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
Normal file
File diff suppressed because it is too large
Load diff
1236
drivers/pinctrl/sh-pfc/pfc-sh7720.c
Normal file
1236
drivers/pinctrl/sh-pfc/pfc-sh7720.c
Normal file
File diff suppressed because it is too large
Load diff
1779
drivers/pinctrl/sh-pfc/pfc-sh7722.c
Normal file
1779
drivers/pinctrl/sh-pfc/pfc-sh7722.c
Normal file
File diff suppressed because it is too large
Load diff
1903
drivers/pinctrl/sh-pfc/pfc-sh7723.c
Normal file
1903
drivers/pinctrl/sh-pfc/pfc-sh7723.c
Normal file
File diff suppressed because it is too large
Load diff
2225
drivers/pinctrl/sh-pfc/pfc-sh7724.c
Normal file
2225
drivers/pinctrl/sh-pfc/pfc-sh7724.c
Normal file
File diff suppressed because it is too large
Load diff
2475
drivers/pinctrl/sh-pfc/pfc-sh7734.c
Normal file
2475
drivers/pinctrl/sh-pfc/pfc-sh7734.c
Normal file
File diff suppressed because it is too large
Load diff
2282
drivers/pinctrl/sh-pfc/pfc-sh7757.c
Normal file
2282
drivers/pinctrl/sh-pfc/pfc-sh7757.c
Normal file
File diff suppressed because it is too large
Load diff
1304
drivers/pinctrl/sh-pfc/pfc-sh7785.c
Normal file
1304
drivers/pinctrl/sh-pfc/pfc-sh7785.c
Normal file
File diff suppressed because it is too large
Load diff
837
drivers/pinctrl/sh-pfc/pfc-sh7786.c
Normal file
837
drivers/pinctrl/sh-pfc/pfc-sh7786.c
Normal file
|
|
@ -0,0 +1,837 @@
|
|||
/*
|
||||
* SH7786 Pinmux
|
||||
*
|
||||
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
|
||||
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
*
|
||||
* Based on SH7785 pinmux
|
||||
*
|
||||
* Copyright (C) 2008 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <cpu/sh7786.h>
|
||||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
enum {
|
||||
PINMUX_RESERVED = 0,
|
||||
|
||||
PINMUX_DATA_BEGIN,
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
|
||||
PE7_DATA, PE6_DATA,
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
|
||||
PG7_DATA, PG6_DATA, PG5_DATA,
|
||||
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA,
|
||||
PINMUX_DATA_END,
|
||||
|
||||
PINMUX_INPUT_BEGIN,
|
||||
PA7_IN, PA6_IN, PA5_IN, PA4_IN,
|
||||
PA3_IN, PA2_IN, PA1_IN, PA0_IN,
|
||||
PB7_IN, PB6_IN, PB5_IN, PB4_IN,
|
||||
PB3_IN, PB2_IN, PB1_IN, PB0_IN,
|
||||
PC7_IN, PC6_IN, PC5_IN, PC4_IN,
|
||||
PC3_IN, PC2_IN, PC1_IN, PC0_IN,
|
||||
PD7_IN, PD6_IN, PD5_IN, PD4_IN,
|
||||
PD3_IN, PD2_IN, PD1_IN, PD0_IN,
|
||||
PE7_IN, PE6_IN,
|
||||
PF7_IN, PF6_IN, PF5_IN, PF4_IN,
|
||||
PF3_IN, PF2_IN, PF1_IN, PF0_IN,
|
||||
PG7_IN, PG6_IN, PG5_IN,
|
||||
PH7_IN, PH6_IN, PH5_IN, PH4_IN,
|
||||
PH3_IN, PH2_IN, PH1_IN, PH0_IN,
|
||||
PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
|
||||
PJ3_IN, PJ2_IN, PJ1_IN,
|
||||
PINMUX_INPUT_END,
|
||||
|
||||
PINMUX_INPUT_PULLUP_BEGIN,
|
||||
PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
|
||||
PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
|
||||
PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
|
||||
PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
|
||||
PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
|
||||
PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
|
||||
PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
|
||||
PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
|
||||
PE7_IN_PU, PE6_IN_PU,
|
||||
PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
|
||||
PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
|
||||
PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
|
||||
PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
|
||||
PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
|
||||
PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
|
||||
PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
|
||||
PINMUX_INPUT_PULLUP_END,
|
||||
|
||||
PINMUX_OUTPUT_BEGIN,
|
||||
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
|
||||
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
|
||||
PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
|
||||
PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
|
||||
PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
|
||||
PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
|
||||
PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
|
||||
PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
|
||||
PE7_OUT, PE6_OUT,
|
||||
PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
|
||||
PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
|
||||
PG7_OUT, PG6_OUT, PG5_OUT,
|
||||
PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
|
||||
PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
|
||||
PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
|
||||
PJ3_OUT, PJ2_OUT, PJ1_OUT,
|
||||
PINMUX_OUTPUT_END,
|
||||
|
||||
PINMUX_FUNCTION_BEGIN,
|
||||
PA7_FN, PA6_FN, PA5_FN, PA4_FN,
|
||||
PA3_FN, PA2_FN, PA1_FN, PA0_FN,
|
||||
PB7_FN, PB6_FN, PB5_FN, PB4_FN,
|
||||
PB3_FN, PB2_FN, PB1_FN, PB0_FN,
|
||||
PC7_FN, PC6_FN, PC5_FN, PC4_FN,
|
||||
PC3_FN, PC2_FN, PC1_FN, PC0_FN,
|
||||
PD7_FN, PD6_FN, PD5_FN, PD4_FN,
|
||||
PD3_FN, PD2_FN, PD1_FN, PD0_FN,
|
||||
PE7_FN, PE6_FN,
|
||||
PF7_FN, PF6_FN, PF5_FN, PF4_FN,
|
||||
PF3_FN, PF2_FN, PF1_FN, PF0_FN,
|
||||
PG7_FN, PG6_FN, PG5_FN,
|
||||
PH7_FN, PH6_FN, PH5_FN, PH4_FN,
|
||||
PH3_FN, PH2_FN, PH1_FN, PH0_FN,
|
||||
PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
|
||||
PJ3_FN, PJ2_FN, PJ1_FN,
|
||||
P1MSEL14_0, P1MSEL14_1,
|
||||
P1MSEL13_0, P1MSEL13_1,
|
||||
P1MSEL12_0, P1MSEL12_1,
|
||||
P1MSEL11_0, P1MSEL11_1,
|
||||
P1MSEL10_0, P1MSEL10_1,
|
||||
P1MSEL9_0, P1MSEL9_1,
|
||||
P1MSEL8_0, P1MSEL8_1,
|
||||
P1MSEL7_0, P1MSEL7_1,
|
||||
P1MSEL6_0, P1MSEL6_1,
|
||||
P1MSEL5_0, P1MSEL5_1,
|
||||
P1MSEL4_0, P1MSEL4_1,
|
||||
P1MSEL3_0, P1MSEL3_1,
|
||||
P1MSEL2_0, P1MSEL2_1,
|
||||
P1MSEL1_0, P1MSEL1_1,
|
||||
P1MSEL0_0, P1MSEL0_1,
|
||||
|
||||
P2MSEL15_0, P2MSEL15_1,
|
||||
P2MSEL14_0, P2MSEL14_1,
|
||||
P2MSEL13_0, P2MSEL13_1,
|
||||
P2MSEL12_0, P2MSEL12_1,
|
||||
P2MSEL11_0, P2MSEL11_1,
|
||||
P2MSEL10_0, P2MSEL10_1,
|
||||
P2MSEL9_0, P2MSEL9_1,
|
||||
P2MSEL8_0, P2MSEL8_1,
|
||||
P2MSEL7_0, P2MSEL7_1,
|
||||
P2MSEL6_0, P2MSEL6_1,
|
||||
P2MSEL5_0, P2MSEL5_1,
|
||||
P2MSEL4_0, P2MSEL4_1,
|
||||
P2MSEL3_0, P2MSEL3_1,
|
||||
P2MSEL2_0, P2MSEL2_1,
|
||||
P2MSEL1_0, P2MSEL1_1,
|
||||
P2MSEL0_0, P2MSEL0_1,
|
||||
PINMUX_FUNCTION_END,
|
||||
|
||||
PINMUX_MARK_BEGIN,
|
||||
DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK,
|
||||
VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK,
|
||||
DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK,
|
||||
DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK,
|
||||
DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK,
|
||||
ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK,
|
||||
ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK,
|
||||
ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK,
|
||||
ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK,
|
||||
ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK,
|
||||
HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK,
|
||||
SCIF0_CTS_MARK, SCIF0_RTS_MARK,
|
||||
SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK,
|
||||
SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK,
|
||||
SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK,
|
||||
SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK,
|
||||
SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK,
|
||||
BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK,
|
||||
FALE_MARK, FRB_MARK, FSTATUS_MARK,
|
||||
FSE_MARK, FCLE_MARK,
|
||||
DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK,
|
||||
DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK,
|
||||
DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK,
|
||||
USB_OVC1_MARK, USB_OVC0_MARK,
|
||||
USB_PENC1_MARK, USB_PENC0_MARK,
|
||||
HAC_RES_MARK,
|
||||
HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK,
|
||||
HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK,
|
||||
SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK,
|
||||
SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK,
|
||||
SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK,
|
||||
SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK,
|
||||
SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK,
|
||||
SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK,
|
||||
SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK,
|
||||
SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK,
|
||||
TCLK_MARK,
|
||||
IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK,
|
||||
PINMUX_MARK_END,
|
||||
};
|
||||
|
||||
static pinmux_enum_t pinmux_data[] = {
|
||||
|
||||
/* PA GPIO */
|
||||
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
|
||||
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
|
||||
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
|
||||
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
|
||||
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
|
||||
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
|
||||
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
|
||||
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
|
||||
|
||||
/* PB GPIO */
|
||||
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
|
||||
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
|
||||
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
|
||||
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
|
||||
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
|
||||
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
|
||||
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
|
||||
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
|
||||
|
||||
/* PC GPIO */
|
||||
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
|
||||
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
|
||||
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
|
||||
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
|
||||
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
|
||||
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
|
||||
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
|
||||
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
|
||||
|
||||
/* PD GPIO */
|
||||
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
|
||||
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
|
||||
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
|
||||
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
|
||||
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
|
||||
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
|
||||
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
|
||||
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
|
||||
|
||||
/* PE GPIO */
|
||||
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
|
||||
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
|
||||
|
||||
/* PF GPIO */
|
||||
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
|
||||
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
|
||||
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
|
||||
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
|
||||
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
|
||||
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
|
||||
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
|
||||
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
|
||||
|
||||
/* PG GPIO */
|
||||
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
|
||||
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
|
||||
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
|
||||
|
||||
/* PH GPIO */
|
||||
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
|
||||
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
|
||||
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
|
||||
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
|
||||
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
|
||||
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
|
||||
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
|
||||
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
|
||||
|
||||
/* PJ GPIO */
|
||||
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
|
||||
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
|
||||
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
|
||||
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
|
||||
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
|
||||
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
|
||||
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
|
||||
|
||||
/* PA FN */
|
||||
PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
|
||||
PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
|
||||
PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
|
||||
PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
|
||||
PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
|
||||
PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
|
||||
PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
|
||||
PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
|
||||
PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
|
||||
PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
|
||||
PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
|
||||
PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
|
||||
PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
|
||||
PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
|
||||
PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
|
||||
PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
|
||||
|
||||
/* PB FN */
|
||||
PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
|
||||
PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
|
||||
PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
|
||||
PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
|
||||
PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
|
||||
PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
|
||||
PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
|
||||
PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
|
||||
PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
|
||||
PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
|
||||
PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
|
||||
PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
|
||||
PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
|
||||
PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
|
||||
PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
|
||||
PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
|
||||
|
||||
/* PC FN */
|
||||
PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
|
||||
PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
|
||||
PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
|
||||
PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
|
||||
PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
|
||||
PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
|
||||
PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
|
||||
PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
|
||||
|
||||
PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
|
||||
PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
|
||||
PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
|
||||
PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
|
||||
PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
|
||||
PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
|
||||
PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
|
||||
PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
|
||||
|
||||
/* PD FN */
|
||||
PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
|
||||
PINMUX_DATA(SCIF1_SCK_MARK, PD6_FN),
|
||||
PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
|
||||
PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
|
||||
PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
|
||||
PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
|
||||
PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
|
||||
PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
|
||||
PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
|
||||
PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
|
||||
PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
|
||||
PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
|
||||
PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
|
||||
PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
|
||||
|
||||
/* PE FN */
|
||||
PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
|
||||
PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
|
||||
|
||||
/* PF FN */
|
||||
PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
|
||||
PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
|
||||
PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
|
||||
PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
|
||||
PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
|
||||
PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
|
||||
PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
|
||||
PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
|
||||
PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
|
||||
PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
|
||||
PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
|
||||
PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
|
||||
PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
|
||||
PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
|
||||
PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
|
||||
PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
|
||||
PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
|
||||
PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
|
||||
PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
|
||||
PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
|
||||
PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
|
||||
PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
|
||||
PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
|
||||
PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
|
||||
|
||||
/* PG FN */
|
||||
PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
|
||||
PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
|
||||
PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
|
||||
PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
|
||||
PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
|
||||
PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
|
||||
PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
|
||||
PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
|
||||
|
||||
/* PH FN */
|
||||
PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
|
||||
PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
|
||||
PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
|
||||
PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
|
||||
PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
|
||||
PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
|
||||
PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
|
||||
PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
|
||||
PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
|
||||
PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
|
||||
PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
|
||||
PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
|
||||
PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
|
||||
PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
|
||||
PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
|
||||
PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
|
||||
PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
|
||||
PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
|
||||
PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
|
||||
PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
|
||||
PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
|
||||
|
||||
/* PJ FN */
|
||||
PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
|
||||
PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
|
||||
PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
|
||||
PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
|
||||
PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
|
||||
PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
|
||||
PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
|
||||
PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
|
||||
PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
|
||||
PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
|
||||
PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
|
||||
PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
|
||||
PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
|
||||
PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
|
||||
PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
|
||||
PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
|
||||
PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
|
||||
PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
|
||||
PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
|
||||
};
|
||||
|
||||
static struct pinmux_gpio pinmux_gpios[] = {
|
||||
/* PA */
|
||||
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
|
||||
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
|
||||
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
|
||||
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
|
||||
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
|
||||
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
|
||||
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
|
||||
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
|
||||
|
||||
/* PB */
|
||||
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
|
||||
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
|
||||
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
|
||||
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
|
||||
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
|
||||
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
|
||||
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
|
||||
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
|
||||
|
||||
/* PC */
|
||||
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
|
||||
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
|
||||
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
|
||||
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
|
||||
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
|
||||
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
|
||||
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
|
||||
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
|
||||
|
||||
/* PD */
|
||||
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
|
||||
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
|
||||
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
|
||||
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
|
||||
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
|
||||
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
|
||||
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
|
||||
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
|
||||
|
||||
/* PE */
|
||||
PINMUX_GPIO(GPIO_PE7, PE7_DATA),
|
||||
PINMUX_GPIO(GPIO_PE6, PE6_DATA),
|
||||
|
||||
/* PF */
|
||||
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
|
||||
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
|
||||
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
|
||||
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
|
||||
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
|
||||
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
|
||||
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
|
||||
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
|
||||
|
||||
/* PG */
|
||||
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
|
||||
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
|
||||
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
|
||||
|
||||
/* PH */
|
||||
PINMUX_GPIO(GPIO_PH7, PH7_DATA),
|
||||
PINMUX_GPIO(GPIO_PH6, PH6_DATA),
|
||||
PINMUX_GPIO(GPIO_PH5, PH5_DATA),
|
||||
PINMUX_GPIO(GPIO_PH4, PH4_DATA),
|
||||
PINMUX_GPIO(GPIO_PH3, PH3_DATA),
|
||||
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
|
||||
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
|
||||
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
|
||||
|
||||
/* PJ */
|
||||
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
|
||||
|
||||
/* FN */
|
||||
PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
|
||||
};
|
||||
|
||||
static struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
|
||||
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
|
||||
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
|
||||
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
|
||||
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
|
||||
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
|
||||
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
|
||||
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
|
||||
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
|
||||
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
|
||||
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
|
||||
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
|
||||
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
|
||||
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
|
||||
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
|
||||
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
|
||||
PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
|
||||
PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
|
||||
PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
|
||||
PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
|
||||
PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
|
||||
PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
|
||||
PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
|
||||
PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
|
||||
PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
|
||||
PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
|
||||
PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
|
||||
PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
|
||||
PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
|
||||
PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
|
||||
PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
|
||||
PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
|
||||
PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
|
||||
PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
|
||||
PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
|
||||
PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
|
||||
PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
|
||||
PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
|
||||
PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
|
||||
PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
|
||||
PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
|
||||
PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
|
||||
PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
|
||||
PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
|
||||
PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
|
||||
PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
|
||||
PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
|
||||
PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
|
||||
PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
|
||||
PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
|
||||
PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
|
||||
PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
|
||||
PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
|
||||
PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
|
||||
PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
|
||||
PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
|
||||
PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
|
||||
PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
|
||||
PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
|
||||
PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
|
||||
PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
|
||||
0, 0, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
|
||||
0, 0,
|
||||
P1MSEL14_0, P1MSEL14_1,
|
||||
P1MSEL13_0, P1MSEL13_1,
|
||||
P1MSEL12_0, P1MSEL12_1,
|
||||
P1MSEL11_0, P1MSEL11_1,
|
||||
P1MSEL10_0, P1MSEL10_1,
|
||||
P1MSEL9_0, P1MSEL9_1,
|
||||
P1MSEL8_0, P1MSEL8_1,
|
||||
P1MSEL7_0, P1MSEL7_1,
|
||||
P1MSEL6_0, P1MSEL6_1,
|
||||
P1MSEL5_0, P1MSEL5_1,
|
||||
P1MSEL4_0, P1MSEL4_1,
|
||||
P1MSEL3_0, P1MSEL3_1,
|
||||
P1MSEL2_0, P1MSEL2_1,
|
||||
P1MSEL1_0, P1MSEL1_1,
|
||||
P1MSEL0_0, P1MSEL0_1 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
|
||||
P2MSEL15_0, P2MSEL15_1,
|
||||
P2MSEL14_0, P2MSEL14_1,
|
||||
P2MSEL13_0, P2MSEL13_1,
|
||||
P2MSEL12_0, P2MSEL12_1,
|
||||
P2MSEL11_0, P2MSEL11_1,
|
||||
P2MSEL10_0, P2MSEL10_1,
|
||||
P2MSEL9_0, P2MSEL9_1,
|
||||
P2MSEL8_0, P2MSEL8_1,
|
||||
P2MSEL7_0, P2MSEL7_1,
|
||||
P2MSEL6_0, P2MSEL6_1,
|
||||
P2MSEL5_0, P2MSEL5_1,
|
||||
P2MSEL4_0, P2MSEL4_1,
|
||||
P2MSEL3_0, P2MSEL3_1,
|
||||
P2MSEL2_0, P2MSEL2_1,
|
||||
P2MSEL1_0, P2MSEL1_1,
|
||||
P2MSEL0_0, P2MSEL0_1 }
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
|
||||
PE7_DATA, PE6_DATA,
|
||||
0, 0, 0, 0, 0, 0 }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, 0,
|
||||
0, 0, 0, 0 }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
|
||||
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
struct sh_pfc_soc_info sh7786_pinmux_info = {
|
||||
.name = "sh7786_pfc",
|
||||
.reserved_id = PINMUX_RESERVED,
|
||||
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
|
||||
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
|
||||
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
|
||||
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
|
||||
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
.first_gpio = GPIO_PA7,
|
||||
.last_gpio = GPIO_FN_IRL4,
|
||||
|
||||
.gpios = pinmux_gpios,
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.data_regs = pinmux_data_regs,
|
||||
|
||||
.gpio_data = pinmux_data,
|
||||
.gpio_data_size = ARRAY_SIZE(pinmux_data),
|
||||
};
|
||||
582
drivers/pinctrl/sh-pfc/pfc-shx3.c
Normal file
582
drivers/pinctrl/sh-pfc/pfc-shx3.c
Normal file
|
|
@ -0,0 +1,582 @@
|
|||
/*
|
||||
* SH-X3 prototype CPU pinmux
|
||||
*
|
||||
* Copyright (C) 2010 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <cpu/shx3.h>
|
||||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
enum {
|
||||
PINMUX_RESERVED = 0,
|
||||
|
||||
PINMUX_DATA_BEGIN,
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
|
||||
PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
|
||||
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
|
||||
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
|
||||
|
||||
PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
|
||||
PINMUX_DATA_END,
|
||||
|
||||
PINMUX_INPUT_BEGIN,
|
||||
PA7_IN, PA6_IN, PA5_IN, PA4_IN,
|
||||
PA3_IN, PA2_IN, PA1_IN, PA0_IN,
|
||||
PB7_IN, PB6_IN, PB5_IN, PB4_IN,
|
||||
PB3_IN, PB2_IN, PB1_IN, PB0_IN,
|
||||
PC7_IN, PC6_IN, PC5_IN, PC4_IN,
|
||||
PC3_IN, PC2_IN, PC1_IN, PC0_IN,
|
||||
PD7_IN, PD6_IN, PD5_IN, PD4_IN,
|
||||
PD3_IN, PD2_IN, PD1_IN, PD0_IN,
|
||||
PE7_IN, PE6_IN, PE5_IN, PE4_IN,
|
||||
PE3_IN, PE2_IN, PE1_IN, PE0_IN,
|
||||
PF7_IN, PF6_IN, PF5_IN, PF4_IN,
|
||||
PF3_IN, PF2_IN, PF1_IN, PF0_IN,
|
||||
PG7_IN, PG6_IN, PG5_IN, PG4_IN,
|
||||
PG3_IN, PG2_IN, PG1_IN, PG0_IN,
|
||||
|
||||
PH5_IN, PH4_IN,
|
||||
PH3_IN, PH2_IN, PH1_IN, PH0_IN,
|
||||
PINMUX_INPUT_END,
|
||||
|
||||
PINMUX_INPUT_PULLUP_BEGIN,
|
||||
PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
|
||||
PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
|
||||
PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
|
||||
PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
|
||||
PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
|
||||
PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
|
||||
PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
|
||||
PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
|
||||
PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU,
|
||||
PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
|
||||
PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
|
||||
PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
|
||||
PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
|
||||
PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
|
||||
|
||||
PH5_IN_PU, PH4_IN_PU,
|
||||
PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
|
||||
PINMUX_INPUT_PULLUP_END,
|
||||
|
||||
PINMUX_OUTPUT_BEGIN,
|
||||
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
|
||||
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
|
||||
PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
|
||||
PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
|
||||
PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
|
||||
PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
|
||||
PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
|
||||
PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
|
||||
PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
|
||||
PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
|
||||
PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
|
||||
PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
|
||||
PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
|
||||
PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
|
||||
|
||||
PH5_OUT, PH4_OUT,
|
||||
PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
|
||||
PINMUX_OUTPUT_END,
|
||||
|
||||
PINMUX_FUNCTION_BEGIN,
|
||||
PA7_FN, PA6_FN, PA5_FN, PA4_FN,
|
||||
PA3_FN, PA2_FN, PA1_FN, PA0_FN,
|
||||
PB7_FN, PB6_FN, PB5_FN, PB4_FN,
|
||||
PB3_FN, PB2_FN, PB1_FN, PB0_FN,
|
||||
PC7_FN, PC6_FN, PC5_FN, PC4_FN,
|
||||
PC3_FN, PC2_FN, PC1_FN, PC0_FN,
|
||||
PD7_FN, PD6_FN, PD5_FN, PD4_FN,
|
||||
PD3_FN, PD2_FN, PD1_FN, PD0_FN,
|
||||
PE7_FN, PE6_FN, PE5_FN, PE4_FN,
|
||||
PE3_FN, PE2_FN, PE1_FN, PE0_FN,
|
||||
PF7_FN, PF6_FN, PF5_FN, PF4_FN,
|
||||
PF3_FN, PF2_FN, PF1_FN, PF0_FN,
|
||||
PG7_FN, PG6_FN, PG5_FN, PG4_FN,
|
||||
PG3_FN, PG2_FN, PG1_FN, PG0_FN,
|
||||
|
||||
PH5_FN, PH4_FN,
|
||||
PH3_FN, PH2_FN, PH1_FN, PH0_FN,
|
||||
PINMUX_FUNCTION_END,
|
||||
|
||||
PINMUX_MARK_BEGIN,
|
||||
|
||||
D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
|
||||
D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
|
||||
D19_MARK, D18_MARK, D17_MARK, D16_MARK,
|
||||
|
||||
BACK_MARK, BREQ_MARK,
|
||||
WE3_MARK, WE2_MARK,
|
||||
CS6_MARK, CS5_MARK, CS4_MARK,
|
||||
CLKOUTENB_MARK,
|
||||
|
||||
DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
|
||||
DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
|
||||
|
||||
IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
|
||||
|
||||
DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
|
||||
|
||||
SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
|
||||
IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
|
||||
TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
|
||||
RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
|
||||
|
||||
CE2B_MARK, CE2A_MARK, IOIS16_MARK,
|
||||
STATUS1_MARK, STATUS0_MARK,
|
||||
|
||||
IRQOUT_MARK,
|
||||
|
||||
PINMUX_MARK_END,
|
||||
};
|
||||
|
||||
static pinmux_enum_t shx3_pinmux_data[] = {
|
||||
|
||||
/* PA GPIO */
|
||||
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
|
||||
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
|
||||
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
|
||||
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
|
||||
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
|
||||
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
|
||||
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
|
||||
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
|
||||
|
||||
/* PB GPIO */
|
||||
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
|
||||
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
|
||||
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
|
||||
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
|
||||
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
|
||||
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
|
||||
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
|
||||
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
|
||||
|
||||
/* PC GPIO */
|
||||
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
|
||||
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
|
||||
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
|
||||
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
|
||||
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
|
||||
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
|
||||
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
|
||||
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
|
||||
|
||||
/* PD GPIO */
|
||||
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
|
||||
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
|
||||
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
|
||||
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
|
||||
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
|
||||
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
|
||||
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
|
||||
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
|
||||
|
||||
/* PE GPIO */
|
||||
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
|
||||
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
|
||||
PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
|
||||
PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
|
||||
PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
|
||||
PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
|
||||
PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
|
||||
PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
|
||||
|
||||
/* PF GPIO */
|
||||
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
|
||||
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
|
||||
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
|
||||
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
|
||||
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
|
||||
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
|
||||
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
|
||||
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
|
||||
|
||||
/* PG GPIO */
|
||||
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
|
||||
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
|
||||
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
|
||||
PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
|
||||
PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
|
||||
PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
|
||||
PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
|
||||
PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
|
||||
|
||||
/* PH GPIO */
|
||||
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
|
||||
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
|
||||
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
|
||||
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
|
||||
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
|
||||
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
|
||||
|
||||
/* PA FN */
|
||||
PINMUX_DATA(D31_MARK, PA7_FN),
|
||||
PINMUX_DATA(D30_MARK, PA6_FN),
|
||||
PINMUX_DATA(D29_MARK, PA5_FN),
|
||||
PINMUX_DATA(D28_MARK, PA4_FN),
|
||||
PINMUX_DATA(D27_MARK, PA3_FN),
|
||||
PINMUX_DATA(D26_MARK, PA2_FN),
|
||||
PINMUX_DATA(D25_MARK, PA1_FN),
|
||||
PINMUX_DATA(D24_MARK, PA0_FN),
|
||||
|
||||
/* PB FN */
|
||||
PINMUX_DATA(D23_MARK, PB7_FN),
|
||||
PINMUX_DATA(D22_MARK, PB6_FN),
|
||||
PINMUX_DATA(D21_MARK, PB5_FN),
|
||||
PINMUX_DATA(D20_MARK, PB4_FN),
|
||||
PINMUX_DATA(D19_MARK, PB3_FN),
|
||||
PINMUX_DATA(D18_MARK, PB2_FN),
|
||||
PINMUX_DATA(D17_MARK, PB1_FN),
|
||||
PINMUX_DATA(D16_MARK, PB0_FN),
|
||||
|
||||
/* PC FN */
|
||||
PINMUX_DATA(BACK_MARK, PC7_FN),
|
||||
PINMUX_DATA(BREQ_MARK, PC6_FN),
|
||||
PINMUX_DATA(WE3_MARK, PC5_FN),
|
||||
PINMUX_DATA(WE2_MARK, PC4_FN),
|
||||
PINMUX_DATA(CS6_MARK, PC3_FN),
|
||||
PINMUX_DATA(CS5_MARK, PC2_FN),
|
||||
PINMUX_DATA(CS4_MARK, PC1_FN),
|
||||
PINMUX_DATA(CLKOUTENB_MARK, PC0_FN),
|
||||
|
||||
/* PD FN */
|
||||
PINMUX_DATA(DACK3_MARK, PD7_FN),
|
||||
PINMUX_DATA(DACK2_MARK, PD6_FN),
|
||||
PINMUX_DATA(DACK1_MARK, PD5_FN),
|
||||
PINMUX_DATA(DACK0_MARK, PD4_FN),
|
||||
PINMUX_DATA(DREQ3_MARK, PD3_FN),
|
||||
PINMUX_DATA(DREQ2_MARK, PD2_FN),
|
||||
PINMUX_DATA(DREQ1_MARK, PD1_FN),
|
||||
PINMUX_DATA(DREQ0_MARK, PD0_FN),
|
||||
|
||||
/* PE FN */
|
||||
PINMUX_DATA(IRQ3_MARK, PE7_FN),
|
||||
PINMUX_DATA(IRQ2_MARK, PE6_FN),
|
||||
PINMUX_DATA(IRQ1_MARK, PE5_FN),
|
||||
PINMUX_DATA(IRQ0_MARK, PE4_FN),
|
||||
PINMUX_DATA(DRAK3_MARK, PE3_FN),
|
||||
PINMUX_DATA(DRAK2_MARK, PE2_FN),
|
||||
PINMUX_DATA(DRAK1_MARK, PE1_FN),
|
||||
PINMUX_DATA(DRAK0_MARK, PE0_FN),
|
||||
|
||||
/* PF FN */
|
||||
PINMUX_DATA(SCK3_MARK, PF7_FN),
|
||||
PINMUX_DATA(SCK2_MARK, PF6_FN),
|
||||
PINMUX_DATA(SCK1_MARK, PF5_FN),
|
||||
PINMUX_DATA(SCK0_MARK, PF4_FN),
|
||||
PINMUX_DATA(IRL3_MARK, PF3_FN),
|
||||
PINMUX_DATA(IRL2_MARK, PF2_FN),
|
||||
PINMUX_DATA(IRL1_MARK, PF1_FN),
|
||||
PINMUX_DATA(IRL0_MARK, PF0_FN),
|
||||
|
||||
/* PG FN */
|
||||
PINMUX_DATA(TXD3_MARK, PG7_FN),
|
||||
PINMUX_DATA(TXD2_MARK, PG6_FN),
|
||||
PINMUX_DATA(TXD1_MARK, PG5_FN),
|
||||
PINMUX_DATA(TXD0_MARK, PG4_FN),
|
||||
PINMUX_DATA(RXD3_MARK, PG3_FN),
|
||||
PINMUX_DATA(RXD2_MARK, PG2_FN),
|
||||
PINMUX_DATA(RXD1_MARK, PG1_FN),
|
||||
PINMUX_DATA(RXD0_MARK, PG0_FN),
|
||||
|
||||
/* PH FN */
|
||||
PINMUX_DATA(CE2B_MARK, PH5_FN),
|
||||
PINMUX_DATA(CE2A_MARK, PH4_FN),
|
||||
PINMUX_DATA(IOIS16_MARK, PH3_FN),
|
||||
PINMUX_DATA(STATUS1_MARK, PH2_FN),
|
||||
PINMUX_DATA(STATUS0_MARK, PH1_FN),
|
||||
PINMUX_DATA(IRQOUT_MARK, PH0_FN),
|
||||
};
|
||||
|
||||
static struct pinmux_gpio shx3_pinmux_gpios[] = {
|
||||
/* PA */
|
||||
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
|
||||
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
|
||||
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
|
||||
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
|
||||
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
|
||||
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
|
||||
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
|
||||
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
|
||||
|
||||
/* PB */
|
||||
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
|
||||
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
|
||||
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
|
||||
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
|
||||
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
|
||||
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
|
||||
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
|
||||
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
|
||||
|
||||
/* PC */
|
||||
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
|
||||
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
|
||||
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
|
||||
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
|
||||
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
|
||||
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
|
||||
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
|
||||
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
|
||||
|
||||
/* PD */
|
||||
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
|
||||
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
|
||||
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
|
||||
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
|
||||
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
|
||||
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
|
||||
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
|
||||
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
|
||||
|
||||
/* PE */
|
||||
PINMUX_GPIO(GPIO_PE7, PE7_DATA),
|
||||
PINMUX_GPIO(GPIO_PE6, PE6_DATA),
|
||||
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
|
||||
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
|
||||
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
|
||||
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
|
||||
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
|
||||
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
|
||||
|
||||
/* PF */
|
||||
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
|
||||
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
|
||||
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
|
||||
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
|
||||
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
|
||||
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
|
||||
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
|
||||
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
|
||||
|
||||
/* PG */
|
||||
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
|
||||
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
|
||||
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
|
||||
PINMUX_GPIO(GPIO_PG4, PG4_DATA),
|
||||
PINMUX_GPIO(GPIO_PG3, PG3_DATA),
|
||||
PINMUX_GPIO(GPIO_PG2, PG2_DATA),
|
||||
PINMUX_GPIO(GPIO_PG1, PG1_DATA),
|
||||
PINMUX_GPIO(GPIO_PG0, PG0_DATA),
|
||||
|
||||
/* PH */
|
||||
PINMUX_GPIO(GPIO_PH5, PH5_DATA),
|
||||
PINMUX_GPIO(GPIO_PH4, PH4_DATA),
|
||||
PINMUX_GPIO(GPIO_PH3, PH3_DATA),
|
||||
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
|
||||
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
|
||||
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
|
||||
|
||||
/* FN */
|
||||
PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
|
||||
};
|
||||
|
||||
static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
|
||||
{ PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
|
||||
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
|
||||
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
|
||||
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
|
||||
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
|
||||
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
|
||||
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
|
||||
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
|
||||
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
|
||||
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
|
||||
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
|
||||
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
|
||||
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
|
||||
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
|
||||
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
|
||||
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
|
||||
PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, },
|
||||
},
|
||||
{ PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
|
||||
PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
|
||||
PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
|
||||
PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
|
||||
PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
|
||||
PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
|
||||
PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
|
||||
PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
|
||||
PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU,
|
||||
PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
|
||||
PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
|
||||
PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
|
||||
PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
|
||||
PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
|
||||
PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
|
||||
PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
|
||||
PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, },
|
||||
},
|
||||
{ PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
|
||||
PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
|
||||
PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
|
||||
PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
|
||||
PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
|
||||
PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
|
||||
PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
|
||||
PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
|
||||
PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU,
|
||||
PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
|
||||
PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
|
||||
PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
|
||||
PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
|
||||
PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
|
||||
PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
|
||||
PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
|
||||
PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, },
|
||||
},
|
||||
{ PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
|
||||
PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
|
||||
PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
|
||||
PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
|
||||
PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
|
||||
PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
|
||||
PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
|
||||
PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
|
||||
PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
|
||||
PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
|
||||
PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
|
||||
PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
|
||||
PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
|
||||
PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, },
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
|
||||
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
|
||||
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
struct sh_pfc_soc_info shx3_pinmux_info = {
|
||||
.name = "shx3_pfc",
|
||||
.reserved_id = PINMUX_RESERVED,
|
||||
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
|
||||
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
|
||||
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
|
||||
PINMUX_INPUT_PULLUP_END },
|
||||
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
|
||||
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
.first_gpio = GPIO_PA7,
|
||||
.last_gpio = GPIO_FN_STATUS0,
|
||||
.gpios = shx3_pinmux_gpios,
|
||||
.gpio_data = shx3_pinmux_data,
|
||||
.gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
|
||||
.cfg_regs = shx3_pinmux_config_regs,
|
||||
.data_regs = shx3_pinmux_data_regs,
|
||||
};
|
||||
463
drivers/pinctrl/sh-pfc/pinctrl.c
Normal file
463
drivers/pinctrl/sh-pfc/pinctrl.c
Normal file
|
|
@ -0,0 +1,463 @@
|
|||
/*
|
||||
* SuperH Pin Function Controller pinmux support.
|
||||
*
|
||||
* Copyright (C) 2012 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#define DRV_NAME "sh-pfc"
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "core.h"
|
||||
|
||||
struct sh_pfc_pinctrl {
|
||||
struct pinctrl_dev *pctl;
|
||||
struct sh_pfc *pfc;
|
||||
|
||||
struct pinmux_gpio **functions;
|
||||
unsigned int nr_functions;
|
||||
|
||||
struct pinctrl_pin_desc *pads;
|
||||
unsigned int nr_pads;
|
||||
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pmx->nr_pads;
|
||||
}
|
||||
|
||||
static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
|
||||
unsigned selector)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pmx->pads[selector].name;
|
||||
}
|
||||
|
||||
static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
|
||||
const unsigned **pins, unsigned *num_pins)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*pins = &pmx->pads[group].number;
|
||||
*num_pins = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
|
||||
unsigned offset)
|
||||
{
|
||||
seq_printf(s, "%s", DRV_NAME);
|
||||
}
|
||||
|
||||
static struct pinctrl_ops sh_pfc_pinctrl_ops = {
|
||||
.get_groups_count = sh_pfc_get_groups_count,
|
||||
.get_group_name = sh_pfc_get_group_name,
|
||||
.get_group_pins = sh_pfc_get_group_pins,
|
||||
.pin_dbg_show = sh_pfc_pin_dbg_show,
|
||||
};
|
||||
|
||||
static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pmx->nr_functions;
|
||||
}
|
||||
|
||||
static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
|
||||
unsigned selector)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pmx->functions[selector]->name;
|
||||
}
|
||||
|
||||
static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
|
||||
const char * const **groups,
|
||||
unsigned * const num_groups)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = &pmx->functions[func]->name;
|
||||
*num_groups = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
|
||||
unsigned group)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
|
||||
unsigned group)
|
||||
{
|
||||
}
|
||||
|
||||
static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
|
||||
{
|
||||
if (sh_pfc_config_gpio(pfc, offset,
|
||||
PINMUX_TYPE_FUNCTION,
|
||||
GPIO_CFG_DRYRUN) != 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (sh_pfc_config_gpio(pfc, offset,
|
||||
PINMUX_TYPE_FUNCTION,
|
||||
GPIO_CFG_REQ) != 0)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
|
||||
int new_type)
|
||||
{
|
||||
unsigned long flags;
|
||||
int pinmux_type;
|
||||
int ret = -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
|
||||
pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
|
||||
|
||||
/*
|
||||
* See if the present config needs to first be de-configured.
|
||||
*/
|
||||
switch (pinmux_type) {
|
||||
case PINMUX_TYPE_GPIO:
|
||||
break;
|
||||
case PINMUX_TYPE_OUTPUT:
|
||||
case PINMUX_TYPE_INPUT:
|
||||
case PINMUX_TYPE_INPUT_PULLUP:
|
||||
case PINMUX_TYPE_INPUT_PULLDOWN:
|
||||
sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
|
||||
break;
|
||||
default:
|
||||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Dry run
|
||||
*/
|
||||
if (sh_pfc_config_gpio(pfc, offset, new_type,
|
||||
GPIO_CFG_DRYRUN) != 0)
|
||||
goto err;
|
||||
|
||||
/*
|
||||
* Request
|
||||
*/
|
||||
if (sh_pfc_config_gpio(pfc, offset, new_type,
|
||||
GPIO_CFG_REQ) != 0)
|
||||
goto err;
|
||||
|
||||
pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
|
||||
pfc->info->gpios[offset].flags |= new_type;
|
||||
|
||||
ret = 0;
|
||||
|
||||
err:
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned offset)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct sh_pfc *pfc = pmx->pfc;
|
||||
unsigned long flags;
|
||||
int ret, pinmux_type;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
|
||||
pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
|
||||
|
||||
switch (pinmux_type) {
|
||||
case PINMUX_TYPE_FUNCTION:
|
||||
pr_notice_once("Use of GPIO API for function requests is "
|
||||
"deprecated, convert to pinctrl\n");
|
||||
/* handle for now */
|
||||
ret = sh_pfc_config_function(pfc, offset);
|
||||
if (unlikely(ret < 0))
|
||||
goto err;
|
||||
|
||||
break;
|
||||
case PINMUX_TYPE_GPIO:
|
||||
case PINMUX_TYPE_INPUT:
|
||||
case PINMUX_TYPE_OUTPUT:
|
||||
break;
|
||||
default:
|
||||
pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
|
||||
ret = -ENOTSUPP;
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
|
||||
err:
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned offset)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct sh_pfc *pfc = pmx->pfc;
|
||||
unsigned long flags;
|
||||
int pinmux_type;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
|
||||
pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
|
||||
|
||||
sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
|
||||
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
}
|
||||
|
||||
static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned offset, bool input)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
|
||||
|
||||
return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
|
||||
}
|
||||
|
||||
static struct pinmux_ops sh_pfc_pinmux_ops = {
|
||||
.get_functions_count = sh_pfc_get_functions_count,
|
||||
.get_function_name = sh_pfc_get_function_name,
|
||||
.get_function_groups = sh_pfc_get_function_groups,
|
||||
.enable = sh_pfc_noop_enable,
|
||||
.disable = sh_pfc_noop_disable,
|
||||
.gpio_request_enable = sh_pfc_gpio_request_enable,
|
||||
.gpio_disable_free = sh_pfc_gpio_disable_free,
|
||||
.gpio_set_direction = sh_pfc_gpio_set_direction,
|
||||
};
|
||||
|
||||
static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
|
||||
unsigned long *config)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct sh_pfc *pfc = pmx->pfc;
|
||||
|
||||
*config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
|
||||
unsigned long config)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
/* Validate the new type */
|
||||
if (config >= PINMUX_FLAG_TYPE)
|
||||
return -EINVAL;
|
||||
|
||||
return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
|
||||
}
|
||||
|
||||
static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned pin)
|
||||
{
|
||||
const char *pinmux_type_str[] = {
|
||||
[PINMUX_TYPE_NONE] = "none",
|
||||
[PINMUX_TYPE_FUNCTION] = "function",
|
||||
[PINMUX_TYPE_GPIO] = "gpio",
|
||||
[PINMUX_TYPE_OUTPUT] = "output",
|
||||
[PINMUX_TYPE_INPUT] = "input",
|
||||
[PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
|
||||
[PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
|
||||
};
|
||||
unsigned long config;
|
||||
int rc;
|
||||
|
||||
rc = sh_pfc_pinconf_get(pctldev, pin, &config);
|
||||
if (unlikely(rc != 0))
|
||||
return;
|
||||
|
||||
seq_printf(s, " %s", pinmux_type_str[config]);
|
||||
}
|
||||
|
||||
static struct pinconf_ops sh_pfc_pinconf_ops = {
|
||||
.pin_config_get = sh_pfc_pinconf_get,
|
||||
.pin_config_set = sh_pfc_pinconf_set,
|
||||
.pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
|
||||
};
|
||||
|
||||
static struct pinctrl_gpio_range sh_pfc_gpio_range = {
|
||||
.name = DRV_NAME,
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc sh_pfc_pinctrl_desc = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.pctlops = &sh_pfc_pinctrl_ops,
|
||||
.pmxops = &sh_pfc_pinmux_ops,
|
||||
.confops = &sh_pfc_pinconf_ops,
|
||||
};
|
||||
|
||||
static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx,
|
||||
struct pinmux_gpio *gpio, unsigned offset)
|
||||
{
|
||||
struct pinmux_data_reg *dummy;
|
||||
unsigned long flags;
|
||||
int bit;
|
||||
|
||||
gpio->flags &= ~PINMUX_FLAG_TYPE;
|
||||
|
||||
if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
|
||||
gpio->flags |= PINMUX_TYPE_GPIO;
|
||||
else {
|
||||
gpio->flags |= PINMUX_TYPE_FUNCTION;
|
||||
|
||||
spin_lock_irqsave(&pmx->lock, flags);
|
||||
pmx->nr_functions++;
|
||||
spin_unlock_irqrestore(&pmx->lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
/* pinmux ranges -> pinctrl pin descs */
|
||||
static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
|
||||
{
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1;
|
||||
|
||||
pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads,
|
||||
GFP_KERNEL);
|
||||
if (unlikely(!pmx->pads)) {
|
||||
pmx->nr_pads = 0;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
|
||||
/*
|
||||
* We don't necessarily have a 1:1 mapping between pin and linux
|
||||
* GPIO number, as the latter maps to the associated enum_id.
|
||||
* Care needs to be taken to translate back to pin space when
|
||||
* dealing with any pin configurations.
|
||||
*/
|
||||
for (i = 0; i < pmx->nr_pads; i++) {
|
||||
struct pinctrl_pin_desc *pin = pmx->pads + i;
|
||||
struct pinmux_gpio *gpio = pfc->info->gpios + i;
|
||||
|
||||
pin->number = pfc->info->first_gpio + i;
|
||||
pin->name = gpio->name;
|
||||
|
||||
/* XXX */
|
||||
if (unlikely(!gpio->enum_id))
|
||||
continue;
|
||||
|
||||
sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
|
||||
sh_pfc_pinctrl_desc.pins = pmx->pads;
|
||||
sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
|
||||
{
|
||||
unsigned long flags;
|
||||
int i, fn;
|
||||
|
||||
pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions *
|
||||
sizeof(*pmx->functions), GFP_KERNEL);
|
||||
if (unlikely(!pmx->functions))
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_irqsave(&pmx->lock, flags);
|
||||
|
||||
for (i = fn = 0; i < pmx->nr_pads; i++) {
|
||||
struct pinmux_gpio *gpio = pfc->info->gpios + i;
|
||||
|
||||
if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
|
||||
pmx->functions[fn++] = gpio;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&pmx->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx;
|
||||
int ret;
|
||||
|
||||
pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
|
||||
if (unlikely(!pmx))
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_init(&pmx->lock);
|
||||
|
||||
pmx->pfc = pfc;
|
||||
pfc->pinctrl = pmx;
|
||||
|
||||
ret = sh_pfc_map_gpios(pfc, pmx);
|
||||
if (unlikely(ret != 0))
|
||||
return ret;
|
||||
|
||||
ret = sh_pfc_map_functions(pfc, pmx);
|
||||
if (unlikely(ret != 0))
|
||||
return ret;
|
||||
|
||||
pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx);
|
||||
if (IS_ERR(pmx->pctl))
|
||||
return PTR_ERR(pmx->pctl);
|
||||
|
||||
sh_pfc_gpio_range.npins = pfc->info->last_gpio
|
||||
- pfc->info->first_gpio + 1;
|
||||
sh_pfc_gpio_range.base = pfc->info->first_gpio;
|
||||
sh_pfc_gpio_range.pin_base = pfc->info->first_gpio;
|
||||
|
||||
pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
|
||||
|
||||
pinctrl_unregister(pmx->pctl);
|
||||
|
||||
pfc->pinctrl = NULL;
|
||||
return 0;
|
||||
}
|
||||
195
drivers/pinctrl/sh-pfc/sh_pfc.h
Normal file
195
drivers/pinctrl/sh-pfc/sh_pfc.h
Normal file
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* SuperH Pin Function Controller Support
|
||||
*
|
||||
* Copyright (c) 2008 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SH_PFC_H
|
||||
#define __SH_PFC_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
typedef unsigned short pinmux_enum_t;
|
||||
typedef unsigned short pinmux_flag_t;
|
||||
|
||||
enum {
|
||||
PINMUX_TYPE_NONE,
|
||||
|
||||
PINMUX_TYPE_FUNCTION,
|
||||
PINMUX_TYPE_GPIO,
|
||||
PINMUX_TYPE_OUTPUT,
|
||||
PINMUX_TYPE_INPUT,
|
||||
PINMUX_TYPE_INPUT_PULLUP,
|
||||
PINMUX_TYPE_INPUT_PULLDOWN,
|
||||
|
||||
PINMUX_FLAG_TYPE, /* must be last */
|
||||
};
|
||||
|
||||
#define PINMUX_FLAG_DBIT_SHIFT 5
|
||||
#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
|
||||
#define PINMUX_FLAG_DREG_SHIFT 10
|
||||
#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
|
||||
|
||||
struct pinmux_gpio {
|
||||
pinmux_enum_t enum_id;
|
||||
pinmux_flag_t flags;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
#define PINMUX_GPIO(gpio, data_or_mark) \
|
||||
[gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE }
|
||||
|
||||
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
|
||||
|
||||
struct pinmux_cfg_reg {
|
||||
unsigned long reg, reg_width, field_width;
|
||||
unsigned long *cnt;
|
||||
pinmux_enum_t *enum_ids;
|
||||
unsigned long *var_field_width;
|
||||
};
|
||||
|
||||
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
|
||||
.reg = r, .reg_width = r_width, .field_width = f_width, \
|
||||
.cnt = (unsigned long [r_width / f_width]) {}, \
|
||||
.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
|
||||
|
||||
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
|
||||
.reg = r, .reg_width = r_width, \
|
||||
.cnt = (unsigned long [r_width]) {}, \
|
||||
.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
|
||||
.enum_ids = (pinmux_enum_t [])
|
||||
|
||||
struct pinmux_data_reg {
|
||||
unsigned long reg, reg_width, reg_shadow;
|
||||
pinmux_enum_t *enum_ids;
|
||||
void __iomem *mapped_reg;
|
||||
};
|
||||
|
||||
#define PINMUX_DATA_REG(name, r, r_width) \
|
||||
.reg = r, .reg_width = r_width, \
|
||||
.enum_ids = (pinmux_enum_t [r_width]) \
|
||||
|
||||
struct pinmux_irq {
|
||||
int irq;
|
||||
pinmux_enum_t *enum_ids;
|
||||
};
|
||||
|
||||
#define PINMUX_IRQ(irq_nr, ids...) \
|
||||
{ .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \
|
||||
|
||||
struct pinmux_range {
|
||||
pinmux_enum_t begin;
|
||||
pinmux_enum_t end;
|
||||
pinmux_enum_t force;
|
||||
};
|
||||
|
||||
struct sh_pfc_soc_info {
|
||||
char *name;
|
||||
pinmux_enum_t reserved_id;
|
||||
struct pinmux_range data;
|
||||
struct pinmux_range input;
|
||||
struct pinmux_range input_pd;
|
||||
struct pinmux_range input_pu;
|
||||
struct pinmux_range output;
|
||||
struct pinmux_range mark;
|
||||
struct pinmux_range function;
|
||||
|
||||
unsigned first_gpio, last_gpio;
|
||||
|
||||
struct pinmux_gpio *gpios;
|
||||
struct pinmux_cfg_reg *cfg_regs;
|
||||
struct pinmux_data_reg *data_regs;
|
||||
|
||||
pinmux_enum_t *gpio_data;
|
||||
unsigned int gpio_data_size;
|
||||
|
||||
struct pinmux_irq *gpio_irq;
|
||||
unsigned int gpio_irq_size;
|
||||
|
||||
unsigned long unlock_reg;
|
||||
};
|
||||
|
||||
enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
|
||||
|
||||
/* helper macro for port */
|
||||
#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
|
||||
|
||||
#define PORT_10(fn, pfx, sfx) \
|
||||
PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
|
||||
PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
|
||||
PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
|
||||
PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
|
||||
PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
|
||||
|
||||
#define PORT_90(fn, pfx, sfx) \
|
||||
PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
|
||||
PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
|
||||
PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
|
||||
PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
|
||||
PORT_10(fn, pfx##9, sfx)
|
||||
|
||||
#define _PORT_ALL(pfx, sfx) pfx##_##sfx
|
||||
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
|
||||
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
|
||||
#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
|
||||
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
|
||||
|
||||
/* helper macro for pinmux_enum_t */
|
||||
#define PORT_DATA_I(nr) \
|
||||
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
|
||||
|
||||
#define PORT_DATA_I_PD(nr) \
|
||||
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
|
||||
PORT##nr##_IN, PORT##nr##_IN_PD)
|
||||
|
||||
#define PORT_DATA_I_PU(nr) \
|
||||
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
|
||||
PORT##nr##_IN, PORT##nr##_IN_PU)
|
||||
|
||||
#define PORT_DATA_I_PU_PD(nr) \
|
||||
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
|
||||
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
|
||||
|
||||
#define PORT_DATA_O(nr) \
|
||||
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
|
||||
|
||||
#define PORT_DATA_IO(nr) \
|
||||
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
|
||||
PORT##nr##_IN)
|
||||
|
||||
#define PORT_DATA_IO_PD(nr) \
|
||||
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
|
||||
PORT##nr##_IN, PORT##nr##_IN_PD)
|
||||
|
||||
#define PORT_DATA_IO_PU(nr) \
|
||||
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
|
||||
PORT##nr##_IN, PORT##nr##_IN_PU)
|
||||
|
||||
#define PORT_DATA_IO_PU_PD(nr) \
|
||||
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
|
||||
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
|
||||
|
||||
/* helper macro for top 4 bits in PORTnCR */
|
||||
#define _PCRH(in, in_pd, in_pu, out) \
|
||||
0, (out), (in), 0, \
|
||||
0, 0, 0, 0, \
|
||||
0, 0, (in_pd), 0, \
|
||||
0, 0, (in_pu), 0
|
||||
|
||||
#define PORTCR(nr, reg) \
|
||||
{ \
|
||||
PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
|
||||
_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
|
||||
PORT##nr##_IN_PU, PORT##nr##_OUT), \
|
||||
PORT##nr##_FN0, PORT##nr##_FN1, \
|
||||
PORT##nr##_FN2, PORT##nr##_FN3, \
|
||||
PORT##nr##_FN4, PORT##nr##_FN5, \
|
||||
PORT##nr##_FN6, PORT##nr##_FN7 } \
|
||||
}
|
||||
|
||||
#endif /* __SH_PFC_H */
|
||||
Loading…
Reference in a new issue