From 7920eae676c938b2a1f81eee41c7856006785dfe Mon Sep 17 00:00:00 2001
From: Prakruthi Deepak Heragu <pheragu@quicinc.com>
Date: Wed, 14 Aug 2019 16:59:49 -0700
Subject: [PATCH] dt-bindings: Add device-tree bindings for Watchdog driver

Add the device-tree bindings documentation for Watchdog timer.

Change-Id: Id0fc6a469e03e2dfa22def4f9ee82578f3fa714c
---
 bindings/arm/msm/msm_watchdog.yaml | 89 ++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 bindings/arm/msm/msm_watchdog.yaml

diff --git a/bindings/arm/msm/msm_watchdog.yaml b/bindings/arm/msm/msm_watchdog.yaml
new file mode 100644
index 000000000000..8309dacc5508
--- /dev/null
+++ b/bindings/arm/msm/msm_watchdog.yaml
@@ -0,0 +1,89 @@
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm/msm/msm_watchdog.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QTI MSM Watchdog
+
+maintainers:
+  - Prakruthi Deepak Heragu <pheragu@quicinc.com>
+
+description: |+
+  Watchdog timer is configured with a bark and a bite time.
+  If the watchdog is not "pet" at regular intervals, the system
+  is assumed to have become non responsive and needs to be reset.
+  A warning in the form of a bark timeout leads to a bark interrupt
+  and a kernel panic. If the watchdog timer is still not reset,
+  a bite timeout occurs, which is an interrupt in the secure mode,
+  which leads to a reset of the SOC via the secure watchdog. The
+  driver needs the petting time, and the bark timeout to be programmed
+  into the watchdog, as well as the bark and bite irqs.
+
+  The device tree parameters for the watchdog are:
+
+properties:
+  compatible:
+    Usage: required
+    Value type: <string>
+    Definition: Must be "qcom,msm-watchdog"
+
+  reg:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: offset and length of the register set for the watchdog block.
+
+  reg-names:
+    Usage: required
+    Value type: <string>
+    Definition: names corresponding to each reg property value (base required).
+          "wdt-base" - physical base address of watchdog timer registers
+          "wdt-absent-base" - physical base address of watchdog absent register
+
+  interrupts:
+     Usage: required
+     Value type: <prop-encoded-array>
+     Definition: should contain bark and bite irq numbers
+
+  qcom,pet-time:
+     Usage: required
+     Value type: <u32>
+     Definition: Non zero time interval at which watchdog should be pet in ms.
+
+  qcom,bark-time:
+     Usage: required
+     Value type: <u32>
+     Definition: Non zero timeout value for a watchdog bark in ms.
+
+  qcom,userspace-watchdog:
+     Usage: optional
+     Value type: <boolean>
+     Definition: Allow enabling the userspace-watchdog feature. This feature
+          requires userspace to pet the watchdog every qcom,pet-time interval
+          in addition to the existing kernel-level checks.
+          This feature is supported through device sysfs files.
+
+  qcom,ipi-ping:
+     Usage: optional
+     Value type: <boolean>
+     Definition: send keep alive ping to other cpus if present
+
+  qcom,wakeup-enable:
+     Usage: optional
+     Value type: <boolean>
+     Definition: enable non secure watchdog to freeze / unfreeze
+          automatically across suspend / resume path.
+
+example:
+  - |
+    wdog: qcom,wdt@17c10000{
+	compatible = "qcom,msm-watchdog";
+	reg = <0x17c10000 0x1000>;
+	reg-names = "wdt-base";
+	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                <0 1 IRQ_TYPE_LEVEL_HIGH>;
+	qcom,bark-time = <11000>;
+	qcom,pet-time = <9360>;
+	qcom,ipi-ping;
+	qcom,wakeup-enable;
+    };
+...