From 603d76db8051cc4d9a0bc9d8427b88358fe06935 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 23 Oct 2019 16:56:03 -0700 Subject: [PATCH] msm: pcie: scale CX and rate change after DRV resume PCIe will vote for maximum CX and rate change during DRV resume. Scale CX and rate change based on final GEN speed after PCIe regains control. Change-Id: I004f4bba6ca12944cd48fd56fa5a1290867c82a9 Signed-off-by: Tony Truong --- drivers/pci/controller/pci-msm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index 6160dd1581d8..e249b966152a 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -6834,6 +6834,14 @@ static int msm_pcie_drv_resume(struct msm_pcie_dev_t *pcie_dev) msm_pcie_scale_link_bandwidth(pcie_dev, current_link_speed); + /* scale CX and rate change based on current GEN speed */ + current_link_speed = readl_relaxed(pcie_dev->dm_core + + PCIE20_CAP_LINKCTRLSTATUS); + current_link_speed = ((current_link_speed >> 16) & + PCI_EXP_LNKSTA_CLS); + + msm_pcie_scale_link_bandwidth(pcie_dev, current_link_speed); + /* always ungate clkreq */ msm_pcie_write_reg_field(pcie_dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE,