From 7c6e0d92058d97463de8bfadfde4147a2c9352db Mon Sep 17 00:00:00 2001 From: houdz1 Date: Mon, 25 Jan 2021 09:42:44 +0800 Subject: [PATCH] dts/denver/panel: change the dsi timing RF requirement change the mipi clock to 1099M. So we also change the dsi timing. Change-Id: I3d7abcce677b38404c2bf460e628e68b51fc505b Signed-off-by: houdz1 Reviewed-on: https://gerrit.mot.com/1860159 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Shanshan Dai Reviewed-by: Huosheng Liao Submit-Approved: Jira Key --- qcom/denver-display.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/denver-display.dtsi b/qcom/denver-display.dtsi index 936e1016d139..a9907115302e 100644 --- a/qcom/denver-display.dtsi +++ b/qcom/denver-display.dtsi @@ -151,11 +151,11 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-t-clk-post = <0x0F>; - qcom,mdss-dsi-t-clk-pre = <0x37>; + qcom,mdss-dsi-t-clk-pre = <0x3B>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 - 0A 06 02 04 00]; + 0A 09 02 04 00]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; }; @@ -192,11 +192,11 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-t-clk-post = <0x0F>; - qcom,mdss-dsi-t-clk-pre = <0x37>; + qcom,mdss-dsi-t-clk-pre = <0x3B>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 - 0A 06 02 04 00]; + 0A 09 02 04 00]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; };