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Merge with rsync://fileserver/linux

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Update to Linus latest
This commit is contained in:
Thomas Gleixner 2005-06-26 23:20:36 +02:00 • committed by Thomas Gleixner
commit 7ca6448dbf
3076 changed files with 187437 additions and 71584 deletions
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10
include/asm-alpha/agp.h
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@ -10,4 +10,14 @@
#define flush_agp_mappings()
#define flush_agp_cache() mb()
/* Convert a physical address to an address suitable for the GART. */
#define phys_to_gart(x) (x)
#define gart_to_phys(x) (x)
/* GATT allocation. Returns/accepts GATT kernel virtual address. */
#define alloc_gatt_pages(order) \
((char *)__get_free_pages(GFP_KERNEL, (order)))
#define free_gatt_pages(table, order) \
free_pages((unsigned long)(table), (order))
#endif

3
include/asm-alpha/mmzone.h
View file

@ -57,7 +57,6 @@ PLAT_NODE_DATA_LOCALNR(unsigned long p, int n)
* Given a kernel address, find the home node of the underlying memory.
*/
#define kvaddr_to_nid(kaddr) pa_to_nid(__pa(kaddr))
#define node_mem_map(nid) (NODE_DATA(nid)->node_mem_map)
#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
#define local_mapnr(kvaddr) \
@ -108,7 +107,7 @@ PLAT_NODE_DATA_LOCALNR(unsigned long p, int n)
#define pfn_to_page(pfn) \
({ \
unsigned long kaddr = (unsigned long)__va((pfn) << PAGE_SHIFT); \
(node_mem_map(kvaddr_to_nid(kaddr)) + local_mapnr(kaddr)); \
(NODE_DATA(kvaddr_to_nid(kaddr))->node_mem_map + local_mapnr(kaddr)); \
})
#define page_to_pfn(page) \

2
include/asm-alpha/smp.h
View file

@ -43,7 +43,7 @@ extern struct cpuinfo_alpha cpu_data[NR_CPUS];
#define PROC_CHANGE_PENALTY 20
#define hard_smp_processor_id() __hard_smp_processor_id()
#define smp_processor_id() (current_thread_info()->cpu)
#define raw_smp_processor_id() (current_thread_info()->cpu)
extern cpumask_t cpu_present_mask;
extern cpumask_t cpu_online_map;

151
include/asm-arm/arch-aaec2000/aaec2000.h Normal file
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@ -0,0 +1,151 @@
/*
* linux/include/asm-arm/arch-aaec2000/aaec2000.h
*
* AAEC-2000 registers definition
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_AAEC2000_H
#define __ASM_ARCH_AAEC2000_H
#ifndef __ASM_ARCH_HARDWARE_H
#error You must include hardware.h not this file
#endif /* __ASM_ARCH_HARDWARE_H */
/* Interrupt controller */
#define IRQ_BASE __REG(0x80000500)
#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
#define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */
#define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */
#define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */
/* UART 1 */
#define UART1_BASE __REG(0x80000600)
#define UART1_DR __REG(0x80000600) /* Data/FIFO Register */
#define UART1_LCR __REG(0x80000604) /* Link Control Register */
#define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */
#define UART1_CR __REG(0x8000060c) /* Control Register */
#define UART1_SR __REG(0x80000610) /* Status Register */
#define UART1_INT __REG(0x80000614) /* Interrupt Status Register */
#define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */
#define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */
/* UART 2 */
#define UART2_BASE __REG(0x80000700)
#define UART2_DR __REG(0x80000700) /* Data/FIFO Register */
#define UART2_LCR __REG(0x80000704) /* Link Control Register */
#define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */
#define UART2_CR __REG(0x8000070c) /* Control Register */
#define UART2_SR __REG(0x80000710) /* Status Register */
#define UART2_INT __REG(0x80000714) /* Interrupt Status Register */
#define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */
#define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */
/* UART 3 */
#define UART3_BASE __REG(0x80000800)
#define UART3_DR __REG(0x80000800) /* Data/FIFO Register */
#define UART3_LCR __REG(0x80000804) /* Link Control Register */
#define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */
#define UART3_CR __REG(0x8000080c) /* Control Register */
#define UART3_SR __REG(0x80000810) /* Status Register */
#define UART3_INT __REG(0x80000814) /* Interrupt Status Register */
#define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */
#define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */
/* These are used in some places */
#define _UART1_BASE __PREG(UART1_BASE)
#define _UART2_BASE __PREG(UART2_BASE)
#define _UART3_BASE __PREG(UART3_BASE)
/* UART Registers Offsets */
#define UART_DR 0x00
#define UART_LCR 0x04
#define UART_BRCR 0x08
#define UART_CR 0x0c
#define UART_SR 0x10
#define UART_INT 0x14
#define UART_INTM 0x18
#define UART_INTRES 0x1c
/* UART_LCR Bitmask */
#define UART_LCR_BRK (1 << 0) /* Send Break */
#define UART_LCR_PEN (1 << 1) /* Parity Enable */
#define UART_LCR_EP (1 << 2) /* Even/Odd Parity */
#define UART_LCR_S2 (1 << 3) /* One/Two Stop bits */
#define UART_LCR_FIFO (1 << 4) /* FIFO Enable */
#define UART_LCR_WL5 (0 << 5) /* Word Length - 5 bits */
#define UART_LCR_WL6 (1 << 5) /* Word Length - 6 bits */
#define UART_LCR_WL7 (1 << 6) /* Word Length - 7 bits */
#define UART_LCR_WL8 (1 << 7) /* Word Length - 8 bits */
/* UART_CR Bitmask */
#define UART_CR_EN (1 << 0) /* UART Enable */
#define UART_CR_SIR (1 << 1) /* IrDA SIR Enable */
#define UART_CR_SIRLP (1 << 2) /* Low Power IrDA Enable */
#define UART_CR_RXP (1 << 3) /* Receive Pin Polarity */
#define UART_CR_TXP (1 << 4) /* Transmit Pin Polarity */
#define UART_CR_MXP (1 << 5) /* Modem Pin Polarity */
#define UART_CR_LOOP (1 << 6) /* Loopback Mode */
/* UART_SR Bitmask */
#define UART_SR_CTS (1 << 0) /* Clear To Send Status */
#define UART_SR_DSR (1 << 1) /* Data Set Ready Status */
#define UART_SR_DCD (1 << 2) /* Data Carrier Detect Status */
#define UART_SR_TxBSY (1 << 3) /* Transmitter Busy Status */
#define UART_SR_RxFE (1 << 4) /* Receive FIFO Empty Status */
#define UART_SR_TxFF (1 << 5) /* Transmit FIFO Full Status */
#define UART_SR_RxFF (1 << 6) /* Receive FIFO Full Status */
#define UART_SR_TxFE (1 << 7) /* Transmit FIFO Empty Status */
/* UART_INT Bitmask */
#define UART_INT_RIS (1 << 0) /* Rx Interrupt */
#define UART_INT_TIS (1 << 1) /* Tx Interrupt */
#define UART_INT_MIS (1 << 2) /* Modem Interrupt */
#define UART_INT_RTIS (1 << 3) /* Receive Timeout Interrupt */
/* Timer 1 */
#define TIMER1_BASE __REG(0x80000c00)
#define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */
#define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */
#define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */
#define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */
/* Timer 2 */
#define TIMER2_BASE __REG(0x80000d00)
#define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */
#define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */
#define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */
#define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */
/* Timer 3 */
#define TIMER3_BASE __REG(0x80000e00)
#define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */
#define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */
#define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */
#define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */
/* Timer Control register bits */
#define TIMER_CTRL_ENABLE (1 << 7) /* Enable (Start° Timer */
#define TIMER_CTRL_PERIODIC (1 << 6) /* Periodic Running Mode */
#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
#define TIMER_CTRL_CLKSEL_508K (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
#define TIMER_CTRL_CLKSEL_2K (0 << 3) /* 2KHz Clock Select (Timer 1, 2)*/
/* Power and State Control */
#define POWER_BASE __REG(0x80000400)
#define POWER_PWRSR __REG(0x80000400) /* Power Status Register */
#define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */
#define POWER_HALT __REG(0x80000408) /* Power Idle Mode */
#define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */
#define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */
#define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */
#define POWER_TEOI __REG(0x80000418) /* Tick EoI */
#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */
#endif /* __ARM_ARCH_AAEC2000_H */

36
include/asm-arm/arch-aaec2000/debug-macro.S Normal file
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@ -0,0 +1,36 @@
/* linux/include/asm-arm/arch-aaec2000/debug-macro.S
*
* Debugging macro include header
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x80000000 @ physical
movne \rx, #io_p2v(0x80000000) @ virtual
orr \rx, \rx, #0x00000800
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0]
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #0x10]
tst \rd, #(1 << 7)
beq 1002b
.endm
.macro waituart,rd,rx
#if 0
1001: ldr \rd, [\rx, #0x10]
tst \rd, #(1 << 5)
beq 1001b
#endif
.endm

17
include/asm-arm/arch-aaec2000/dma.h Normal file
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@ -0,0 +1,17 @@
/*
* linux/include/asm-arm/arch-aaec2000/dma.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#define MAX_DMA_ADDRESS 0xffffffff
#define MAX_DMA_CHANNELS 0
#endif

33
include/asm-arm/arch-aaec2000/entry-macro.S Normal file
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@ -0,0 +1,33 @@
/*
* linux/include/asm-arm/arch-aaec2000/entry-macro.S
*
* Low-level IRQ helper for aaec-2000 based platforms
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xf8000000
add r4, r4, #0x00000500
mov \base, r4
ldr \irqstat, [\base, #0]
cmp \irqstat, #0
bne 1001f
ldr \irqnr, =NR_IRQS+1
b 1003f
1001: mov \irqnr, #0
1002: ands \tmp, \irqstat, #1
mov \irqstat, \irqstat, LSR #1
add \irqnr, \irqnr, #1
beq 1002b
sub \irqnr, \irqnr, #1
1003:
.endm

49
include/asm-arm/arch-aaec2000/hardware.h Normal file
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@ -0,0 +1,49 @@
/*
* linux/include/asm-arm/arch-aaec2000/hardware.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <linux/config.h>
/* The kernel is loaded at physical address 0xf8000000.
* We map the IO space a bit after
*/
#define PIO_APB_BASE 0x80000000
#define VIO_APB_BASE 0xf8000000
#define IO_APB_LENGTH 0x2000
#define PIO_AHB_BASE 0x80002000
#define VIO_AHB_BASE 0xf8002000
#define IO_AHB_LENGTH 0x2000
#define VIO_BASE VIO_APB_BASE
#define PIO_BASE PIO_APB_BASE
#define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE )
#define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE )
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* FIXME: Is it needed to optimize this a la pxa ?? */
#define __REG(x) (*((volatile u32 *)io_p2v(x)))
#define __PREG(x) (io_v2p((u32)&(x)))
#else /* __ASSEMBLY__ */
#define __REG(x) io_p2v(x)
#define __PREG(x) io_v2p(x)
#endif
#include "aaec2000.h"
#endif /* __ASM_ARCH_HARDWARE_H */

19
include/asm-arm/arch-aaec2000/io.h Normal file
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@ -0,0 +1,19 @@
/*
* linux/include/asm-arm/arch-aaec2000/io.h
*
* Copied from asm/arch/sa1100/io.h
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif

46
include/asm-arm/arch-aaec2000/irqs.h Normal file
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@ -0,0 +1,46 @@
/*
* linux/include/asm-arm/arch-aaec2000/irqs.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define INT_GPIOF0_FIQ 0 /* External GPIO Port F O Fast Interrupt Input */
#define INT_BL_FIQ 1 /* Battery Low Fast Interrupt */
#define INT_WE_FIQ 2 /* Watchdog Expired Fast Interrupt */
#define INT_MV_FIQ 3 /* Media Changed Interrupt */
#define INT_SC 4 /* Sound Codec Interrupt */
#define INT_GPIO1 5 /* GPIO Port F Configurable Int 1 */
#define INT_GPIO2 6 /* GPIO Port F Configurable Int 2 */
#define INT_GPIO3 7 /* GPIO Port F Configurable Int 3 */
#define INT_TMR1_OFL 8 /* Timer 1 Overflow Interrupt */
#define INT_TMR2_OFL 9 /* Timer 2 Overflow Interrupt */
#define INT_RTC_CM 10 /* RTC Compare Match Interrupt */
#define INT_TICK 11 /* 64Hz Tick Interrupt */
#define INT_UART1 12 /* UART1 Interrupt */
#define INT_UART2 13 /* UART2 & Modem State Changed Interrupt */
#define INT_LCD 14 /* LCD Interrupt */
#define INT_SSI 15 /* SSI End of Transfer Interrupt */
#define INT_UART3 16 /* UART3 Interrupt */
#define INT_SCI 17 /* SCI Interrupt */
#define INT_AAC 18 /* Advanced Audio Codec Interrupt */
#define INT_MMC 19 /* MMC Interrupt */
#define INT_USB 20 /* USB Interrupt */
#define INT_DMA 21 /* DMA Interrupt */
#define INT_TMR3_UOFL 22 /* Timer 3 Underflow Interrupt */
#define INT_GPIO4 23 /* GPIO Port F Configurable Int 4 */
#define INT_GPIO5 24 /* GPIO Port F Configurable Int 4 */
#define INT_GPIO6 25 /* GPIO Port F Configurable Int 4 */
#define INT_GPIO7 26 /* GPIO Port F Configurable Int 4 */
#define INT_BMI 27 /* BMI Interrupt */
#define NR_IRQS (INT_BMI + 1)
#endif /* __ASM_ARCH_IRQS_H */

73
include/asm-arm/arch-aaec2000/memory.h Normal file
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@ -0,0 +1,73 @@
/*
* linux/include/asm-arm/arch-aaec2000/memory.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <linux/config.h>
#define PHYS_OFFSET (0xf0000000UL)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#ifdef CONFIG_DISCONTIGMEM
/*
* The nodes are the followings:
*
* node 0: 0xf000.0000 - 0xf3ff.ffff
* node 1: 0xf400.0000 - 0xf7ff.ffff
* node 2: 0xf800.0000 - 0xfbff.ffff
* node 3: 0xfc00.0000 - 0xffff.ffff
*/
/*
* Given a kernel address, find the home node of the underlying memory.
*/
#define KVADDR_TO_NID(addr) \
(((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
/*
* Given a page frame number, convert it to a node id.
*/
#define PFN_TO_NID(pfn) \
(((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
/*
* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
* and return the mem_map of that node.
*/
#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
/*
* Given a page frame number, find the owning node of the memory
* and return the mem_map of that node.
*/
#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
/*
* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
* node's mem_map.
*/
#define LOCAL_MAP_NR(addr) \
(((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
#define NODE_MAX_MEM_SHIFT 26
#define NODE_MAX_MEM_SIZE (1 << NODE_MAX_MEM_SHIFT)
#else
#define PFN_TO_NID(addr) (0)
#endif /* CONFIG_DISCONTIGMEM */
#endif /* __ASM_ARCH_MEMORY_H */

15
include/asm-arm/arch-aaec2000/param.h Normal file
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@ -0,0 +1,15 @@
/*
* linux/include/asm-arm/arch-aaec2000/param.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PARAM_H
#define __ASM_ARCH_PARAM_H
#endif /* __ASM_ARCH_PARAM_H */

24
include/asm-arm/arch-aaec2000/system.h Normal file
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@ -0,0 +1,24 @@
/*
* linux/include/asm-arm/arch-aaed2000/system.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
cpu_reset(0);
}
#endif /* __ASM_ARCH_SYSTEM_H */

18
include/asm-arm/arch-aaec2000/timex.h Normal file
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@ -0,0 +1,18 @@
/*
* linux/include/asm-arm/arch-aaec2000/timex.h
*
* AAEC-2000 Architecture timex specification
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#define CLOCK_TICK_RATE 508000
#endif /* __ASM_ARCH_TIMEX_H */

47
include/asm-arm/arch-aaec2000/uncompress.h Normal file
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@ -0,0 +1,47 @@
/*
* linux/include/asm-arm/arch-aaec2000/uncompress.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include "hardware.h"
#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
static void putstr( const char *s )
{
unsigned long serial_port;
do {
serial_port = _UART3_BASE;
if (UART(UART_CR) & UART_CR_EN) break;
serial_port = _UART1_BASE;
if (UART(UART_CR) & UART_CR_EN) break;
serial_port = _UART2_BASE;
if (UART(UART_CR) & UART_CR_EN) break;
return;
} while (0);
for (; *s; s++) {
/* wait for space in the UART's transmitter */
while ((UART(UART_SR) & UART_SR_TxFF));
/* send the character out. */
UART(UART_DR) = *s;
/* if a LF, also do CR... */
if (*s == 10) {
while ((UART(UART_SR) & UART_SR_TxFF));
UART(UART_DR) = 13;
}
}
}
#define arch_decomp_setup()
#define arch_decomp_wdog()
#endif /* __ASM_ARCH_UNCOMPRESS_H */

16
include/asm-arm/arch-aaec2000/vmalloc.h Normal file
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@ -0,0 +1,16 @@
/*
* linux/include/asm-arm/arch-aaec2000/vmalloc.h
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#endif /* __ASM_ARCH_VMALLOC_H */

4
include/asm-arm/arch-integrator/platform.h
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@ -293,7 +293,11 @@
#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
#if defined(CONFIG_ARCH_INTEGRATOR_AP)
#define INTEGRATOR_GPIO_BASE 0x1B000000 /* GPIO */
#elif defined(CONFIG_ARCH_INTEGRATOR_CP)
#define INTEGRATOR_GPIO_BASE 0xC9000000 /* GPIO */
#endif
/* ------------------------------------------------------------------------
* KMI keyboard/mouse definitions

19
include/asm-arm/arch-integrator/smp.h Normal file
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@ -0,0 +1,19 @@
#ifndef ASMARM_ARCH_SMP_H
#define ASMARM_ARCH_SMP_H
#include <linux/config.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5" \
: "=r" (cpunum)); \
cpunum &= 0x0F; \
})
extern void secondary_scan_irqs(void);
#endif

31
include/asm-arm/arch-ixp2000/gpio.h
View file

@ -1,5 +1,5 @@
/*
* include/asm-arm/arch-ixp2000/ixp2000-gpio.h
* include/asm-arm/arch-ixp2000/gpio.h
*
* Copyright (C) 2002 Intel Corporation.
*
@ -16,26 +16,18 @@
* Use this instead of directly setting the GPIO registers.
* GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
*/
#ifndef _ASM_ARCH_IXP2000_GPIO_H_
#define _ASM_ARCH_IXP2000_GPIO_H_
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#ifndef __ASSEMBLY__
#define GPIO_OUT 0x0
#define GPIO_IN 0x80
#define GPIO_IN 0
#define GPIO_OUT 1
#define IXP2000_GPIO_LOW 0
#define IXP2000_GPIO_HIGH 1
#define GPIO_NO_EDGES 0
#define GPIO_FALLING_EDGE 1
#define GPIO_RISING_EDGE 2
#define GPIO_BOTH_EDGES 3
#define GPIO_LEVEL_LOW 4
#define GPIO_LEVEL_HIGH 8
extern void set_GPIO_IRQ_edge(int gpio_nr, int edge);
extern void set_GPIO_IRQ_level(int gpio_nr, int level);
extern void gpio_line_config(int line, int style);
extern void gpio_line_config(int line, int direction);
static inline int gpio_line_get(int line)
{
@ -45,11 +37,12 @@ static inline int gpio_line_get(int line)
static inline void gpio_line_set(int line, int value)
{
if (value == IXP2000_GPIO_HIGH) {
ixp_reg_write(IXP2000_GPIO_POSR, BIT(line));
} else if (value == IXP2000_GPIO_LOW)
ixp_reg_write(IXP2000_GPIO_POCR, BIT(line));
ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
} else if (value == IXP2000_GPIO_LOW) {
ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
}
}
#endif /* !__ASSEMBLY__ */
#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
#endif /* ASM_ARCH_IXP2000_GPIO_H_ */

112
include/asm-arm/arch-ixp2000/io.h
View file

@ -17,18 +17,23 @@
#define IO_SPACE_LIMIT 0xffffffff
#define __mem_pci(a) (a)
#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
/*
* The IXP2400 before revision B0 asserts byte lanes for PCI I/O
* The A? revisions of the IXP2000s assert byte lanes for PCI I/O
* transactions the other way round (MEM transactions don't have this
* issue), so we need to override the standard functions. B0 and later
* have a bit that can be set to 1 to get the 'proper' behavior, but
* since that isn't available on the A? revisions we just keep doing
* things manually.
* issue), so if we want to support those models, we need to override
* the standard I/O functions.
*
* B0 and later have a bit that can be set to 1 to get the proper
* behavior for I/O transactions, which then allows us to use the
* standard I/O functions. This is what we do if the user does not
* explicitly ask for support for pre-B0.
*/
#define alignb(addr) (void __iomem *)((unsigned long)addr ^ 3)
#define alignw(addr) (void __iomem *)((unsigned long)addr ^ 2)
#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3)
#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2)
#define outb(v,p) __raw_writeb((v),alignb(___io(p)))
#define outw(v,p) __raw_writew((v),alignw(___io(p)))
@ -48,6 +53,81 @@
#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
#define insl(p,d,l) __raw_readsl(___io(p),d,l)
#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
#define ioread8(p) \
({ \
unsigned int __v; \
\
if (__is_io_address(p)) { \
__v = __raw_readb(alignb(p)); \
} else { \
__v = __raw_readb(p); \
} \
\
__v; \
}) \
#define ioread16(p) \
({ \
unsigned int __v; \
\
if (__is_io_address(p)) { \
__v = __raw_readw(alignw(p)); \
} else { \
__v = le16_to_cpu(__raw_readw(p)); \
} \
\
__v; \
})
#define ioread32(p) \
({ \
unsigned int __v; \
\
if (__is_io_address(p)) { \
__v = __raw_readl(p); \
} else { \
__v = le32_to_cpu(__raw_readl(p)); \
} \
\
__v; \
})
#define iowrite8(v,p) \
({ \
if (__is_io_address(p)) { \
__raw_writeb((v), alignb(p)); \
} else { \
__raw_writeb((v), p); \
} \
})
#define iowrite16(v,p) \
({ \
if (__is_io_address(p)) { \
__raw_writew((v), alignw(p)); \
} else { \
__raw_writew(cpu_to_le16(v), p); \
} \
})
#define iowrite32(v,p) \
({ \
if (__is_io_address(p)) { \
__raw_writel((v), p); \
} else { \
__raw_writel(cpu_to_le32(v), p); \
} \
})
#define ioport_map(port, nr) ___io(port)
#define ioport_unmap(addr)
#else
#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
#endif
#ifdef CONFIG_ARCH_IXDP2X01
/*
@ -75,8 +155,8 @@ static inline void insw(u32 ptr, void *buf, int length)
* Is this cycle meant for the CS8900?
*/
if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
((port >= IXDP2X01_CS8900_VIRT_BASE) &&
(port <= IXDP2X01_CS8900_VIRT_END))) {
(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
u8 *buf8 = (u8*)buf;
register u32 tmp32;
@ -100,8 +180,8 @@ static inline void outsw(u32 ptr, void *buf, int length)
* Is this cycle meant for the CS8900?
*/
if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
((port >= IXDP2X01_CS8900_VIRT_BASE) &&
(port <= IXDP2X01_CS8900_VIRT_END))) {
(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
register u32 tmp32;
u8 *buf8 = (u8*)buf;
do {
@ -124,8 +204,8 @@ static inline u16 inw(u32 ptr)
* Is this cycle meant for the CS8900?
*/
if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
((port >= IXDP2X01_CS8900_VIRT_BASE) &&
(port <= IXDP2X01_CS8900_VIRT_END))) {
(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
return (u16)(*port);
}
@ -137,8 +217,8 @@ static inline void outw(u16 value, u32 ptr)
register volatile u32 *port = (volatile u32 *)ptr;
if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
((port >= IXDP2X01_CS8900_VIRT_BASE) &&
(port <= IXDP2X01_CS8900_VIRT_END))) {
(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
*port = value;
return;
}

3
include/asm-arm/arch-ixp2000/ixp2000-regs.h
View file

@ -241,7 +241,7 @@
#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
#define PCI_CONTROL_PNR (1 << 17) /* PCI Not Reset bit */
#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */
#define IXP2000_PCI_RST_REL (1 << 2)
#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
@ -363,6 +363,7 @@
#define IXP2000_MIN_REV_MASK 0x0000000F
#define IXP2000_PROD_ID_MASK 0xFFFFFFFF
#define IXP2000_PRODUCT_ID GLOBAL_REG(0x00)
#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04)
#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08)
#define IXP2000_RESET0 GLOBAL_REG(0x0c)

22
include/asm-arm/arch-ixp2000/platform.h
View file

@ -138,30 +138,10 @@ struct ixp2000_flash_data {
unsigned long (*bank_setup)(unsigned long);
};
/*
* GPIO helper functions
*/
#define GPIO_IN 0
#define GPIO_OUT 1
extern void gpio_line_config(int line, int style);
static inline int gpio_line_get(int line)
{
return (((*IXP2000_GPIO_PLR) >> line) & 1);
}
static inline void gpio_line_set(int line, int value)
{
if (value)
ixp2000_reg_write(IXP2000_GPIO_POSR, (1 << line));
else
ixp2000_reg_write(IXP2000_GPIO_POCR, (1 << line));
}
struct ixp2000_i2c_pins {
unsigned long sda_pin;
unsigned long scl_pin;
};
#endif /* !__ASSEMBLY__ */

1
include/asm-arm/arch-ixp4xx/debug-macro.S
View file

@ -14,6 +14,7 @@
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0xc8000000
orrne \rx, \rx, #0x00b00000
movne \rx, #0xff000000
add \rx,\rx,#3 @ Uart regs are at off set of 3 if
@ byte writes used - Big Endian.

10
include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
View file

@ -69,6 +69,16 @@
#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000)
#define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000)
/*
* Debug UART
*
* This is basically a remap of UART1 into a region that is section
* aligned so that it * can be used with the low-level debug code.
*/
#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000)
#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000)
#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
#define IXP4XX_EXP_CS0_OFFSET 0x00
#define IXP4XX_EXP_CS1_OFFSET 0x04
#define IXP4XX_EXP_CS2_OFFSET 0x08

76
include/asm-arm/arch-omap/tps65010.h
View file

@ -28,6 +28,66 @@
#ifndef __ASM_ARCH_TPS65010_H
#define __ASM_ARCH_TPS65010_H
/*
* ----------------------------------------------------------------------------
* Registers, all 8 bits
* ----------------------------------------------------------------------------
*/
#define TPS_CHGSTATUS 0x01
# define TPS_CHG_USB (1 << 7)
# define TPS_CHG_AC (1 << 6)
# define TPS_CHG_THERM (1 << 5)
# define TPS_CHG_TERM (1 << 4)
# define TPS_CHG_TAPER_TMO (1 << 3)
# define TPS_CHG_CHG_TMO (1 << 2)
# define TPS_CHG_PRECHG_TMO (1 << 1)
# define TPS_CHG_TEMP_ERR (1 << 0)
#define TPS_REGSTATUS 0x02
# define TPS_REG_ONOFF (1 << 7)
# define TPS_REG_COVER (1 << 6)
# define TPS_REG_UVLO (1 << 5)
# define TPS_REG_NO_CHG (1 << 4) /* tps65013 */
# define TPS_REG_PG_LD02 (1 << 3)
# define TPS_REG_PG_LD01 (1 << 2)
# define TPS_REG_PG_MAIN (1 << 1)
# define TPS_REG_PG_CORE (1 << 0)
#define TPS_MASK1 0x03
#define TPS_MASK2 0x04
#define TPS_ACKINT1 0x05
#define TPS_ACKINT2 0x06
#define TPS_CHGCONFIG 0x07
# define TPS_CHARGE_POR (1 << 7) /* 65010/65012 */
# define TPS65013_AUA (1 << 7) /* 65011/65013 */
# define TPS_CHARGE_RESET (1 << 6)
# define TPS_CHARGE_FAST (1 << 5)
# define TPS_CHARGE_CURRENT (3 << 3)
# define TPS_VBUS_500MA (1 << 2)
# define TPS_VBUS_CHARGING (1 << 1)
# define TPS_CHARGE_ENABLE (1 << 0)
#define TPS_LED1_ON 0x08
#define TPS_LED1_PER 0x09
#define TPS_LED2_ON 0x0a
#define TPS_LED2_PER 0x0b
#define TPS_VDCDC1 0x0c
# define TPS_ENABLE_LP (1 << 3)
#define TPS_VDCDC2 0x0d
#define TPS_VREGS1 0x0e
# define TPS_LDO2_ENABLE (1 << 7)
# define TPS_LDO2_OFF (1 << 6)
# define TPS_VLDO2_3_0V (3 << 4)
# define TPS_VLDO2_2_75V (2 << 4)
# define TPS_VLDO2_2_5V (1 << 4)
# define TPS_VLDO2_1_8V (0 << 4)
# define TPS_LDO1_ENABLE (1 << 3)
# define TPS_LDO1_OFF (1 << 2)
# define TPS_VLDO1_3_0V (3 << 0)
# define TPS_VLDO1_2_75V (2 << 0)
# define TPS_VLDO1_2_5V (1 << 0)
# define TPS_VLDO1_ADJ (0 << 0)
#define TPS_MASK3 0x0f
#define TPS_DEFGPIO 0x10
/*
* ----------------------------------------------------------------------------
* Macros used by exported functions
@ -71,10 +131,26 @@ extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
*/
extern int tps65010_set_led(unsigned led, unsigned mode);
/* tps65010_set_vib parameter:
* value: ON or OFF
*/
extern int tps65010_set_vib(unsigned value);
/* tps65010_set_low_pwr parameter:
* mode: ON or OFF
*/
extern int tps65010_set_low_pwr(unsigned mode);
/* tps65010_config_vregs1 parameter:
* value to be written to VREGS1 register
* Note: The complete register is written, set all bits you need
*/
extern int tps65010_config_vregs1(unsigned value);
/* tps65013_set_low_pwr parameter:
* mode: ON or OFF
*/
extern int tps65013_set_low_pwr(unsigned mode);
#endif /* __ASM_ARCH_TPS65010_H */

2
include/asm-arm/arch-pxa/pxa-regs.h
View file

@ -1296,6 +1296,7 @@
#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */
#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
/* GPIO alternate function mode & direction */
@ -1428,6 +1429,7 @@
#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_OUT)
#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)

27
include/asm-arm/arch-versatile/hardware.h
View file

@ -25,19 +25,26 @@
#include <asm/sizes.h>
#include <asm/arch/platform.h>
// FIXME = PCI settings need to be fixed!!!!!
/*
* Similar to above, but for PCI addresses (memory, IO, Config and the
* V3 chip itself). WARNING: this has to mirror definitions in platform.h
* PCI space virtual addresses
*/
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_CONFIG_VADDR 0xec000000
#define PCI_V3_VADDR 0xed000000
#define PCI_IO_VADDR 0xee000000
#define VERSATILE_PCI_VIRT_BASE 0xe8000000
#define VERSATILE_PCI_CFG_VIRT_BASE 0xe9000000
#define PCIO_BASE PCI_IO_VADDR
#define PCIMEM_BASE PCI_MEMORY_VADDR
#if 0
#define VERSATILE_PCI_VIRT_MEM_BASE0 0xf4000000
#define VERSATILE_PCI_VIRT_MEM_BASE1 0xf5000000
#define VERSATILE_PCI_VIRT_MEM_BASE2 0xf6000000
#define PCIO_BASE VERSATILE_PCI_VIRT_MEM_BASE0
#define PCIMEM_BASE VERSATILE_PCI_VIRT_MEM_BASE1
#endif
/* CIK guesswork */
#define PCIBIOS_MIN_IO 0x44000000
#define PCIBIOS_MIN_MEM 0x50000000
#define pcibios_assign_all_busses() 1
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)

2
include/asm-arm/arch-versatile/io.h
View file

@ -20,7 +20,7 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffff
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)

33
include/asm-arm/arch-versatile/platform.h
View file

@ -76,7 +76,7 @@
#define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38
#define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C
#define VERSATILE_SYS_RESETCTL_OFFSET 0x40
#define VERSATILE_SYS_PICCTL_OFFSET 0x44
#define VERSATILE_SYS_PCICTL_OFFSET 0x44
#define VERSATILE_SYS_MCI_OFFSET 0x48
#define VERSATILE_SYS_FLASH_OFFSET 0x4C
#define VERSATILE_SYS_CLCD_OFFSET 0x50
@ -114,7 +114,7 @@
#define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
#define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
#define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
#define VERSATILE_SYS_PICCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PICCTL_OFFSET)
#define VERSATILE_SYS_PCICTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
#define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
#define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
#define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
@ -225,7 +225,20 @@
#define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */
#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
#define VERSATILE_MBX_BASE 0x40000000 /* MBX */
/* PCI space */
#define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */
#define VERSATILE_PCI_CFG_BASE 0x42000000
#define VERSATILE_PCI_MEM_BASE0 0x44000000
#define VERSATILE_PCI_MEM_BASE1 0x50000000
#define VERSATILE_PCI_MEM_BASE2 0x60000000
/* Sizes of above maps */
#define VERSATILE_PCI_BASE_SIZE 0x01000000
#define VERSATILE_PCI_CFG_BASE_SIZE 0x02000000
#define VERSATILE_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
#define VERSATILE_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
#define VERSATILE_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
#define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
#define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */
@ -498,11 +511,17 @@
/*
* IB2 Versatile/AB expansion board definitions
*/
#define VERSATILE_IB2_CAMERA_BANK 0x24000000
#define VERSATILE_IB2_KBD_DATAREG 0x25000000
#define VERSATILE_IB2_IER 0x26000000 /* for VICINTSOURCE27 */
#define VERSATILE_IB2_CTRL 0x27000000
#define VERSATILE_IB2_STAT 0x27000004
#define VERSATILE_IB2_CAMERA_BANK VERSATILE_IB2_BASE
#define VERSATILE_IB2_KBD_DATAREG (VERSATILE_IB2_BASE + 0x01000000)
/* VICINTSOURCE27 */
#define VERSATILE_IB2_INT_BASE (VERSATILE_IB2_BASE + 0x02000000)
#define VERSATILE_IB2_IER (VERSATILE_IB2_INT_BASE + 0)
#define VERSATILE_IB2_ISR (VERSATILE_IB2_INT_BASE + 4)
#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
#define VERSATILE_IB2_CTRL (VERSATILE_IB2_CTL_BASE + 0)
#define VERSATILE_IB2_STAT (VERSATILE_IB2_CTL_BASE + 4)
#endif
#endif

3
include/asm-arm/cacheflush.h
View file

@ -16,6 +16,9 @@
#include <asm/mman.h>
#include <asm/glue.h>
#include <asm/shmparam.h>
#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
/*
* Cache Model

4
include/asm-arm/elf.h
View file

@ -38,9 +38,9 @@ typedef struct user_fp elf_fpregset_t;
*/
#define ELF_CLASS ELFCLASS32
#ifdef __ARMEB__
#define ELF_DATA ELFDATA2MSB;
#define ELF_DATA ELFDATA2MSB
#else
#define ELF_DATA ELFDATA2LSB;
#define ELF_DATA ELFDATA2LSB
#endif
#define ELF_ARCH EM_ARM

29
include/asm-arm/io.h
View file

@ -272,6 +272,35 @@ extern void __iounmap(void __iomem *addr);
#define iounmap(cookie) __arch_iounmap(cookie)
#endif
/*
* io{read,write}{8,16,32} macros
*/
#ifndef ioread8
#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; })
#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
#define iowrite8(v,p) __raw_writeb(v, p)
#define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p)
#define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p)
#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
extern void ioport_unmap(void __iomem *addr);
#endif
struct pci_dev;
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
/*
* can the hardware map this into one segment or not, given no other
* constraints.

21
include/asm-arm/mach/time.h
View file

@ -39,8 +39,29 @@ struct sys_timer {
void (*suspend)(void);
void (*resume)(void);
unsigned long (*offset)(void);
#ifdef CONFIG_NO_IDLE_HZ
struct dyn_tick_timer *dyn_tick;
#endif
};
#ifdef CONFIG_NO_IDLE_HZ
#define DYN_TICK_SKIPPING (1 << 2)
#define DYN_TICK_ENABLED (1 << 1)
#define DYN_TICK_SUITABLE (1 << 0)
struct dyn_tick_timer {
unsigned int state; /* Current state */
int (*enable)(void); /* Enables dynamic tick */
int (*disable)(void); /* Disables dynamic tick */
void (*reprogram)(unsigned long); /* Reprograms the timer */
int (*handler)(int, void *, struct pt_regs *);
};
void timer_dyn_reprogram(void);
#endif
extern struct sys_timer *system_timer;
extern void timer_tick(struct pt_regs *);

24
include/asm-arm/pgalloc.h
View file

@ -89,6 +89,13 @@ static inline void pte_free(struct page *pte)
__free_page(pte);
}
static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval)
{
pmdp[0] = __pmd(pmdval);
pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
flush_pmd_entry(pmdp);
}
/*
* Populate the pmdp entry with a pointer to the pte. This pmd is part
* of the mm address space.
@ -99,32 +106,19 @@ static inline void
pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
{
unsigned long pte_ptr = (unsigned long)ptep;
unsigned long pmdval;
BUG_ON(mm != &init_mm);
/*
* The pmd must be loaded with the physical
* address of the PTE table
*/
pte_ptr -= PTRS_PER_PTE * sizeof(void *);
pmdval = __pa(pte_ptr) | _PAGE_KERNEL_TABLE;
pmdp[0] = __pmd(pmdval);
pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
flush_pmd_entry(pmdp);
__pmd_populate(pmdp, __pa(pte_ptr) | _PAGE_KERNEL_TABLE);
}
static inline void
pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
{
unsigned long pmdval;
BUG_ON(mm == &init_mm);
pmdval = page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE;
pmdp[0] = __pmd(pmdval);
pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
flush_pmd_entry(pmdp);
__pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE);
}
#endif

1
include/asm-arm/signal.h
View file

@ -114,6 +114,7 @@ typedef unsigned long sigset_t;
#define SIGSTKSZ 8192
#ifdef __KERNEL__
#define SA_TIMER 0x40000000
#define SA_IRQNOMASK 0x08000000
#endif

16
include/asm-arm/smp.h
View file

@ -21,7 +21,7 @@
# error "<asm-arm/smp.h> included in non-SMP build"
#endif
#define smp_processor_id() (current_thread_info()->cpu)
#define raw_smp_processor_id() (current_thread_info()->cpu)
extern cpumask_t cpu_present_mask;
#define cpu_possible_map cpu_present_mask
@ -55,4 +55,18 @@ extern void smp_cross_call(cpumask_t callmap);
*/
extern int boot_secondary(unsigned int cpu, struct task_struct *);
/*
* Perform platform specific initialisation of the specified CPU.
*/
extern void platform_secondary_init(unsigned int cpu);
/*
* Initial data for bringing up a secondary CPU.
*/
struct secondary_data {
unsigned long pgdir;
void *stack;
};
extern struct secondary_data secondary_data;
#endif /* ifndef __ASM_ARM_SMP_H */

33
include/asm-arm/system.h
View file

@ -104,6 +104,7 @@ extern void show_pte(struct mm_struct *mm, unsigned long addr);
extern void __show_regs(struct pt_regs *);
extern int cpu_architecture(void);
extern void cpu_init(void);
#define set_cr(x) \
__asm__ __volatile__( \
@ -144,34 +145,12 @@ extern unsigned int user_debug;
#define set_wmb(var, value) do { var = value; wmb(); } while (0)
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
#ifdef CONFIG_SMP
/*
* Define our own context switch locking. This allows us to enable
* interrupts over the context switch, otherwise we end up with high
* interrupt latency. The real problem area is switch_mm() which may
* do a full cache flush.
* switch_mm() may do a full cache flush over the context switch,
* so enable interrupts over the context switch to avoid high
* latency.
*/
#define prepare_arch_switch(rq,next) \
do { \
spin_lock(&(next)->switch_lock); \
spin_unlock_irq(&(rq)->lock); \
} while (0)
#define finish_arch_switch(rq,prev) \
spin_unlock(&(prev)->switch_lock)
#define task_running(rq,p) \
((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
#else
/*
* Our UP-case is more simple, but we assume knowledge of how
* spin_unlock_irq() and friends are implemented. This avoids
* us needlessly decrementing and incrementing the preempt count.
*/
#define prepare_arch_switch(rq,next) local_irq_enable()
#define finish_arch_switch(rq,prev) spin_unlock(&(rq)->lock)
#define task_running(rq,p) ((rq)->curr == (p))
#endif
#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
/*
* switch_to(prev, next) should switch from task `prev' to `next'
@ -307,7 +286,7 @@ do { \
({ \
unsigned long flags; \
local_save_flags(flags); \
flags & PSR_I_BIT; \
(int)(flags & PSR_I_BIT); \
})
#ifdef CONFIG_SMP

2
include/asm-arm/thread_info.h
View file

@ -49,7 +49,7 @@ struct cpu_context_save {
*/
struct thread_info {
unsigned long flags; /* low level flags */
__s32 preempt_count; /* 0 => preemptable, <0 => bug */
int preempt_count; /* 0 => preemptable, <0 => bug */
mm_segment_t addr_limit; /* address limit */
struct task_struct *task; /* main task structure */
struct exec_domain *exec_domain; /* execution domain */

2
include/asm-arm26/elf.h
View file

@ -36,7 +36,7 @@ typedef struct { void *null; } elf_fpregset_t;
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2LSB;
#define ELF_DATA ELFDATA2LSB
#define ELF_ARCH EM_ARM
#define USE_ELF_CORE_DUMP

3
include/asm-arm26/signal.h
View file

@ -166,9 +166,6 @@ typedef struct sigaltstack {
#include <asm/sigcontext.h>
#define sigmask(sig) (1UL << ((sig) - 1))
//FIXME!!!
//#define HAVE_ARCH_GET_SIGNAL_TO_DELIVER
#endif

2
include/asm-arm26/thread_info.h
View file

@ -44,7 +44,7 @@ struct cpu_context_save {
*/
struct thread_info {
unsigned long flags; /* low level flags */
__s32 preempt_count; /* 0 => preemptable, <0 => bug */
int preempt_count; /* 0 => preemptable, <0 => bug */
mm_segment_t addr_limit; /* address limit */
struct task_struct *task; /* main task structure */
struct exec_domain *exec_domain; /* execution domain */

2
include/asm-cris/thread_info.h
View file

@ -31,7 +31,7 @@ struct thread_info {
struct exec_domain *exec_domain; /* execution domain */
unsigned long flags; /* low level flags */
__u32 cpu; /* current CPU */
__s32 preempt_count; /* 0 => preemptable, <0 => BUG */
int preempt_count; /* 0 => preemptable, <0 => BUG */
mm_segment_t addr_limit; /* thread address space:
0-0xBFFFFFFF for user-thead

2
include/asm-frv/thread_info.h
View file

@ -33,7 +33,7 @@ struct thread_info {
unsigned long flags; /* low level flags */
unsigned long status; /* thread-synchronous flags */
__u32 cpu; /* current CPU */
__s32 preempt_count; /* 0 => preemptable, <0 => BUG */
int preempt_count; /* 0 => preemptable, <0 => BUG */
mm_segment_t addr_limit; /* thread address space:
0-0xBFFFFFFF for user-thead

2
include/asm-generic/percpu.h
View file

@ -29,7 +29,7 @@ do { \
#define DEFINE_PER_CPU(type, name) \
__typeof__(type) per_cpu__##name
#define per_cpu(var, cpu) (*((void)cpu, &per_cpu__##var))
#define per_cpu(var, cpu) (*((void)(cpu), &per_cpu__##var))
#define __get_cpu_var(var) per_cpu__##var
#endif /* SMP */

3
include/asm-generic/pgtable.h
View file

@ -125,6 +125,9 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres
#ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
#define page_test_and_clear_dirty(page) (0)
#define pte_maybe_dirty(pte) pte_dirty(pte)
#else
#define pte_maybe_dirty(pte) (1)
#endif
#ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG

9
include/asm-generic/topology.h
View file

@ -41,8 +41,15 @@
#ifndef node_to_first_cpu
#define node_to_first_cpu(node) (0)
#endif
#ifndef pcibus_to_node
#define pcibus_to_node(node) (-1)
#endif
#ifndef pcibus_to_cpumask
#define pcibus_to_cpumask(bus) (cpu_online_map)
#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
CPU_MASK_ALL : \
node_to_cpumask(pcibus_to_node(bus)) \
)
#endif
#endif /* _ASM_GENERIC_TOPOLOGY_H */

2
include/asm-generic/vmlinux.lds.h
View file

@ -73,7 +73,7 @@
}
#define SECURITY_INIT \
.security_initcall.init : { \
.security_initcall.init : AT(ADDR(.security_initcall.init) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__security_initcall_start) = .; \
*(.security_initcall.init) \
VMLINUX_SYMBOL(__security_initcall_end) = .; \

6
include/asm-h8300/kmap_types.h
View file

@ -1,5 +1,5 @@
#ifndef _ASM_KMAP_TYPES_H
#define _ASM_KMAP_TYPES_H
#ifndef _ASM_H8300_KMAP_TYPES_H
#define _ASM_H8300_KMAP_TYPES_H
enum km_type {
KM_BOUNCE_READ,
@ -13,6 +13,8 @@ enum km_type {
KM_PTE1,
KM_IRQ0,
KM_IRQ1,
KM_SOFTIRQ0,
KM_SOFTIRQ1,
KM_TYPE_NR
};

3
include/asm-h8300/mman.h
View file

@ -4,6 +4,7 @@
#define PROT_READ 0x1 /* page can be read */
#define PROT_WRITE 0x2 /* page can be written */
#define PROT_EXEC 0x4 /* page can be executed */
#define PROT_SEM 0x8 /* page may be used for atomic ops */
#define PROT_NONE 0x0 /* page can not be accessed */
#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
@ -19,6 +20,8 @@
#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
#define MAP_LOCKED 0x2000 /* pages are locked */
#define MAP_NORESERVE 0x4000 /* don't check for reservations */
#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
#define MAP_NONBLOCK 0x10000 /* do not block on IO */
#define MS_ASYNC 1 /* sync memory asynchronously */
#define MS_INVALIDATE 2 /* invalidate the caches */

2
include/asm-h8300/thread_info.h
View file

@ -23,7 +23,7 @@ struct thread_info {
struct exec_domain *exec_domain; /* execution domain */
unsigned long flags; /* low level flags */
int cpu; /* cpu we're on */
int preempt_count; /* 0 => preemptable, <0 => BUG*/
int preempt_count; /* 0 => preemptable, <0 => BUG */
struct restart_block restart_block;
};

10
include/asm-i386/agp.h
View file

@ -21,4 +21,14 @@ int unmap_page_from_agp(struct page *page);
worth it. Would need a page for it. */
#define flush_agp_cache() asm volatile("wbinvd":::"memory")
/* Convert a physical address to an address suitable for the GART. */
#define phys_to_gart(x) (x)
#define gart_to_phys(x) (x)
/* GATT allocation. Returns/accepts GATT kernel virtual address. */
#define alloc_gatt_pages(order) \
((char *)__get_free_pages(GFP_KERNEL, (order)))
#define free_gatt_pages(table, order) \
free_pages((unsigned long)(table), (order))
#endif

15
include/asm-i386/apic.h
View file

@ -5,6 +5,7 @@
#include <linux/pm.h>
#include <asm/fixmap.h>
#include <asm/apicdef.h>
#include <asm/processor.h>
#include <asm/system.h>
#define Dprintk(x...)
@ -16,8 +17,20 @@
#define APIC_VERBOSE 1
#define APIC_DEBUG 2
extern int enable_local_apic;
extern int apic_verbosity;
static inline void lapic_disable(void)
{
enable_local_apic = -1;
clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
}
static inline void lapic_enable(void)
{
enable_local_apic = 1;
}
/*
* Define the default level of output to be very little
* This can be turned up by using apic=verbose for more
@ -87,7 +100,7 @@ extern void (*wait_timer_tick)(void);
extern int get_maxlvt(void);
extern void clear_local_APIC(void);
extern void connect_bsp_APIC (void);
extern void disconnect_bsp_APIC (void);
extern void disconnect_bsp_APIC (int virt_wire_setup);
extern void disable_local_APIC (void);
extern void lapic_shutdown (void);
extern int verify_local_APIC (void);

3
include/asm-i386/apicdef.h
View file

@ -86,11 +86,12 @@
#define APIC_LVT_REMOTE_IRR (1<<14)
#define APIC_INPUT_POLARITY (1<<13)
#define APIC_SEND_PENDING (1<<12)
#define APIC_MODE_MASK 0x700
#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
#define APIC_MODE_FIXED 0x0
#define APIC_MODE_NMI 0x4
#define APIC_MODE_EXINT 0x7
#define APIC_MODE_EXTINT 0x7
#define APIC_LVT1 0x360
#define APIC_LVTERR 0x370
#define APIC_TMICT 0x380

2
include/asm-i386/checksum.h
View file

@ -3,6 +3,8 @@
#include <linux/in6.h>
#include <asm/uaccess.h>
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)

2
include/asm-i386/cpu.h
View file

@ -5,6 +5,7 @@
#include <linux/cpu.h>
#include <linux/topology.h>
#include <linux/nodemask.h>
#include <linux/percpu.h>
#include <asm/node.h>
@ -16,4 +17,5 @@ extern int arch_register_cpu(int num);
extern void arch_unregister_cpu(int);
#endif
DECLARE_PER_CPU(int, cpu_state);
#endif /* _ASM_I386_CPU_H_ */

1
include/asm-i386/genapic.h
View file

@ -78,7 +78,6 @@ struct genapic {
.int_delivery_mode = INT_DELIVERY_MODE, \
.int_dest_mode = INT_DEST_MODE, \
.no_balance_irq = NO_BALANCE_IRQ, \
.no_ioapic_check = NO_IOAPIC_CHECK, \
.ESR_DISABLE = esr_disable, \
.apic_destination_logical = APIC_DEST_LOGICAL, \
APICFUNC(apic_id_registered), \

1
include/asm-i386/highmem.h
View file

@ -70,6 +70,7 @@ void *kmap(struct page *page);
void kunmap(struct page *page);
void *kmap_atomic(struct page *page, enum km_type type);
void kunmap_atomic(void *kvaddr, enum km_type type);
void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
struct page *kmap_atomic_to_page(void *ptr);
#define flush_cache_kmaps() do { } while (0)

6
include/asm-i386/irq.h
View file

@ -29,13 +29,19 @@ extern void release_vm86_irqs(struct task_struct *);
#ifdef CONFIG_4KSTACKS
extern void irq_ctx_init(int cpu);
extern void irq_ctx_exit(int cpu);
# define __ARCH_HAS_DO_SOFTIRQ
#else
# define irq_ctx_init(cpu) do { } while (0)
# define irq_ctx_exit(cpu) do { } while (0)
#endif
#ifdef CONFIG_IRQBALANCE
extern int irqbalance_disable(char *str);
#endif
#ifdef CONFIG_HOTPLUG_CPU
extern void fixup_irqs(cpumask_t map);
#endif
#endif /* _ASM_IRQ_H */

2
include/asm-i386/kdebug.h
View file

@ -18,7 +18,7 @@ struct die_args {
};
/* Note - you should never unregister because that can race with NMIs.
If you really want to do it first unregister - then synchronize_kernel - then free.
If you really want to do it first unregister - then synchronize_sched - then free.
*/
int register_die_notifier(struct notifier_block *nb);
extern struct notifier_block *i386die_chain;

33
include/asm-i386/kexec.h Normal file
View file

@ -0,0 +1,33 @@
#ifndef _I386_KEXEC_H
#define _I386_KEXEC_H
#include <asm/fixmap.h>
/*
* KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
* I.e. Maximum page that is mapped directly into kernel memory,
* and kmap is not required.
*
* Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
* calculation for the amount of memory directly mappable into the
* kernel memory space.
*/
/* Maximum physical address we can use pages from */
#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
/* Maximum address we can reach in physical address mode */
#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
/* Maximum address we can use for the control code buffer */
#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
#define KEXEC_CONTROL_CODE_SIZE 4096
/* The native architecture */
#define KEXEC_ARCH KEXEC_ARCH_386
#define MAX_NOTE_BYTES 1024
typedef u32 note_buf_t[MAX_NOTE_BYTES/4];
extern note_buf_t crash_notes[];
#endif /* _I386_KEXEC_H */

3
include/asm-i386/kprobes.h
View file

@ -39,6 +39,9 @@ typedef u8 kprobe_opcode_t;
: (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)pentry
#define ARCH_SUPPORTS_KRETPROBES
void kretprobe_trampoline(void);
/* Architecture specific copy of original instruction*/
struct arch_specific_insn {

4
include/asm-i386/linkage.h
View file

@ -5,9 +5,7 @@
#define FASTCALL(x) x __attribute__((regparm(3)))
#define fastcall __attribute__((regparm(3)))
#ifdef CONFIG_REGPARM
# define prevent_tail_call(ret) __asm__ ("" : "=r" (ret) : "0" (ret))
#endif
#define prevent_tail_call(ret) __asm__ ("" : "=r" (ret) : "0" (ret))
#ifdef CONFIG_X86_ALIGNMENT_16
#define __ALIGN .align 16,0x90

2
include/asm-i386/mach-bigsmp/mach_apic.h
View file

@ -14,8 +14,6 @@
#define NO_BALANCE_IRQ (1)
#define esr_disable (1)
#define NO_IOAPIC_CHECK (0)
static inline int apic_id_registered(void)
{
return (1);

2
include/asm-i386/mach-default/mach_apic.h
View file

@ -19,8 +19,6 @@ static inline cpumask_t target_cpus(void)
#define NO_BALANCE_IRQ (0)
#define esr_disable (0)
#define NO_IOAPIC_CHECK (0)
#define INT_DELIVERY_MODE dest_LowestPrio
#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */

27
include/asm-i386/mach-default/mach_ipi.h
View file

@ -4,11 +4,34 @@
void send_IPI_mask_bitmask(cpumask_t mask, int vector);
void __send_IPI_shortcut(unsigned int shortcut, int vector);
extern int no_broadcast;
static inline void send_IPI_mask(cpumask_t mask, int vector)
{
send_IPI_mask_bitmask(mask, vector);
}
static inline void __local_send_IPI_allbutself(int vector)
{
if (no_broadcast) {
cpumask_t mask = cpu_online_map;
int this_cpu = get_cpu();
cpu_clear(this_cpu, mask);
send_IPI_mask(mask, vector);
put_cpu();
} else
__send_IPI_shortcut(APIC_DEST_ALLBUT, vector);
}
static inline void __local_send_IPI_all(int vector)
{
if (no_broadcast)
send_IPI_mask(cpu_online_map, vector);
else
__send_IPI_shortcut(APIC_DEST_ALLINC, vector);
}
static inline void send_IPI_allbutself(int vector)
{
/*
@ -18,13 +41,13 @@ static inline void send_IPI_allbutself(int vector)
if (!(num_online_cpus() > 1))
return;
__send_IPI_shortcut(APIC_DEST_ALLBUT, vector);
__local_send_IPI_allbutself(vector);
return;
}
static inline void send_IPI_all(int vector)
{
__send_IPI_shortcut(APIC_DEST_ALLINC, vector);
__local_send_IPI_all(vector);
}
#endif /* __ASM_MACH_IPI_H */

2
include/asm-i386/mach-es7000/mach_apic.h
View file

@ -38,8 +38,6 @@ static inline cpumask_t target_cpus(void)
#define WAKE_SECONDARY_VIA_INIT
#endif
#define NO_IOAPIC_CHECK (1)
static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
{
return 0;

1
include/asm-i386/mach-generic/mach_apic.h
View file

@ -5,7 +5,6 @@
#define esr_disable (genapic->ESR_DISABLE)
#define NO_BALANCE_IRQ (genapic->no_balance_irq)
#define NO_IOAPIC_CHECK (genapic->no_ioapic_check)
#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
#define INT_DEST_MODE (genapic->int_dest_mode)
#undef APIC_DEST_LOGICAL

2
include/asm-i386/mach-numaq/mach_apic.h
View file

@ -17,8 +17,6 @@ static inline cpumask_t target_cpus(void)
#define NO_BALANCE_IRQ (1)
#define esr_disable (1)
#define NO_IOAPIC_CHECK (0)
#define INT_DELIVERY_MODE dest_LowestPrio
#define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */

2
include/asm-i386/mach-numaq/mach_ipi.h
View file

@ -1,7 +1,7 @@
#ifndef __ASM_MACH_IPI_H
#define __ASM_MACH_IPI_H
inline void send_IPI_mask_sequence(cpumask_t, int vector);
void send_IPI_mask_sequence(cpumask_t, int vector);
static inline void send_IPI_mask(cpumask_t mask, int vector)
{

2
include/asm-i386/mach-summit/mach_apic.h
View file

@ -7,8 +7,6 @@
#define esr_disable (1)
#define NO_BALANCE_IRQ (0)
#define NO_IOAPIC_CHECK (1) /* Don't check I/O APIC ID for xAPIC */
/* In clustered mode, the high nibble of APIC ID is a cluster number.
* The low nibble is a 4-bit bitmap. */
#define XAPIC_DEST_CPUS_SHIFT 4

2
include/asm-i386/mach-visws/mach_apic.h
View file

@ -9,8 +9,6 @@
#define no_balance_irq (0)
#define esr_disable (0)
#define NO_IOAPIC_CHECK (0)
#define INT_DELIVERY_MODE dest_LowestPrio
#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */

99
include/asm-i386/mmzone.h
View file

@ -8,7 +8,9 @@
#include <asm/smp.h>
#ifdef CONFIG_DISCONTIGMEM
#if CONFIG_NUMA
extern struct pglist_data *node_data[];
#define NODE_DATA(nid) (node_data[nid])
#ifdef CONFIG_NUMA
#ifdef CONFIG_X86_NUMAQ
@ -21,8 +23,28 @@
#define get_zholes_size(n) (0)
#endif /* CONFIG_NUMA */
extern struct pglist_data *node_data[];
#define NODE_DATA(nid) (node_data[nid])
extern int get_memcfg_numa_flat(void );
/*
* This allows any one NUMA architecture to be compiled
* for, and still fall back to the flat function if it
* fails.
*/
static inline void get_memcfg_numa(void)
{
#ifdef CONFIG_X86_NUMAQ
if (get_memcfg_numaq())
return;
#elif CONFIG_ACPI_SRAT
if (get_memcfg_from_srat())
return;
#endif
get_memcfg_numa_flat();
}
#endif /* CONFIG_NUMA */
#ifdef CONFIG_DISCONTIGMEM
/*
* generic node memory support, the following assumptions apply:
@ -48,26 +70,6 @@ static inline int pfn_to_nid(unsigned long pfn)
#endif
}
/*
* Following are macros that are specific to this numa platform.
*/
#define reserve_bootmem(addr, size) \
reserve_bootmem_node(NODE_DATA(0), (addr), (size))
#define alloc_bootmem(x) \
__alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
#define alloc_bootmem_low(x) \
__alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, 0)
#define alloc_bootmem_pages(x) \
__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
#define alloc_bootmem_low_pages(x) \
__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
#define alloc_bootmem_node(ignore, x) \
__alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
#define alloc_bootmem_pages_node(ignore, x) \
__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
#define alloc_bootmem_low_pages_node(ignore, x) \
__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
#define node_localnr(pfn, nid) ((pfn) - node_data[nid]->node_start_pfn)
/*
@ -79,7 +81,6 @@ static inline int pfn_to_nid(unsigned long pfn)
*/
#define kvaddr_to_nid(kaddr) pfn_to_nid(__pa(kaddr) >> PAGE_SHIFT)
#define node_mem_map(nid) (NODE_DATA(nid)->node_mem_map)
#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
#define node_end_pfn(nid) \
({ \
@ -100,7 +101,7 @@ static inline int pfn_to_nid(unsigned long pfn)
({ \
unsigned long __pfn = pfn; \
int __node = pfn_to_nid(__pfn); \
&node_mem_map(__node)[node_localnr(__pfn,__node)]; \
&NODE_DATA(__node)->node_mem_map[node_localnr(__pfn,__node)]; \
})
#define page_to_pfn(pg) \
@ -122,26 +123,34 @@ static inline int pfn_valid(int pfn)
return (pfn < node_end_pfn(nid));
return 0;
}
#endif
extern int get_memcfg_numa_flat(void );
/*
* This allows any one NUMA architecture to be compiled
* for, and still fall back to the flat function if it
* fails.
*/
static inline void get_memcfg_numa(void)
{
#ifdef CONFIG_X86_NUMAQ
if (get_memcfg_numaq())
return;
#elif CONFIG_ACPI_SRAT
if (get_memcfg_from_srat())
return;
#endif
get_memcfg_numa_flat();
}
#endif /* CONFIG_X86_NUMAQ */
#endif /* CONFIG_DISCONTIGMEM */
#ifdef CONFIG_NEED_MULTIPLE_NODES
/*
* Following are macros that are specific to this numa platform.
*/
#define reserve_bootmem(addr, size) \
reserve_bootmem_node(NODE_DATA(0), (addr), (size))
#define alloc_bootmem(x) \
__alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
#define alloc_bootmem_low(x) \
__alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, 0)
#define alloc_bootmem_pages(x) \
__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
#define alloc_bootmem_low_pages(x) \
__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
#define alloc_bootmem_node(ignore, x) \
__alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
#define alloc_bootmem_pages_node(ignore, x) \
__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
#define alloc_bootmem_low_pages_node(ignore, x) \
__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
#endif /* CONFIG_NEED_MULTIPLE_NODES */
extern int early_pfn_to_nid(unsigned long pfn);
#endif /* _ASM_MMZONE_H_ */

10
include/asm-i386/page.h
View file

@ -68,6 +68,7 @@ typedef struct { unsigned long pgprot; } pgprot_t;
#define HPAGE_MASK (~(HPAGE_SIZE - 1))
#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
#define ARCH_HAS_HUGETLB_CLEAN_STALE_PGTABLE
#endif
#define pgd_val(x) ((x).pgd)
@ -119,13 +120,18 @@ static __inline__ int get_order(unsigned long size)
extern int sysctl_legacy_va_layout;
extern int page_is_ram(unsigned long pagenr);
#endif /* __ASSEMBLY__ */
#ifdef __ASSEMBLY__
#define __PAGE_OFFSET (0xC0000000)
#define __PHYSICAL_START CONFIG_PHYSICAL_START
#else
#define __PAGE_OFFSET (0xC0000000UL)
#define __PHYSICAL_START ((unsigned long)CONFIG_PHYSICAL_START)
#endif
#define __KERNEL_START (__PAGE_OFFSET + __PHYSICAL_START)
#define PAGE_OFFSET ((unsigned long)__PAGE_OFFSET)
@ -134,11 +140,11 @@ extern int sysctl_legacy_va_layout;
#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET)
#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET))
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#ifndef CONFIG_DISCONTIGMEM
#ifdef CONFIG_FLATMEM
#define pfn_to_page(pfn) (mem_map + (pfn))
#define page_to_pfn(page) ((unsigned long)((page) - mem_map))
#define pfn_valid(pfn) ((pfn) < max_mapnr)
#endif /* !CONFIG_DISCONTIGMEM */
#endif /* CONFIG_FLATMEM */
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)

4
include/asm-i386/param.h
View file

@ -1,8 +1,10 @@
#include <linux/config.h>
#ifndef _ASMi386_PARAM_H
#define _ASMi386_PARAM_H
#ifdef __KERNEL__
# define HZ 1000 /* Internal kernel timer frequency */
# define HZ CONFIG_HZ /* Internal kernel timer frequency */
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
#endif

6
include/asm-i386/pgtable.h
View file

@ -236,6 +236,7 @@ static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return
static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; }
static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; }
static inline pte_t pte_mkhuge(pte_t pte) { (pte).pte_low |= _PAGE_PRESENT | _PAGE_PSE; return pte; }
#ifdef CONFIG_X86_PAE
# include <asm/pgtable-3level.h>
@ -275,7 +276,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
*/
#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
#define mk_pte_huge(entry) ((entry).pte_low |= _PAGE_PRESENT | _PAGE_PSE)
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
@ -398,9 +398,9 @@ extern void noexec_setup(const char *str);
#endif /* !__ASSEMBLY__ */
#ifndef CONFIG_DISCONTIGMEM
#ifdef CONFIG_FLATMEM
#define kern_addr_valid(addr) (1)
#endif /* !CONFIG_DISCONTIGMEM */
#endif /* CONFIG_FLATMEM */
#define io_remap_page_range(vma, vaddr, paddr, size, prot) \
remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)

16
include/asm-i386/processor.h
View file

@ -501,12 +501,16 @@ static inline void load_esp0(struct tss_struct *tss, struct thread_struct *threa
} while (0)
/*
* This special macro can be used to load a debugging register
* These special macros can be used to get or set a debugging register
*/
#define loaddebug(thread,register) \
__asm__("movl %0,%%db" #register \
: /* no output */ \
:"r" ((thread)->debugreg[register]))
#define get_debugreg(var, register) \
__asm__("movl %%db" #register ", %0" \
:"=r" (var))
#define set_debugreg(value, register) \
__asm__("movl %0,%%db" #register \
: /* no output */ \
:"r" (value))
/* Forward declaration, a strange C thing */
struct task_struct;
@ -687,5 +691,7 @@ extern void select_idle_routine(const struct cpuinfo_x86 *c);
#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
extern unsigned long boot_option_idle_override;
extern void enable_sep_cpu(void);
extern int sysenter_setup(void);
#endif /* __ASM_I386_PROCESSOR_H */

3
include/asm-i386/ptrace.h
View file

@ -57,7 +57,8 @@ struct pt_regs {
#ifdef __KERNEL__
struct task_struct;
extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, int error_code);
#define user_mode(regs) ((VM_MASK & (regs)->eflags) || (3 & (regs)->xcs))
#define user_mode(regs) (3 & (regs)->xcs)
#define user_mode_vm(regs) ((VM_MASK & (regs)->eflags) || user_mode(regs))
#define instruction_pointer(regs) ((regs)->eip)
#if defined(CONFIG_SMP) && defined(CONFIG_FRAME_POINTER)
extern unsigned long profile_pc(struct pt_regs *regs);

12
include/asm-i386/smp.h
View file

@ -42,16 +42,23 @@ extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
extern void smp_invalidate_rcv(void); /* Process an NMI */
extern void (*mtrr_hook) (void);
extern void zap_low_mappings (void);
extern void lock_ipi_call_lock(void);
extern void unlock_ipi_call_lock(void);
#define MAX_APICID 256
extern u8 x86_cpu_to_apicid[];
#ifdef CONFIG_HOTPLUG_CPU
extern void cpu_exit_clear(void);
extern void cpu_uninit(void);
#endif
/*
* This function is needed by all SMP systems. It must _always_ be valid
* from the initial startup. We map APIC_BASE very early in page_setup(),
* so this is correct in the x86 case.
*/
#define __smp_processor_id() (current_thread_info()->cpu)
#define raw_smp_processor_id() (current_thread_info()->cpu)
extern cpumask_t cpu_callout_map;
extern cpumask_t cpu_callin_map;
@ -83,6 +90,9 @@ static __inline int logical_smp_processor_id(void)
}
#endif
extern int __cpu_disable(void);
extern void __cpu_die(unsigned int cpu);
#endif /* !__ASSEMBLY__ */
#define NO_PROC_ID 0xFF /* No processor magic marker */

31
include/asm-i386/sparsemem.h Normal file
View file

@ -0,0 +1,31 @@
#ifndef _I386_SPARSEMEM_H
#define _I386_SPARSEMEM_H
#ifdef CONFIG_SPARSEMEM
/*
* generic non-linear memory support:
*
* 1) we will not split memory into more chunks than will fit into the
* flags field of the struct page
*/
/*
* SECTION_SIZE_BITS 2^N: how big each section will be
* MAX_PHYSADDR_BITS 2^N: how much physical address space we have
* MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
*/
#ifdef CONFIG_X86_PAE
#define SECTION_SIZE_BITS 30
#define MAX_PHYSADDR_BITS 36
#define MAX_PHYSMEM_BITS 36
#else
#define SECTION_SIZE_BITS 26
#define MAX_PHYSADDR_BITS 32
#define MAX_PHYSMEM_BITS 32
#endif
/* XXX: FIXME -- wli */
#define kern_addr_valid(kaddr) (0)
#endif /* CONFIG_SPARSEMEM */
#endif /* _I386_SPARSEMEM_H */

32
include/asm-i386/string.h
View file

@ -116,7 +116,8 @@ __asm__ __volatile__(
"orb $1,%%al\n"
"3:"
:"=a" (__res), "=&S" (d0), "=&D" (d1)
:"1" (cs),"2" (ct));
:"1" (cs),"2" (ct)
:"memory");
return __res;
}
@ -138,8 +139,9 @@ __asm__ __volatile__(
"3:\tsbbl %%eax,%%eax\n\t"
"orb $1,%%al\n"
"4:"
:"=a" (__res), "=&S" (d0), "=&D" (d1), "=&c" (d2)
:"1" (cs),"2" (ct),"3" (count));
:"=a" (__res), "=&S" (d0), "=&D" (d1), "=&c" (d2)
:"1" (cs),"2" (ct),"3" (count)
:"memory");
return __res;
}
@ -158,7 +160,9 @@ __asm__ __volatile__(
"movl $1,%1\n"
"2:\tmovl %1,%0\n\t"
"decl %0"
:"=a" (__res), "=&S" (d0) : "1" (s),"0" (c));
:"=a" (__res), "=&S" (d0)
:"1" (s),"0" (c)
:"memory");
return __res;
}
@ -175,7 +179,9 @@ __asm__ __volatile__(
"leal -1(%%esi),%0\n"
"2:\ttestb %%al,%%al\n\t"
"jne 1b"
:"=g" (__res), "=&S" (d0), "=&a" (d1) :"0" (0),"1" (s),"2" (c));
:"=g" (__res), "=&S" (d0), "=&a" (d1)
:"0" (0),"1" (s),"2" (c)
:"memory");
return __res;
}
@ -189,7 +195,9 @@ __asm__ __volatile__(
"scasb\n\t"
"notl %0\n\t"
"decl %0"
:"=c" (__res), "=&D" (d0) :"1" (s),"a" (0), "0" (0xffffffffu));
:"=c" (__res), "=&D" (d0)
:"1" (s),"a" (0), "0" (0xffffffffu)
:"memory");
return __res;
}
@ -333,7 +341,9 @@ __asm__ __volatile__(
"je 1f\n\t"
"movl $1,%0\n"
"1:\tdecl %0"
:"=D" (__res), "=&c" (d0) : "a" (c),"0" (cs),"1" (count));
:"=D" (__res), "=&c" (d0)
:"a" (c),"0" (cs),"1" (count)
:"memory");
return __res;
}
@ -369,7 +379,7 @@ __asm__ __volatile__(
"je 2f\n\t"
"stosb\n"
"2:"
: "=&c" (d0), "=&D" (d1)
:"=&c" (d0), "=&D" (d1)
:"a" (c), "q" (count), "0" (count/4), "1" ((long) s)
:"memory");
return (s);
@ -392,7 +402,8 @@ __asm__ __volatile__(
"jne 1b\n"
"3:\tsubl %2,%0"
:"=a" (__res), "=&d" (d0)
:"c" (s),"1" (count));
:"c" (s),"1" (count)
:"memory");
return __res;
}
/* end of additional stuff */
@ -473,7 +484,8 @@ static inline void * memscan(void * addr, int c, size_t size)
"dec %%edi\n"
"1:"
: "=D" (addr), "=c" (size)
: "0" (addr), "1" (size), "a" (c));
: "0" (addr), "1" (size), "a" (c)
: "memory");
return addr;
}

2
include/asm-i386/thread_info.h
View file

@ -31,7 +31,7 @@ struct thread_info {
unsigned long flags; /* low level flags */
unsigned long status; /* thread-synchronous flags */
__u32 cpu; /* current CPU */
__s32 preempt_count; /* 0 => preemptable, <0 => BUG */
int preempt_count; /* 0 => preemptable, <0 => BUG */
mm_segment_t addr_limit; /* thread address space:

3
include/asm-i386/timer.h
View file

@ -22,6 +22,7 @@ struct timer_opts {
unsigned long (*get_offset)(void);
unsigned long long (*monotonic_clock)(void);
void (*delay)(unsigned long);
unsigned long (*read_timer)(void);
};
struct init_timer_opts {
@ -52,7 +53,9 @@ extern struct init_timer_opts timer_cyclone_init;
#endif
extern unsigned long calibrate_tsc(void);
extern unsigned long read_timer_tsc(void);
extern void init_cpu_khz(void);
extern int recalibrate_cpu_khz(void);
#ifdef CONFIG_HPET_TIMER
extern struct init_timer_opts timer_hpet_init;
extern unsigned long calibrate_tsc_hpet(unsigned long *tsc_hpet_quotient_ptr);

5
include/asm-i386/timex.h
View file

@ -47,6 +47,9 @@ static inline cycles_t get_cycles (void)
return ret;
}
extern unsigned long cpu_khz;
extern unsigned int cpu_khz;
extern int read_current_timer(unsigned long *timer_value);
#define ARCH_HAS_READ_CURRENT_TIMER 1
#endif

15
include/asm-i386/topology.h
View file

@ -60,12 +60,8 @@ static inline int node_to_first_cpu(int node)
return first_cpu(mask);
}
/* Returns the number of the node containing PCI bus number 'busnr' */
static inline cpumask_t __pcibus_to_cpumask(int busnr)
{
return node_to_cpumask(mp_bus_id_to_node[busnr]);
}
#define pcibus_to_cpumask(bus) __pcibus_to_cpumask(bus->number)
#define pcibus_to_node(bus) mp_bus_id_to_node[(bus)->number]
#define pcibus_to_cpumask(bus) node_to_cpumask(pcibus_to_node(bus))
/* sched_domains SD_NODE_INIT for NUMAQ machines */
#define SD_NODE_INIT (struct sched_domain) { \
@ -78,11 +74,14 @@ static inline cpumask_t __pcibus_to_cpumask(int busnr)
.imbalance_pct = 125, \
.cache_hot_time = (10*1000000), \
.cache_nice_tries = 1, \
.busy_idx = 3, \
.idle_idx = 1, \
.newidle_idx = 2, \
.wake_idx = 1, \
.per_cpu_gain = 100, \
.flags = SD_LOAD_BALANCE \
| SD_BALANCE_EXEC \
| SD_BALANCE_NEWIDLE \
| SD_WAKE_IDLE \
| SD_BALANCE_FORK \
| SD_WAKE_BALANCE, \
.last_balance = jiffies, \
.balance_interval = 1, \

2
include/asm-i386/unistd.h
View file

@ -256,7 +256,7 @@
#define __NR_io_submit 248
#define __NR_io_cancel 249
#define __NR_fadvise64 250
#define __NR_set_zone_reclaim 251
#define __NR_exit_group 252
#define __NR_lookup_dcookie 253
#define __NR_epoll_create 254

10
include/asm-ia64/agp.h
View file

@ -18,4 +18,14 @@
#define flush_agp_mappings() /* nothing */
#define flush_agp_cache() mb()
/* Convert a physical address to an address suitable for the GART. */
#define phys_to_gart(x) (x)
#define gart_to_phys(x) (x)
/* GATT allocation. Returns/accepts GATT kernel virtual address. */
#define alloc_gatt_pages(order) \
((char *)__get_free_pages(GFP_KERNEL, (order)))
#define free_gatt_pages(table, order) \
free_pages((unsigned long)(table), (order))
#endif /* _ASM_IA64_AGP_H */

2
include/asm-ia64/break.h
View file

@ -12,6 +12,8 @@
* OS-specific debug break numbers:
*/
#define __IA64_BREAK_KDB 0x80100
#define __IA64_BREAK_KPROBE 0x80200
#define __IA64_BREAK_JPROBE 0x80300
/*
* OS-specific break numbers:

1
include/asm-ia64/compat.h
View file

@ -27,6 +27,7 @@ typedef u16 compat_ipc_pid_t;
typedef s32 compat_daddr_t;
typedef u32 compat_caddr_t;
typedef __kernel_fsid_t compat_fsid_t;
typedef s32 compat_timer_t;
typedef s32 compat_int_t;
typedef s32 compat_long_t;

2
include/asm-ia64/fcntl.h
View file

@ -81,4 +81,6 @@ struct flock {
#define F_LINUX_SPECIFIC_BASE 1024
#define force_o_largefile() ( ! (current->personality & PER_LINUX32) )
#endif /* _ASM_IA64_FCNTL_H */

61
include/asm-ia64/kdebug.h Normal file
View file

@ -0,0 +1,61 @@
#ifndef _IA64_KDEBUG_H
#define _IA64_KDEBUG_H 1
/*
* include/asm-ia64/kdebug.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) Intel Corporation, 2005
*
* 2005-Apr Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
* <anil.s.keshavamurthy@intel.com> adopted from
* include/asm-x86_64/kdebug.h
*/
#include <linux/notifier.h>
struct pt_regs;
struct die_args {
struct pt_regs *regs;
const char *str;
long err;
int trapnr;
int signr;
};
int register_die_notifier(struct notifier_block *nb);
extern struct notifier_block *ia64die_chain;
enum die_val {
DIE_BREAK = 1,
DIE_SS,
DIE_PAGE_FAULT,
};
static inline int notify_die(enum die_val val, char *str, struct pt_regs *regs,
long err, int trap, int sig)
{
struct die_args args = {
.regs = regs,
.str = str,
.err = err,
.trapnr = trap,
.signr = sig
};
return notifier_call_chain(&ia64die_chain, val, &args);
}
#endif

116
include/asm-ia64/kprobes.h Normal file
View file

@ -0,0 +1,116 @@
#ifndef _ASM_KPROBES_H
#define _ASM_KPROBES_H
/*
* Kernel Probes (KProbes)
* include/asm-ia64/kprobes.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) IBM Corporation, 2002, 2004
* Copyright (C) Intel Corporation, 2005
*
* 2005-Apr Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
* <anil.s.keshavamurthy@intel.com> adapted from i386
*/
#include <linux/types.h>
#include <linux/ptrace.h>
#include <asm/break.h>
#define BREAK_INST (long)(__IA64_BREAK_KPROBE << 6)
typedef union cmp_inst {
struct {
unsigned long long qp : 6;
unsigned long long p1 : 6;
unsigned long long c : 1;
unsigned long long r2 : 7;
unsigned long long r3 : 7;
unsigned long long p2 : 6;
unsigned long long ta : 1;
unsigned long long x2 : 2;
unsigned long long tb : 1;
unsigned long long opcode : 4;
unsigned long long reserved : 23;
}f;
unsigned long long l;
} cmp_inst_t;
struct kprobe;
typedef struct _bundle {
struct {
unsigned long long template : 5;
unsigned long long slot0 : 41;
unsigned long long slot1_p0 : 64-46;
} quad0;
struct {
unsigned long long slot1_p1 : 41 - (64-46);
unsigned long long slot2 : 41;
} quad1;
} __attribute__((__aligned__(16))) bundle_t;
#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)pentry
#define SLOT0_OPCODE_SHIFT (37)
#define SLOT1_p1_OPCODE_SHIFT (37 - (64-46))
#define SLOT2_OPCODE_SHIFT (37)
#define INDIRECT_CALL_OPCODE (1)
#define IP_RELATIVE_CALL_OPCODE (5)
#define IP_RELATIVE_BRANCH_OPCODE (4)
#define IP_RELATIVE_PREDICT_OPCODE (7)
#define LONG_BRANCH_OPCODE (0xC)
#define LONG_CALL_OPCODE (0xD)
typedef struct kprobe_opcode {
bundle_t bundle;
} kprobe_opcode_t;
struct fnptr {
unsigned long ip;
unsigned long gp;
};
/* Architecture specific copy of original instruction*/
struct arch_specific_insn {
/* copy of the instruction to be emulated */
kprobe_opcode_t insn;
#define INST_FLAG_FIX_RELATIVE_IP_ADDR 1
#define INST_FLAG_FIX_BRANCH_REG 2
unsigned long inst_flag;
unsigned short target_br_reg;
};
/* ia64 does not need this */
static inline void jprobe_return(void)
{
}
/* ia64 does not need this */
static inline void arch_copy_kprobe(struct kprobe *p)
{
}
#ifdef CONFIG_KPROBES
extern int kprobe_exceptions_notify(struct notifier_block *self,
unsigned long val, void *data);
#else /* !CONFIG_KPROBES */
static inline int kprobe_exceptions_notify(struct notifier_block *self,
unsigned long val, void *data)
{
return 0;
}
#endif
#endif /* _ASM_KPROBES_H */

14
include/asm-ia64/mmzone.h
View file

@ -17,6 +17,20 @@
#ifdef CONFIG_DISCONTIGMEM
static inline int pfn_to_nid(unsigned long pfn)
{
#ifdef CONFIG_NUMA
extern int paddr_to_nid(unsigned long);
int nid = paddr_to_nid(pfn << PAGE_SHIFT);
if (nid < 0)
return 0;
else
return nid;
#else
return 0;
#endif
}
#ifdef CONFIG_IA64_DIG /* DIG systems are small */
# define MAX_PHYSNODE_ID 8
# define NR_NODE_MEMBLKS (MAX_NUMNODES * 8)

2
include/asm-ia64/param.h
View file

@ -27,7 +27,7 @@
*/
# define HZ 32
# else
# define HZ 1024
# define HZ CONFIG_HZ
# endif
# define USER_HZ HZ
# define CLOCKS_PER_SEC HZ /* frequency at which times() counts */

2
include/asm-ia64/percpu.h
View file

@ -50,7 +50,7 @@ extern void *per_cpu_init(void);
#else /* ! SMP */
#define per_cpu(var, cpu) (*((void)cpu, &per_cpu__##var))
#define per_cpu(var, cpu) (*((void)(cpu), &per_cpu__##var))
#define __get_cpu_var(var) per_cpu__##var
#define per_cpu_init() (__phys_per_cpu_start)

8
include/asm-ia64/perfmon.h
View file

@ -177,6 +177,10 @@ typedef union {
extern long perfmonctl(int fd, int cmd, void *arg, int narg);
typedef struct {
void (*handler)(int irq, void *arg, struct pt_regs *regs);
} pfm_intr_handler_desc_t;
extern void pfm_save_regs (struct task_struct *);
extern void pfm_load_regs (struct task_struct *);
@ -187,6 +191,10 @@ extern void pfm_syst_wide_update_task(struct task_struct *, unsigned long info,
extern void pfm_inherit(struct task_struct *task, struct pt_regs *regs);
extern void pfm_init_percpu(void);
extern void pfm_handle_work(void);
extern int pfm_install_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
extern int pfm_remove_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
/*
* Reset PMD register flags

9
include/asm-ia64/pgtable.h
View file

@ -8,7 +8,7 @@
* This hopefully works with any (fixed) IA-64 page-size, as defined
* in <asm/page.h>.
*
* Copyright (C) 1998-2004 Hewlett-Packard Co
* Copyright (C) 1998-2005 Hewlett-Packard Co
* David Mosberger-Tang <davidm@hpl.hp.com>
*/
@ -283,6 +283,7 @@ ia64_phys_addr_valid (unsigned long addr)
#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
#define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_P))
/*
* Macro to a page protection value as "uncacheable". Note that "protection" is really a
@ -551,7 +552,11 @@ do { \
/* These tell get_user_pages() that the first gate page is accessible from user-level. */
#define FIXADDR_USER_START GATE_ADDR
#define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
#ifdef HAVE_BUGGY_SEGREL
# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
#else
# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
#endif
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY

10
include/asm-ia64/processor.h
View file

@ -403,7 +403,10 @@ extern void ia64_setreg_unknown_kr (void);
* task_struct at this point.
*/
/* Return TRUE if task T owns the fph partition of the CPU we're running on. */
/*
* Return TRUE if task T owns the fph partition of the CPU we're running on.
* Must be called from code that has preemption disabled.
*/
#define ia64_is_local_fpu_owner(t) \
({ \
struct task_struct *__ia64_islfo_task = (t); \
@ -411,7 +414,10 @@ extern void ia64_setreg_unknown_kr (void);
&& __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
})
/* Mark task T as owning the fph partition of the CPU we're running on. */
/*
* Mark task T as owning the fph partition of the CPU we're running on.
* Must be called from code that has preemption disabled.
*/
#define ia64_set_local_fpu_owner(t) do { \
struct task_struct *__ia64_slfo_task = (t); \
__ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \

2
include/asm-ia64/smp.h
View file

@ -46,7 +46,7 @@ ia64_get_lid (void)
#define SMP_IRQ_REDIRECTION (1 << 0)
#define SMP_IPI_REDIRECTION (1 << 1)
#define smp_processor_id() (current_thread_info()->cpu)
#define raw_smp_processor_id() (current_thread_info()->cpu)
extern struct smp_boot_data {
int cpu_count;

59
include/asm-ia64/sn/mspec.h Normal file
View file

@ -0,0 +1,59 @@
/*
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_MSPEC_H
#define _ASM_IA64_SN_MSPEC_H
#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
#define FETCHOP_LOAD 0
#define FETCHOP_INCREMENT 8
#define FETCHOP_DECREMENT 16
#define FETCHOP_CLEAR 24
#define FETCHOP_STORE 0
#define FETCHOP_AND 24
#define FETCHOP_OR 32
#define FETCHOP_CLEAR_CACHE 56
#define FETCHOP_LOAD_OP(addr, op) ( \
*(volatile long *)((char*) (addr) + (op)))
#define FETCHOP_STORE_OP(addr, op, x) ( \
*(volatile long *)((char*) (addr) + (op)) = (long) (x))
#ifdef __KERNEL__
/*
* Each Atomic Memory Operation (AMO formerly known as fetchop)
* variable is 64 bytes long. The first 8 bytes are used. The
* remaining 56 bytes are unaddressable due to the operation taking
* that portion of the address.
*
* NOTE: The AMO_t _MUST_ be placed in either the first or second half
* of the cache line. The cache line _MUST NOT_ be used for anything
* other than additional AMO_t entries. This is because there are two
* addresses which reference the same physical cache line. One will
* be a cached entry with the memory type bits all set. This address
* may be loaded into processor cache. The AMO_t will be referenced
* uncached via the memory special memory type. If any portion of the
* cached cache-line is modified, when that line is flushed, it will
* overwrite the uncached value in physical memory and lead to
* inconsistency.
*/
typedef struct {
u64 variable;
u64 unused[7];
} AMO_t;
#endif /* __KERNEL__ */
#endif /* _ASM_IA64_SN_MSPEC_H */

28
include/asm-ia64/sn/sn_sal.h
View file

@ -115,6 +115,13 @@
#define SAL_IROUTER_INTR_XMIT SAL_CONSOLE_INTR_XMIT
#define SAL_IROUTER_INTR_RECV SAL_CONSOLE_INTR_RECV
/*
* Error Handling Features
*/
#define SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV 0x1
#define SAL_ERR_FEAT_LOG_SBES 0x2
#define SAL_ERR_FEAT_MFR_OVERRIDE 0x4
#define SAL_ERR_FEAT_SBE_THRESHOLD 0xffff0000
/*
* SAL Error Codes
@ -341,6 +348,25 @@ ia64_sn_plat_cpei_handler(void)
return ret_stuff.status;
}
/*
* Set Error Handling Features
*/
static inline u64
ia64_sn_plat_set_error_handling_features(void)
{
struct ia64_sal_retval ret_stuff;
ret_stuff.status = 0;
ret_stuff.v0 = 0;
ret_stuff.v1 = 0;
ret_stuff.v2 = 0;
SAL_CALL_REENTRANT(ret_stuff, SN_SAL_SET_ERROR_HANDLING_FEATURES,
(SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV | SAL_ERR_FEAT_LOG_SBES),
0, 0, 0, 0, 0, 0);
return ret_stuff.status;
}
/*
* Checks for console input.
*/
@ -472,7 +498,7 @@ static inline u64
ia64_sn_pod_mode(void)
{
struct ia64_sal_retval isrv;
SAL_CALL(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
SAL_CALL_REENTRANT(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
if (isrv.status)
return 0;
return isrv.v0;

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