From 84f5b6aef85a682c03d94644b54616e6ee9cae08 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Thu, 17 Dec 2020 12:05:30 +0530 Subject: [PATCH 1/2] pinctrl: qcom: Update configuration for Yupik Update pinctrl driver for Yupik, to match latest configuration. Change-Id: I067fb20535dd144bf07f1253dbf9b498de8bb123 Signed-off-by: Neeraj Upadhyay --- drivers/pinctrl/qcom/pinctrl-yupik.c | 35 ++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-yupik.c b/drivers/pinctrl/qcom/pinctrl-yupik.c index ae35485ce7d7..553ae718c287 100644 --- a/drivers/pinctrl/qcom/pinctrl-yupik.c +++ b/drivers/pinctrl/qcom/pinctrl-yupik.c @@ -621,7 +621,10 @@ enum yupik_functions { msm_mux_pll_clk, msm_mux_pll_reset, msm_mux_pri_mi2s, - msm_mux_prng_rosc, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, msm_mux_qdss_cti, msm_mux_qdss_gpio, msm_mux_qdss_gpio0, @@ -1090,9 +1093,18 @@ static const char * const pll_reset_groups[] = { static const char * const pri_mi2s_groups[] = { "gpio96", }; -static const char * const prng_rosc_groups[] = { +static const char * const prng_rosc0_groups[] = { "gpio123", }; +static const char * const prng_rosc1_groups[] = { + "gpio120", +}; +static const char * const prng_rosc2_groups[] = { + "gpio121", +}; +static const char * const prng_rosc3_groups[] = { + "gpio122", +}; static const char * const qdss_cti_groups[] = { "gpio15", "gpio16", "gpio18", "gpio19", "gpio156", "gpio157", "gpio165", "gpio166", @@ -1458,14 +1470,17 @@ static const struct msm_function yupik_functions[] = { FUNCTION(mss_grfc3), FUNCTION(cmu_rng0), FUNCTION(phase_flag12), + FUNCTION(prng_rosc1), FUNCTION(mss_grfc4), FUNCTION(cri_trng0), FUNCTION(phase_flag11), + FUNCTION(prng_rosc2), FUNCTION(mss_grfc5), FUNCTION(cri_trng1), FUNCTION(phase_flag10), + FUNCTION(prng_rosc3), FUNCTION(mss_grfc6), - FUNCTION(prng_rosc), + FUNCTION(prng_rosc0), FUNCTION(phase_flag9), FUNCTION(mss_grfc7), FUNCTION(cri_trng), @@ -1696,13 +1711,13 @@ static const struct msm_pingroup yupik_groups[] = { NA, NA, NA, 0, -1), [119] = PINGROUP(119, NA, mss_grfc2, cmu_rng1, phase_flag13, NA, NA, NA, NA, NA, 0xAF014, 2), - [120] = PINGROUP(120, NA, mss_grfc3, cmu_rng0, phase_flag12, NA, NA, - NA, NA, NA, 0, -1), - [121] = PINGROUP(121, NA, mss_grfc4, cri_trng0, phase_flag11, NA, NA, - NA, NA, NA, 0xAF014, 3), - [122] = PINGROUP(122, NA, mss_grfc5, cri_trng1, phase_flag10, NA, NA, - NA, NA, NA, 0, -1), - [123] = PINGROUP(123, NA, mss_grfc6, prng_rosc, phase_flag9, NA, NA, + [120] = PINGROUP(120, NA, mss_grfc3, cmu_rng0, phase_flag12, NA, + prng_rosc1, NA, NA, NA, 0, -1), + [121] = PINGROUP(121, NA, mss_grfc4, cri_trng0, phase_flag11, NA, + prng_rosc2, NA, NA, NA, 0xAF014, 3), + [122] = PINGROUP(122, NA, mss_grfc5, cri_trng1, phase_flag10, NA, + prng_rosc3, NA, NA, NA, 0, -1), + [123] = PINGROUP(123, NA, mss_grfc6, prng_rosc0, phase_flag9, NA, NA, NA, NA, NA, 0xAF014, 4), [124] = PINGROUP(124, NA, mss_grfc7, cri_trng, phase_flag8, NA, NA, NA, NA, NA, 0, -1), From 188f75cf17c5e7da915f588de43f3d44eb2fd192 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Thu, 17 Dec 2020 12:12:57 +0530 Subject: [PATCH 2/2] pinctrl: qcom: Add flexibility to disable the wakeup capability for Yupik By default, the system firmware enables the mpm wakeup functionality of all the supported GPIOs. However, certain usecases demand that this capability be disabled on certain gpios. Hence, provide a generic interface to disable the GPIOs as needed. Change-Id: I147629e0126b2eb41c645de03958ef480fd5d7d0 Signed-off-by: Neeraj Upadhyay --- drivers/pinctrl/qcom/pinctrl-yupik.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-yupik.c b/drivers/pinctrl/qcom/pinctrl-yupik.c index 553ae718c287..2543d4fbfefa 100644 --- a/drivers/pinctrl/qcom/pinctrl-yupik.c +++ b/drivers/pinctrl/qcom/pinctrl-yupik.c @@ -1849,9 +1849,32 @@ static const struct msm_pinctrl_soc_data yupik_pinctrl = { .nwakeirq_map = ARRAY_SIZE(yupik_pdc_map), }; +/* By default, all the gpios that are mpm wake capable are enabled. + * The following list disables the gpios explicitly + */ +static const unsigned int config_mpm_wake_disable_gpios[] = { +}; + +static void yupik_pinctrl_config_mpm_wake_disable_gpios(void) +{ + unsigned int i; + unsigned int n_gpios = ARRAY_SIZE(config_mpm_wake_disable_gpios); + + for (i = 0; i < n_gpios; i++) + msm_gpio_mpm_wake_set(config_mpm_wake_disable_gpios[i], false); +} + static int yupik_pinctrl_probe(struct platform_device *pdev) { - return msm_pinctrl_probe(pdev, &yupik_pinctrl); + int ret; + + ret = msm_pinctrl_probe(pdev, &yupik_pinctrl); + if (ret) + return ret; + + yupik_pinctrl_config_mpm_wake_disable_gpios(); + + return 0; } static const struct of_device_id yupik_pinctrl_of_match[] = {