diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 1521b7906a6e..d7780262ebdc 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -510,6 +510,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
 	/* register the clock */
 	hw = &div->hw;
 	ret = clk_hw_register(dev, hw);
+	hw->init = NULL;
 	if (ret) {
 		kfree(div);
 		hw = ERR_PTR(ret);
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 8b343e59dc61..623522cbc187 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -98,6 +98,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
 		ret = clk_hw_register(dev, hw);
 	else
 		ret = of_clk_hw_register(np, hw);
+	hw->init = NULL;
 	if (ret) {
 		kfree(fix);
 		hw = ERR_PTR(ret);
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index a7e4aef7a376..6844e177acb8 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -80,6 +80,7 @@ struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
 	/* register the clock */
 	hw = &fixed->hw;
 	ret = clk_hw_register(dev, hw);
+	hw->init = NULL;
 	if (ret) {
 		kfree(fixed);
 		hw = ERR_PTR(ret);
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index b1e556f20911..d071fc63ba8f 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -185,6 +185,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
 
 	hw = &fd->hw;
 	ret = clk_hw_register(dev, hw);
+	hw->init = NULL;
 	if (ret) {
 		kfree(fd);
 		hw = ERR_PTR(ret);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 1b99fc962745..40ce3fa093d7 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -171,6 +171,7 @@ struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
 
 	hw = &gate->hw;
 	ret = clk_hw_register(dev, hw);
+	hw->init = NULL;
 	if (ret) {
 		kfree(gate);
 		hw = ERR_PTR(ret);
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
index 9d930edd6516..8147c66ad9ad 100644
--- a/drivers/clk/clk-gpio.c
+++ b/drivers/clk/clk-gpio.c
@@ -149,7 +149,7 @@ static struct clk_hw *clk_register_gpio(struct device *dev, const char *name,
 		err = devm_clk_hw_register(dev, hw);
 	else
 		err = clk_hw_register(NULL, hw);
-
+	hw->init = NULL;
 	if (!err)
 		return hw;
 
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 66e91f740508..23d41798883c 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -190,6 +190,7 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
 
 	hw = &mux->hw;
 	ret = clk_hw_register(dev, hw);
+	hw->init = NULL;
 	if (ret) {
 		kfree(mux);
 		hw = ERR_PTR(ret);
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
index edcab3f7b7d3..1f135ea393f5 100644
--- a/include/dt-bindings/clock/qcom,rpmh.h
+++ b/include/dt-bindings/clock/qcom,rpmh.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */
 
 
 #ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
@@ -8,16 +8,22 @@
 /* RPMh controlled clocks */
 #define RPMH_CXO_CLK				0
 #define RPMH_CXO_CLK_A				1
-#define RPMH_LN_BB_CLK2				2
-#define RPMH_LN_BB_CLK2_A			3
-#define RPMH_LN_BB_CLK3				4
-#define RPMH_LN_BB_CLK3_A			5
-#define RPMH_RF_CLK1				6
-#define RPMH_RF_CLK1_A				7
-#define RPMH_RF_CLK2				8
-#define RPMH_RF_CLK2_A				9
-#define RPMH_RF_CLK3				10
-#define RPMH_RF_CLK3_A				11
-#define RPMH_IPA_CLK				12
+#define RPMH_LN_BB_CLK1				2
+#define RPMH_LN_BB_CLK1_A			3
+#define RPMH_LN_BB_CLK2				4
+#define RPMH_LN_BB_CLK2_A			5
+#define RPMH_LN_BB_CLK3				6
+#define RPMH_LN_BB_CLK3_A			7
+#define RPMH_RF_CLK1				8
+#define RPMH_RF_CLK1_A				9
+#define RPMH_RF_CLK2				10
+#define RPMH_RF_CLK2_A				11
+#define RPMH_RF_CLK3				12
+#define RPMH_RF_CLK3_A				13
+#define RPMH_RF_CLKD3				14
+#define RPMH_RF_CLKD3_A				15
+#define RPMH_RF_CLKD4				16
+#define RPMH_RF_CLKD4_A				17
+#define RPMH_IPA_CLK				18
 
 #endif