From c503ce604acb876bcd8bae1ce9f7550a0d63888c Mon Sep 17 00:00:00 2001 From: Vivek Aknurwar Date: Thu, 7 May 2020 01:17:42 -0700 Subject: [PATCH] clk: qcom: gdsc-regulator: Poll PWR_ON during GDSC HW to SW mode switch While switching from HW to SW control mode, HW may be busy updating internal required signals. Add a check that polls for PWR_ON status bit to ensure that the GDSC switches to SW mode before software starts to use SW mode. Change-Id: Ie6bd5c5e8c073fb70c696eeb6e911219108f9260 Signed-off-by: Vivek Aknurwar --- drivers/clk/qcom/gdsc-regulator.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/gdsc-regulator.c b/drivers/clk/qcom/gdsc-regulator.c index 301c6f47ff55..acef2c2bf04f 100644 --- a/drivers/clk/qcom/gdsc-regulator.c +++ b/drivers/clk/qcom/gdsc-regulator.c @@ -499,6 +499,20 @@ static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode) */ gdsc_mb(sc); udelay(1); + /* + * While switching from HW to SW mode, HW may be busy + * updating internal required signals. Polling for PWR_ON + * ensures that the GDSC switches to SW mode before software + * starts to use SW mode. + */ + if (sc->is_gdsc_enabled) { + ret = poll_gdsc_status(sc, ENABLED); + if (ret) { + dev_err(&rdev->dev, "%s enable timed out\n", + sc->rdesc.name); + goto done; + } + } sc->is_gdsc_hw_ctrl_mode = false; break; default: