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h8300 update for v4.4

Browse source 
some bug fix.
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Merge tag 'for-4.4' of git://git.osdn.jp/gitroot/uclinux-h8/linux

Pull h8300 updates from Yoshinori Sato:
 "Some bug fixes"

* tag 'for-4.4' of git://git.osdn.jp/gitroot/uclinux-h8/linux:
  h8300: enable CLKSRC_OF
  h8300: Don't set CROSS_COMPILE unconditionally
  asm-generic: {get,put}_user ptr argument evaluate only 1 time
  h8300: bit io fix
  h8300: zImage fix
  h8300: register address fix
  h8300: Fix alignment for .data
  h8300: unaligned divcr register support.
This commit is contained in:
Linus Torvalds 2015-11-12 15:26:39 -08:00
commit 7dac7102af
13 changed files with 40 additions and 35 deletions
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6
drivers/clk/h8300/clk-div.c
View file

@ -19,6 +19,7 @@ static void __init h8300_div_clk_setup(struct device_node *node)
const char *parent_name;
void __iomem *divcr = NULL;
int width;
int offset;
num_parents = of_clk_get_parent_count(node);
if (num_parents < 1) {
@ -31,11 +32,14 @@ static void __init h8300_div_clk_setup(struct device_node *node)
pr_err("%s: failed to map divide register", clk_name);
goto error;
}
offset = (unsigned long)divcr & 3;
offset = (3 - offset) * 8;
divcr = (void *)((unsigned long)divcr & ~3);
parent_name = of_clk_get_parent_name(node, 0);
of_property_read_u32(node, "renesas,width", &width);
clk = clk_register_divider(NULL, clk_name, parent_name,
CLK_SET_RATE_GATE, divcr, 0, width,
CLK_SET_RATE_GATE, divcr, offset, width,
CLK_DIVIDER_POWER_OF_TWO, &clklock);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);