From 7db2a3f608aad8f0932ed2b95f4daef2995cce29 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 22 Jun 2020 19:58:20 +0530 Subject: [PATCH] ARM: dts: msm: Add cpufreq hw debug support for HOLI and SHIMA Add support to print cpufreq hw debug registers on HOLI and SHIMA. Change-Id: Ic2bd35bfaa3c374461333bdd936407b710d3f6e9 --- qcom/holi.dtsi | 7 +++++++ qcom/shima.dtsi | 8 ++++++++ 2 files changed, 15 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index f1ab2ea2a27e..134c90f93f55 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1243,6 +1243,13 @@ #freq-domain-cells = <2>; }; + qcom,cpufreq-hw-debug@0fd91000 { + compatible = "qcom,cpufreq-hw-epss-debug"; + reg = <0x0fd91000 0x800>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + }; + ddr_bw_opp_table: ddr-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ae02be1e1589..e49259f837ee 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -989,6 +989,14 @@ #freq-domain-cells = <2>; }; + qcom,cpufreq-hw-debug@18591000 { + compatible = "qcom,cpufreq-hw-epss-debug"; + reg = <0x18591000 0x800>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, + <&cpufreq_hw 2>; + }; + qcom_tzlog: tz-log@0x146aa720 { compatible = "qcom,tz-log"; reg = <0x146aa720 0x3000>;