mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 06:09:23 -04:00
Merge "firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
7db9be171f
1 changed files with 170 additions and 102 deletions
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@ -39,6 +39,46 @@ static struct qcom_scm_entry qcom_scm_wb[] = {
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static DEFINE_MUTEX(qcom_scm_lock);
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#define MAX_QCOM_SCM_ARGS 10
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#define MAX_QCOM_SCM_RETS 3
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enum qcom_scm_arg_types {
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QCOM_SCM_VAL,
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QCOM_SCM_RO,
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QCOM_SCM_RW,
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QCOM_SCM_BUFVAL,
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};
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#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
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(((a) & 0x3) << 4) | \
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(((b) & 0x3) << 6) | \
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(((c) & 0x3) << 8) | \
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(((d) & 0x3) << 10) | \
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(((e) & 0x3) << 12) | \
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(((f) & 0x3) << 14) | \
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(((g) & 0x3) << 16) | \
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(((h) & 0x3) << 18) | \
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(((i) & 0x3) << 20) | \
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(((j) & 0x3) << 22) | \
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((num) & 0xf))
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#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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/**
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* struct qcom_scm_desc
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* @arginfo: Metadata describing the arguments in args[]
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* @args: The array of arguments for the secure syscall
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* @res: The values returned by the secure syscall
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*/
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struct qcom_scm_desc {
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u32 svc;
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u32 cmd;
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u32 arginfo;
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u64 args[MAX_QCOM_SCM_ARGS];
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u64 res[MAX_QCOM_SCM_RETS];
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u32 owner;
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};
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#define LEGACY_FUNCNUM(s, c) (((s) << 10) | ((c) & 0x3ff))
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/**
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@ -153,15 +193,19 @@ static u32 __qcom_scm_call_do(u32 cmd_addr)
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* and response buffers is taken care of by qcom_scm_call; however, callers are
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* responsible for any other cached buffers passed over to the secure world.
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*/
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static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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const void *cmd_buf, size_t cmd_len, void *resp_buf,
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size_t resp_len)
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static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc)
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{
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int arglen = desc->arginfo & 0xf;
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int ret;
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size_t i;
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struct qcom_scm_legacy_command *cmd;
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struct qcom_scm_legacy_response *rsp;
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const size_t cmd_len = arglen * sizeof(__le32);
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const size_t resp_len = MAX_QCOM_SCM_RETS * sizeof(__le32);
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size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len;
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dma_addr_t cmd_phys;
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__le32 *arg_buf;
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__le32 *res_buf;
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cmd = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
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if (!cmd)
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@ -170,10 +214,11 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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cmd->len = cpu_to_le32(alloc_len);
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cmd->buf_offset = cpu_to_le32(sizeof(*cmd));
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cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len);
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cmd->id = cpu_to_le32(LEGACY_FUNCNUM(desc->svc, desc->cmd));
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cmd->id = cpu_to_le32(LEGACY_FUNCNUM(svc_id, cmd_id));
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if (cmd_buf)
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memcpy(legacy_get_command_buffer(cmd), cmd_buf, cmd_len);
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arg_buf = legacy_get_command_buffer(cmd);
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for (i = 0; i < arglen; i++)
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arg_buf[i] = cpu_to_le32(desc->args[i]);
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rsp = legacy_command_to_response(cmd);
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@ -196,13 +241,13 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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sizeof(*rsp), DMA_FROM_DEVICE);
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} while (!rsp->is_complete);
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if (resp_buf) {
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dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
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le32_to_cpu(rsp->buf_offset),
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resp_len, DMA_FROM_DEVICE);
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memcpy(resp_buf, legacy_get_response_buffer(rsp),
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resp_len);
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}
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dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
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le32_to_cpu(rsp->buf_offset),
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resp_len, DMA_FROM_DEVICE);
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res_buf = legacy_get_response_buffer(rsp);
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for (i = 0; i < MAX_QCOM_SCM_RETS; i++)
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desc->res[i] = le32_to_cpu(res_buf[i]);
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out:
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dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
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kfree(cmd);
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@ -305,10 +350,11 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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int ret;
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int flags = 0;
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int cpu;
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struct {
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__le32 flags;
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__le32 addr;
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} cmd;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_SET_ADDR,
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.arginfo = QCOM_SCM_ARGS(2),
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};
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/*
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* Reassign only if we are switching from hotplug entry point
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@ -324,10 +370,9 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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if (!flags)
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return 0;
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cmd.addr = cpu_to_le32(virt_to_phys(entry));
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cmd.flags = cpu_to_le32(flags);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR,
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&cmd, sizeof(cmd), NULL, 0);
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desc.args[0] = flags;
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desc.args[1] = virt_to_phys(entry);
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ret = qcom_scm_call(dev, &desc);
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if (!ret) {
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for_each_cpu(cpu, cpus)
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qcom_scm_wb[cpu].entry = entry;
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@ -352,21 +397,20 @@ void __qcom_scm_cpu_power_down(u32 flags)
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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{
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struct {
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__le32 state;
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__le32 id;
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} req;
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__le32 scm_ret = 0;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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int ret;
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req.state = cpu_to_le32(state);
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req.id = cpu_to_le32(id);
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desc.args[0] = state;
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desc.args[1] = id;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_REMOTE_STATE,
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&req, sizeof(req), &scm_ret, sizeof(scm_ret));
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ret = qcom_scm_call(dev, &desc);
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return ret ? : le32_to_cpu(scm_ret);
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return ret ? : desc.res[0];
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}
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int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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@ -379,104 +423,107 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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{
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__le32 out;
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__le32 in;
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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in = cpu_to_le32(peripheral);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PIL_PAS_IS_SUPPORTED,
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&in, sizeof(in),
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&out, sizeof(out));
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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return ret ? false : !!out;
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ret = qcom_scm_call(dev, &desc);
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return ret ? false : !!desc.res[0];
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}
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int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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dma_addr_t metadata_phys)
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{
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__le32 scm_ret;
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int ret;
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struct {
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__le32 proc;
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__le32 image_addr;
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} request;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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request.proc = cpu_to_le32(peripheral);
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request.image_addr = cpu_to_le32(metadata_phys);
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desc.args[0] = peripheral;
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desc.args[1] = metadata_phys;
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desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PIL_PAS_INIT_IMAGE,
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&request, sizeof(request),
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&scm_ret, sizeof(scm_ret));
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ret = qcom_scm_call(dev, &desc);
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return ret ? : le32_to_cpu(scm_ret);
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return ret ? : desc.res[0];
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}
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int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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phys_addr_t addr, phys_addr_t size)
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phys_addr_t addr, phys_addr_t size)
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{
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__le32 scm_ret;
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int ret;
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struct {
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__le32 proc;
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__le32 addr;
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__le32 len;
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} request;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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request.proc = cpu_to_le32(peripheral);
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request.addr = cpu_to_le32(addr);
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request.len = cpu_to_le32(size);
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desc.args[0] = peripheral;
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desc.args[1] = addr;
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desc.args[2] = size;
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desc.arginfo = QCOM_SCM_ARGS(3);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PIL_PAS_MEM_SETUP,
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&request, sizeof(request),
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&scm_ret, sizeof(scm_ret));
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ret = qcom_scm_call(dev, &desc);
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return ret ? : le32_to_cpu(scm_ret);
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return ret ? : desc.res[0];
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}
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int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
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{
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__le32 out;
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__le32 in;
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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in = cpu_to_le32(peripheral);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
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&in, sizeof(in),
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&out, sizeof(out));
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ret = qcom_scm_call(dev, &desc);
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return ret ? : le32_to_cpu(out);
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return ret ? : desc.res[0];
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}
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int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
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{
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__le32 out;
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__le32 in;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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int ret;
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in = cpu_to_le32(peripheral);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PIL_PAS_SHUTDOWN,
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&in, sizeof(in),
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&out, sizeof(out));
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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return ret ? : le32_to_cpu(out);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : desc.res[0];
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}
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int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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{
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__le32 out;
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__le32 in = cpu_to_le32(reset);
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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int ret;
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MSS_RESET,
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&in, sizeof(in),
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&out, sizeof(out));
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desc.args[0] = reset;
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desc.args[1] = 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return ret ? : le32_to_cpu(out);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : desc.res[0];
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}
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int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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@ -500,16 +547,16 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
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int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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{
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int ret;
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__le32 svc_cmd = cpu_to_le32((svc_id << 10) | cmd_id);
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__le32 ret_val = 0;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_INFO,
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.cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
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.args[0] = (svc_id << 10) | cmd_id,
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.arginfo = QCOM_SCM_ARGS(1),
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};
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
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&svc_cmd, sizeof(svc_cmd), &ret_val,
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sizeof(ret_val));
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if (ret)
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return ret;
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ret = qcom_scm_call(dev, &desc);
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return le32_to_cpu(ret_val);
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return ret ? : desc.res[0];
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}
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int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
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@ -540,11 +587,32 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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u32 req_cnt, u32 *resp)
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{
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_HDCP,
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.cmd = QCOM_SCM_HDCP_INVOKE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE,
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req, req_cnt * sizeof(*req), resp, sizeof(*resp));
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desc.args[0] = req[0].addr;
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desc.args[1] = req[0].val;
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desc.args[2] = req[1].addr;
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desc.args[3] = req[1].val;
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desc.args[4] = req[2].addr;
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desc.args[5] = req[2].val;
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desc.args[6] = req[3].addr;
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desc.args[7] = req[3].val;
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desc.args[8] = req[4].addr;
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desc.args[9] = req[4].val;
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desc.arginfo = QCOM_SCM_ARGS(req_cnt * 2);
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ret = qcom_scm_call(dev, &desc);
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*resp = desc.res[0];
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return ret;
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}
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int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable)
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