bos0614_mmi: initial reference driver

Initial reference kernel driver code for BOS0614 piezo haptic IC

Change-Id: Ia7d7abca9eca2f077c830a7edada0f7450a8cebc
Signed-off-by: Konstantin Makariev <hcv867@motorola.com>
Reviewed-on: https://gerrit.mot.com/1870423
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
Reviewed-by: Ling Jin <lingjin@motorola.com>
Submit-Approved: Jira Key

drivers/input/misc/bos0614_mmi/LICENSE

@@ -0,0 +1,339 @@
+                    GNU GENERAL PUBLIC LICENSE
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drivers/input/misc/bos0614_mmi/Makefile

@@ -0,0 +1,17 @@
+obj-m := bosDriverModule.o
+bosDriverModule-y := i2cLinux.o
+bosDriverModule-y += bosDriver.o
+bosDriverModule-y += libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.o
+bosDriverModule-y += libs/dk-core/contribs/comm-stack-dk/data.o
+
+ccflags-y += -I$(src)/libs/dk-core/src
+ccflags-y += -I$(src)/libs/dk-core/
+ccflags-y += -std=gnu99
+ccflags-y += -DDEBUG
+ccflags-y += -DLITTLE_ENDIAN=1234
+ccflags-y += -DBYTE_ORDER=LITTLE_ENDIAN
+
+PWD := $(shell pwd)
+
+default:
+	$(MAKE) -C $(KERNELDIR) M=$(PWD)

drivers/input/misc/bos0614_mmi/README.md

@@ -0,0 +1,180 @@
+# BOS0614 Kernel Driver
+
+![GitHub Logo](/images/logo.png)
+
+_Version: 1.0.0_
+
+_Copyright (c) 2021 Boreas Technologies All rights reserved._
+
+_GNU GENERAL PUBLIC V2 LICENSE_
+
+Allow to configure the button press & release detection with feedback generated with the synthesizer. This linux kernel
+driver provides a file system API (String base). The binary file API & GPIO configuration will be supported in the
+subsequent release.
+
+Kbuild configuration are not yet available. Please use Linux Kernel makefiles methods for compiling the driver.
+
+_Tested against the Linux Kernel V4.14_
+
+## File System API (user space)
+
+### chip_id
+
+_Access: Read only_
+
+Return the chip id in hexadecimal value
+
+* 0x0D: BOS0614 Rev B
+
+### sensing_config
+
+_Access: Write only_
+
+Configure the hardware press or release detection on chip
+
+**Arguments**
+
+* channel id :        The channel number starting from 0
+* mode :              The detection mode such threshold (0) or slope (1) detection
+* direction:          The button direction such press (0) or release (1)
+* debouncing:         The debouncing duration in microseconds
+* stabilization:      The stabilization duration in milliseconds
+
+### sensing_autoplay
+
+_Access: Write only_
+
+Setup autoplay configuration. The autoplay mechanism allows the BOS0614 to play automatically a feedback once a press or
+release event is detected.
+
+**Arguments**
+
+* channel id :        The channel number starting from 0
+* waveform id:        The waveform id to play as a feedback
+* direction:          The button direction which the specified feedback will be played
+
+### sensing_stop
+
+_Access: Write only_
+
+Deactivate the button detection for a specific channel & direction
+
+**Arguments**
+
+* channel id :        The channel number starting from 0
+* direction:          The button direction such press (0) or release (1)
+
+### set_slice
+
+_Access: Write only_
+
+Create a slice (simple waveform). Slices are allocated into the BOS0614 RAM using the slice id. If you declare multiple
+time the same slice id, only the latest set slice configuration will remain into the RAM.
+
+**Arguments**
+
+* slice id:           The slice id (must be unique)
+* amplitude:          The sinus amplitude in milliVolt
+* frequency:          The sinus frequency in milliHertz.
+* cycle:              Duration of the sinus in period (only integer)
+* channel mask:       The list of channel to play the waveform. Each bit represent a channel #. The LSB reprensents the
+  channel #0 and the fourth bit (from LSB) the channel #4. The maximum value is 15d.
+
+### set_waveform
+
+_Access: Write only_
+
+Create a waveform by composing it with slices. Same as the slice. Waveforms are allocated into the BOS0614 RAM. Waveform
+unicity is based on the waveform id.
+
+**Arguments**
+
+* waveform id:        The waveform id
+* start slice id:     The first slice of the sequence to play
+* number of slice:    The number of slice to include starting from the start slice id param.
+* cycle:              The amount of time the sequence of slices is repeated
+* channel mask:       The list of channel to play the waveform. Each bit represent a channel #. The LSB reprensents the
+  channel #0 and the fourth bit (from LSB) the channel #4. The maximum value is 15d.
+
+### ctrl_output
+
+_Access: Write only_
+
+Control the BOS0614 output drive
+
+**Arguments**
+
+*state:               Output state: On (1) and Off (0)
+
+### ic_errors
+
+_Access: Read only_
+
+Read the IC operational status. Operational status are defined in the datasheet
+> SC: 0 UVLO: 0 IDAC: 0 MAX_POWER: 0 OVT: 0 OVV: 0
+
+### synth_play
+
+_Access: Write only_
+
+Arm the synthesizer for playing a specific sequence of waveforms. The waveform sequence is continuous sequence.
+
+**Arguments**
+
+* start:              The waveform id to start with.
+* stop:               The waveform id to end with (inclusively).
+
+## Virtual Button Example - on chip detection
+
+This example configure the button detection mechanism on the channel #0 with a specific feedback for the press and one
+for the release event. This example uses a i2c device instance on the bus i2c #1 with the address 0x002c.
+
+### 1. Configure the feedback for press event.
+
+Press Feedback:
+
+Press Slice (Slice #0) : 60 volts amplitude @175 Hz 2 Cycle on channel #0
+
+`echo 0 60000 175000 2 1 > /sys/bus/i2c/devices/1-002c/set_slice`
+
+Stabilization Slice (Slice #1) : 0 volts amplitude @250 Hz 2 cycle on channel #0
+
+`echo 1 00000 250000 2 1 >/sys/bus/i2c/devices/1-002c/set_slice`
+
+Setup the waveform #0 using the two previous slices
+
+`echo 0 0 2 1 1 > /sys/bus/i2c/devices/1-002c/set_waveform`
+
+### 2. Configure the feedback for release event.
+
+Release Slice (Slice #2) : 60 volts amplitude @170 Hz 2 Cycle on channel #0
+
+`echo 2 60000 170000 2 1 > /sys/bus/i2c/devices/1-002c/set_slice`
+
+Stabilization Slice (Slice #3) : 0 volts amplitude @250 Hz 11 cycle on channel #0
+
+`echo 3 00000 250000 11 1 > /sys/bus/i2c/devices/1-002c/set_slice`
+
+Setup the waveform #1 using the two previous slices
+
+`echo 1 2 2 1 1 >/sys/bus/i2c/devices/1-002c/set_waveform`
+
+### 3. Activate Press Detection and Autoplay on button press event
+
+Setup press detection with threshold mode, 1.2 Volt threshold, 4000 uS debounce time and 4 milliseconds stabilization
+
+`echo 0 0 0 4000 1200 4 > /sys/bus/i2c/devices/1-002c/sensing_config`
+
+`echo 0 0 0 >/sys/bus/i2c/devices/1-002c/sensing_autoplay`
+
+### 4. Activate Release Detection and Autoplay on button release event
+
+Setup release detection with slope mode, -11 mV gradient, 8000 uS debounce time and 32 milliseconds stabilization
+
+`echo 0 1 1 8000 -11 32 > /sys/bus/i2c/devices/1-002c/sensing_config`
+
+`echo 0 1 1 > /sys/bus/i2c/devices/1-002c/sensing_autoplay`
+
+
+
+

drivers/input/misc/bos0614_mmi/bosDriver.c

@@ -0,0 +1,599 @@
+//
+// Description: Linux Boréas Haptic Driver for I2C base IC
+//
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/i2c.h>
+#include "libs/dk-core/src/bsp/drivers/haptic/bosDriver.h"
+#include "i2cLinux.h"
+#include <libs/dk-core/src/bsp/drivers/i2c/i2c.h>
+#include <libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.h>
+
+typedef struct
+{
+    I2c *i2c;
+    const struct i2c_device_id *id;
+    struct mutex lock;
+    struct device *dev;
+    HapticDriver *hapticDriver;
+} Context;
+
+#define SET_WAVEFORM_PARAM_LENGTH (5)
+#define SET_SLICE_PARAM_LENGTH (5)
+#define SYNTH_PLAY_PARAM_LENGTH (2)
+#define CTRL_OUTPUT_PARAM_LENGTH (1)
+#define SENSING_CONFIG_PARAM_LENGTH (6)
+#define SENSING_AUTO_FEEDBACK_PARAM_LENGTH (3)
+#define STOP_SENSING_PARAM_LENGTH (2)
+
+static ssize_t getChipId(struct device *dev,
+                         struct device_attribute *attr, char *buf)
+{
+    Context *ctx = dev_get_drvdata(dev);
+    u32 chipId = 0;
+    (void) attr;
+
+    if (ctx != NULL)
+    {
+        mutex_lock(&ctx->lock);
+
+        if (ctx->hapticDriver != NULL)
+        {
+            chipId = ctx->hapticDriver->getChipId(ctx->hapticDriver);
+        }
+
+        mutex_unlock(&ctx->lock);
+    }
+
+    return snprintf(buf, PAGE_SIZE, "0x%x\n", chipId);
+}
+
+static DEVICE_ATTR(chip_id, 0440, getChipId, NULL);
+
+static bool hasError(BOSError *errors, size_t length, BOSError errorType)
+{
+    bool res = false;
+
+    if (errors != NULL)
+    {
+        for (size_t index = 0; index < length; index++)
+        {
+            if (errors[index] == errorType)
+            {
+                res = true;
+                break;
+            }
+        }
+    }
+
+    return res;
+}
+
+
+static ssize_t getIcErrors(struct device *dev,
+                           struct device_attribute *attr, char *buf)
+{
+    Context *ctx = dev_get_drvdata(dev);
+    ssize_t res = -EIO;
+
+    if (ctx != NULL && ctx->hapticDriver != NULL)
+    {
+        mutex_lock(&ctx->lock);
+
+        BOSError *errors = kzalloc(sizeof(BOSError) * BOSERROR_Length, GFP_KERNEL);
+
+        if (errors != NULL)
+        {
+            HapticDriver *driver = ctx->hapticDriver;
+            size_t nbrErros = driver->getError(driver, errors, BOSERROR_Length);
+
+            res = snprintf(buf, PAGE_SIZE, "SC: %d UVLO: %d IDAC: %d MAX_POWER: %d OVT: %d OVV: %d\n",
+                           hasError(errors, nbrErros, BOSERROR_SHORT_CIRCUIT),
+                           hasError(errors, nbrErros, BOSERROR_UVLO),
+                           hasError(errors, nbrErros, BOSERROR_IDAC),
+                           hasError(errors, nbrErros, BOSERROR_MAX_POWER),
+                           hasError(errors, nbrErros, BOSERROR_OVT),
+                           hasError(errors, nbrErros, BOSERROR_OVV));
+
+            kfree(errors);
+        }
+
+
+        mutex_unlock(&ctx->lock);
+    }
+
+    return res;
+}
+
+static DEVICE_ATTR(ic_errors, 0440, getIcErrors, NULL);
+
+static ssize_t setSynthWaveform(struct device *dev,
+                                struct device_attribute *attr,
+                                const char *buf, size_t count)
+{
+    Context *ctx = dev_get_drvdata(dev);
+    ssize_t res = -EIO;
+    (void) attr;
+
+    if (ctx != NULL && ctx->hapticDriver != NULL)
+    {
+        mutex_lock(&ctx->lock);
+
+        WaveformId id;
+        uint8_t startSliceId;
+        size_t nbrOfSlices;
+        uint16_t cycle;
+        uint8_t outputChannel;
+
+        size_t paramLength = sscanf(buf, "%hi %hi %zi %hi %hi", &id, &startSliceId, &nbrOfSlices, &cycle,
+                                    &outputChannel);
+        dev_dbg(ctx->dev,
+                "[Set Synth Waveform] Waveform Id: %d Start Slice Id: %d Nbr Of Slices: %d Cycle: %d Output Channel: %d\n",
+                id, startSliceId, nbrOfSlices, cycle, outputChannel);
+
+        if (paramLength == SET_WAVEFORM_PARAM_LENGTH)
+        {
+            HapticDriver *driver = ctx->hapticDriver;
+
+            if (driver->synthSetWaveform(driver, id, startSliceId, nbrOfSlices, cycle, outputChannel))
+            {
+                res = count;
+            }
+        }
+
+        mutex_unlock(&ctx->lock);
+    }
+
+    return res;
+}
+
+static DEVICE_ATTR(set_waveform, 0220, NULL, setSynthWaveform);
+
+static ssize_t setSynthSlice(struct device *dev,
+                             struct device_attribute *attr,
+                             const char *buf, size_t count)
+{
+    (void) attr;
+    Context *ctx = dev_get_drvdata(dev);
+    ssize_t res = -EIO;
+
+    if (ctx != NULL && ctx->hapticDriver != NULL)
+    {
+        mutex_lock(&ctx->lock);
+
+        HapticDriver *driver = ctx->hapticDriver;
+        SynthSlice slice;
+        uint8_t outputChannel;
+
+        size_t paramLength = sscanf(buf, "%d %d %d %d %d", &slice.sliceId, &slice.mVAmp, &slice.mHzFreq,
+                                    &slice.cycle, &outputChannel);
+
+        dev_dbg(ctx->dev,
+                "[Set Slice] Slice Id: %d Amplitude: %d mV Frequency: %d milliHertz Cycle: %d Output Channel: %d\n",
+                slice.sliceId, slice.mVAmp, slice.mHzFreq, slice.cycle, outputChannel);
+
+        if (paramLength == SET_SLICE_PARAM_LENGTH &&
+            driver->synthSetSlice(driver, (const SynthSlice *) &slice, outputChannel))
+        {
+            res = count;
+        }
+
+        mutex_unlock(&ctx->lock);
+    }
+
+    return res;
+}
+
+static DEVICE_ATTR(set_slice, 0220, NULL, setSynthSlice);
+
+
+static ssize_t synthPlay(struct device *dev,
+                         struct device_attribute *attr,
+                         const char *buf, size_t count)
+{
+    (void) attr;
+    Context *ctx = dev_get_drvdata(dev);
+    ssize_t res = -EIO;
+
+    if (ctx != NULL && ctx->hapticDriver != NULL)
+    {
+        mutex_lock(&ctx->lock);
+
+        HapticDriver *driver = ctx->hapticDriver;
+
+        WaveformId start;
+        WaveformId stop;
+
+        size_t paramLength = sscanf(buf, "%hi %hi", &start, &stop);
+
+        if (paramLength == SYNTH_PLAY_PARAM_LENGTH && driver->wfsPlay(driver, start, stop))
+        {
+            res = count;
+        }
+
+        mutex_unlock(&ctx->lock);
+    }
+
+    return res;
+}
+
+static DEVICE_ATTR(synth_play, 0220, NULL, synthPlay);
+
+static ssize_t setOutput(struct device *dev,
+                         struct device_attribute *attr,
+                         const char *buf, size_t count)
+{
+    (void) attr;
+    Context *ctx = dev_get_drvdata(dev);
+    ssize_t res = -EIO;
+
+    if (ctx != NULL && ctx->hapticDriver != NULL)
+    {
+        mutex_lock(&ctx->lock);
+
+        HapticDriver *driver = ctx->hapticDriver;
+
+        int outputState = 0;
+        size_t paramLength = sscanf(buf, "%d", &outputState);
+
+        bool bOutputState = outputState > 0 ? true : false;
+
+        if (paramLength == CTRL_OUTPUT_PARAM_LENGTH &&
+            driver->ctrlOutput(driver, bOutputState))
+        {
+            dev_dbg(ctx->dev,
+                    "[Set Output] State: %d \n", bOutputState);
+            res = count;
+        }
+
+        mutex_unlock(&ctx->lock);
+    }
+
+    return res;
+}
+
+static DEVICE_ATTR(ctrl_output, 0220, NULL, setOutput);
+
+const char *slopeDetection = "Slope";
+const char *thresholdDetection = "Threshold";
+
+static const char *getSensingDetectionMode(SensingDetectionMode mode)
+{
+    const char *stringDetectionMode = NULL;
+    switch (mode)
+    {
+        case SensingDetectionMode_Slope:
+            stringDetectionMode = slopeDetection;
+            break;
+        case SensingDetectionMode_Threshold:
+            stringDetectionMode = thresholdDetection;
+            break;
+    }
+
+    return stringDetectionMode;
+}
+
+const char *sensingPressDirection = "Press";
+const char *sensingReleaseDirection = "Release";
+const char *sensingPressReleaseDirection = "Press & Release";
+
+static const char *getSensingDirection(SensingDirection direction)
+{
+    const char *directionString = NULL;
+
+    switch (direction)
+    {
+        case SensingDirection_Press:
+            directionString = sensingPressDirection;
+            break;
+        case SensingDirection_Release:
+            directionString = sensingReleaseDirection;
+            break;
+        case SensingDirection_Both:
+            directionString = sensingPressReleaseDirection;
+            break;
+    }
+
+    return directionString;
+}
+
+static ssize_t setSensingConfig(struct device *dev,
+                                struct device_attribute *attr,
+                                const char *buf, size_t count)
+{
+    (void) attr;
+    Context *ctx = dev_get_drvdata(dev);
+    ssize_t res = -EIO;
+
+    if (ctx != NULL && ctx->hapticDriver != NULL)
+    {
+        mutex_lock(&ctx->lock);
+
+        HapticDriver *driver = ctx->hapticDriver;
+
+        SensingConfig config;
+        ChannelId channelId;
+
+        size_t paramLength = sscanf(buf, "%hhu %d %d %hd %hd %s",
+                                    &channelId, &config.mode, &config.direction,
+                                    &config.debounceUs,
+                                    &config.thresholdMv,
+                                    &config.stabilisationMs);
+
+        const char *directionS = getSensingDirection(config.direction);
+        const char *modeS = getSensingDetectionMode(config.mode);
+
+        if (paramLength == SENSING_CONFIG_PARAM_LENGTH &&
+            directionS != NULL &&
+            modeS != NULL &&
+            driver->configSensing(driver, channelId, config) &&
+            ctx->hapticDriver->configGPO(ctx->hapticDriver, channelId, GPO_ButtonState))
+        {
+            dev_dbg(ctx->dev,
+                    "[Sensing config] Success Channel #: %d Mode: %s Direction: %s Debouncing Duration: %d microS Threshold: %d Stabilization Duration: %d ms\n",
+                    channelId, modeS, directionS, config.debounceUs,
+                    config.thresholdMv, config.stabilisationMs);
+            res = count;
+        }
+
+        mutex_unlock(&ctx->lock);
+    }
+
+    return res;
+}
+
+static DEVICE_ATTR(sensing_config, 0220, NULL, setSensingConfig);
+
+static ssize_t setSensingAutoPlay(struct device *dev,
+                                  struct device_attribute *attr,
+                                  const char *buf, size_t count)
+{
+    (void) attr;
+    Context *ctx = dev_get_drvdata(dev);
+    ssize_t res = -EIO;
+
+    if (ctx != NULL && ctx->hapticDriver != NULL)
+    {
+        mutex_lock(&ctx->lock);
+
+        HapticDriver *driver = ctx->hapticDriver;
+
+        ChannelId channelId;
+        WaveformId id;
+        SensingDirection direction;
+
+        size_t paramLength = sscanf(buf, "%d %d %d", &channelId, &id, &direction);
+        const char *directionS = getSensingDirection(direction);
+
+
+        if (paramLength == SENSING_AUTO_FEEDBACK_PARAM_LENGTH &&
+            directionS != NULL &&
+            driver->sensingAutoPlayWave(driver, channelId, id, direction))
+        {
+            dev_dbg(ctx->dev, "[Set Sensing Automatic Feedback] Channel #: %d Waveform #: %d Direction: %s", channelId,
+                    id, directionS);
+            res = count;
+        }
+
+        mutex_unlock(&ctx->lock);
+    }
+
+
+    return res;
+}
+
+static DEVICE_ATTR(sensing_autoplay, 0220, NULL, setSensingAutoPlay);
+
+static ssize_t stopSensing(struct device *dev,
+                           struct device_attribute *attr,
+                           const char *buf, size_t count)
+{
+    (void) attr;
+    Context *ctx = dev_get_drvdata(dev);
+    ssize_t res = -EIO;
+
+    if (ctx != NULL && ctx->hapticDriver != NULL)
+    {
+        mutex_lock(&ctx->lock);
+
+        HapticDriver *driver = ctx->hapticDriver;
+
+        ChannelId channelId;
+        SensingDirection direction;
+
+        size_t paramLength = sscanf(buf, "%d %d", &channelId, &direction);
+        const char *directionS = getSensingDirection(direction);
+
+        if (paramLength == STOP_SENSING_PARAM_LENGTH &&
+            directionS != NULL &&
+            driver->stopSensing(driver, channelId, direction))
+        {
+            dev_dbg(ctx->dev, "[Remove Sensing Profile] Channel #: %d Direction: %s", channelId, directionS);
+            res = count;
+        }
+
+
+        mutex_unlock(&ctx->lock);
+    }
+
+
+    return res;
+}
+
+static DEVICE_ATTR(sensing_stop, 0220, NULL, stopSensing);
+
+static struct attribute *bosDriverAttrs[] = {
+        &dev_attr_chip_id.attr,
+        &dev_attr_set_waveform.attr,
+        &dev_attr_set_slice.attr,
+        &dev_attr_synth_play.attr,
+        &dev_attr_ic_errors.attr,
+        &dev_attr_ctrl_output.attr,
+        &dev_attr_sensing_config.attr,
+        &dev_attr_sensing_autoplay.attr,
+        &dev_attr_sensing_stop.attr,
+        NULL,
+};
+
+static struct attribute_group bosDriverAttrGroup = {
+        .attrs = bosDriverAttrs
+};
+
+static void freeResources(Context *ctx)
+{
+    if (ctx != NULL)
+    {
+        sysfs_remove_group(&ctx->dev->kobj, &bosDriverAttrGroup);
+
+        if (ctx->i2c != NULL)
+        {
+            i2cBoreasLinuxFree(ctx->i2c);
+        }
+
+        mutex_destroy(&ctx->lock);
+    }
+
+}
+
+/*
+ * Public Section
+ */
+
+static int bosDriverI2cProbe(struct i2c_client *client,
+                             const struct i2c_device_id *id)
+{
+    int res = -ENODEV;
+
+    dev_info(&client->dev, "%s called\n", __func__);
+
+    if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
+    {
+        dev_err(&client->dev, "%s:I2C check failed\n", __func__);
+        res = -ENODEV;
+        goto bosDriverProbeError;
+    }
+
+    Context *ctx = devm_kzalloc(&client->dev, sizeof(*ctx), GFP_KERNEL);
+
+    if (ctx == NULL)
+    {
+        dev_err(&client->dev, "%s:no memory\n", __func__);
+        res = -ENOMEM;
+        goto bosDriverProbeError;
+    }
+
+    ctx->dev = &client->dev;
+    i2c_set_clientdata(client, ctx);
+    dev_set_drvdata(&client->dev, ctx);
+
+    ctx->i2c = i2cBoreasLinuxInit(client);
+
+    Bos0614Resource resource = {.i2c = ctx->i2c, .gpioA = NULL, .gpioB = NULL, .gpioC = NULL, .gpioD = NULL};
+    ctx->hapticDriver = bos0614DriverI2cInit(resource);
+
+    if (ctx->i2c == NULL || ctx->hapticDriver == NULL)
+    {
+        dev_err(&client->dev, "Failed to instantiate BOS0614 driver\n");
+        goto bosDriverProbeError;
+    }
+
+    mutex_init(&ctx->lock);
+
+    int err = sysfs_create_group(&ctx->dev->kobj, &bosDriverAttrGroup);
+
+    if (err)
+    {
+        dev_err(&client->dev, "Failed to instantiate FS attributes\n");
+        goto bosDriverProbeError;
+    }
+
+    if (ctx->i2c == NULL || ctx->hapticDriver == NULL)
+    {
+        dev_err(&client->dev, "Boreas Haptic Driver failed to instantiate I2C or Haptic Driver\n");
+        goto bosDriverProbeError;
+    }
+
+    res = 0;
+
+    dev_info(&client->dev, "BosDriver Successfully Configured \n");
+
+    bosDriverProbeError:
+
+    if (res != 0)
+    {
+        freeResources(ctx);
+        dev_err(&client->dev, "Boreas Haptic Driver failed to probe\n");
+    }
+
+    return res;
+}
+
+static int bosDriverI2cRemove(struct i2c_client *client)
+{
+    int res = -ENODEV;
+
+    dev_info(&client->dev, "%s called \n", __func__);
+
+    Context *ctx = i2c_get_clientdata(client);
+
+    freeResources(ctx);
+
+    return res;
+}
+
+static const struct i2c_device_id bosDriverI2cId[] = {
+        {"bos0614", 0}
+};
+
+static const unsigned short addrList[] = {
+        0x2c,
+};
+
+static int detect(struct i2c_client *client, struct i2c_board_info *info)
+{
+    dev_info(&client->dev, "%s Remove bosDriver \n", __func__);
+    return 0;
+}
+
+static struct i2c_driver bosDriverI2c = {
+        .class = I2C_CLASS_HWMON,
+        .driver = {
+                .name = "bos0614",
+                .owner = THIS_MODULE,
+        },
+        .probe = bosDriverI2cProbe,
+        .remove = bosDriverI2cRemove,
+        .detect = detect,
+        .id_table = bosDriverI2cId,
+        .address_list = addrList
+};
+
+module_i2c_driver(bosDriverI2c)
+
+MODULE_AUTHOR("Pascal-Frédéric St-Laurent <pfstlaurent@boreas.ca>");
+MODULE_DESCRIPTION("I2C Driver for Boréas Haptic Technologies");
+MODULE_LICENSE("GPL v2");

drivers/input/misc/bos0614_mmi/bsp.h

@@ -0,0 +1,30 @@
+//
+// Description: Boréas Board Support Package for Linux Kernel
+//
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#ifndef BORÉAS_HAPTIC_DRIVER_LINUX_BSP_H
+#define BORÉAS_HAPTIC_DRIVER_LINUX_BSP_H
+
+#define BOS0614_NBR_OF_INSTANCE (1)
+
+#endif //BORÉAS_HAPTIC_DRIVER_LINUX_BSP_H

drivers/input/misc/bos0614_mmi/coreDefOption.h

@@ -0,0 +1,26 @@
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+
+#ifndef DKCORE_COREDEFOPTION_H
+#define DKCORE_COREDEFOPTION_H
+
+#define BOS0614_NBR_OF_INSTANCE (1)
+
+#endif //DKCORE_COREDEFOPTION_H

drivers/input/misc/bos0614_mmi/envSetup.sh

@@ -0,0 +1,49 @@
+#To configure
+export ANDROID_AOSP="/home/pfstlaurent/workspace/HDK855_Android-P_v1.0/Source_Package/SM8150P_HDK_855_Android-P_v1.0/"
+export ANDROID_KERNEL_LOC=$ANDROID_AOSP/out/target/product/msmnile/obj/kernel/msm-4.14
+
+CURRENT_PATH=$(pwd)
+cd $ANDROID_AOSP
+. build/envsetup.sh
+lunch msmnile-userdebug
+cd $CURRENT_PATH
+
+export CROSS_COMPILE_ARM32=$ANDROID_AOSP/prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/bin
+export CLANG=$ANDROID_AOSP/prebuilts/clang/host/linux-x86/clang-4691093/bin
+export PATH=$PATH:$CROSS_COMPILE_ARM32:$CLANG
+export TARGET_PREBUILT_KERNEL=$ANDROID_KERNEL_LOC/out/android-msm-pixel-4.9/private/msm-google/arch/arm64/boot/Image.lz4-dtb
+
+adb root
+alias build="ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make CC=clang KERNELDIR=$ANDROID_KERNEL_LOC"
+alias push="adb push bosDriverModule.ko /mnt/vendor/persist"
+alias load="adb shell insmod /mnt/vendor/persist/bosDriverModule.ko"
+alias rmmod="adb shell rmmod bosDriverModule.ko"
+alias lsmod="adb shell lsmod"
+alias new_device="adb shell \"echo bos0614 0x2c > /sys/bus/i2c/devices/i2c-0/new_device\""
+alias new_device1="adb shell \"echo bos0614 0x2c > /sys/bus/i2c/devices/i2c-1/new_device\""
+alias new_device2="adb shell \"echo bos0614 0x2c > /sys/bus/i2c/devices/i2c-2/new_device\""
+alias del_device="adb shell \"echo bos0614 0x2c > /sys/bus/i2c/devices/i2c-0/delete_device\""
+alias del_device1="adb shell \"echo bos0614 0x2c > /sys/bus/i2c/devices/i2c-1/delete_device\""
+alias del_device2="adb shell \"echo bos0614 0x2c > /sys/bus/i2c/devices/i2c-2/delete_device\""
+alias status="adb shell \"cat /sys/bus/i2c/devices/1-002c/ic_errors\""
+alias pressSensing="adb shell \"echo 0 0 0 4000 1200 4 > /sys/bus/i2c/devices/1-002c/sensing_config\""
+alias pressAutoplay="adb shell \"echo 0 0 0 > /sys/bus/i2c/devices/1-002c/sensing_autoplay\""
+alias releaseSensing="adb shell \"echo 0 1 1 8000 -11 32 > /sys/bus/i2c/devices/1-002c/sensing_config\""
+alias releaseAutoplay="adb shell \"echo 0 1 1 > /sys/bus/i2c/devices/1-002c/sensing_autoplay\""
+alias pressStop="adb shell \"echo 0 0 > /sys/bus/i2c/devices/1-002c/sensing_stop\""
+alias releaseStop="adb shell \"echo 0 1 > /sys/bus/i2c/devices/1-002c/sensing_stop\""
+alias log="adb shell dmesg -T -w"
+alias sliceA="adb shell \"echo 0 60000 175000 2 1 > /sys/bus/i2c/devices/1-002c/set_slice\""
+alias sliceStabA="adb shell \"echo 1 00000 250000 2 1 > /sys/bus/i2c/devices/1-002c/set_slice\""
+alias waveformA="adb shell \"echo 0 0 2 1 1 > /sys/bus/i2c/devices/1-002c/set_waveform\""
+alias sliceB="adb shell \"echo 2 60000 175000 2 1 > /sys/bus/i2c/devices/1-002c/set_slice\""
+alias sliceStabB="adb shell \"echo 3 00000 250000 11 1 > /sys/bus/i2c/devices/1-002c/set_slice\""
+alias waveformB="adb shell \"echo 1 2 2 1 1 > /sys/bus/i2c/devices/1-002c/set_waveform\""
+alias sensingOn="sliceA && sliceStabA &&waveformA && sliceB && sliceStabB && waveformB && pressSensing && pressAutoplay && releaseSensing && releaseAutoplay"
+alias sensingOff="pressStop && releaseStop"
+alias play="adb shell \"echo 0 0 > /sys/bus/i2c/devices/1-002c/synth_play\""
+alias output_on="adb shell \"echo 1 > /sys/bus/i2c/devices/1-002c/ctrl_output\""
+alias output_off="adb shell \"echo 0 > /sys/bus/i2c/devices/1-002c/ctrl_output\""
+alias demoWave="sliceA && waveform && play && output_on"
+alias refresh="(push & rmmod) && load"
+alias test="build && refresh"

drivers/input/misc/bos0614_mmi/i2cLinux.c

@@ -0,0 +1,183 @@
+//
+// Description: I2C Adapter for Boreas Haptic Driver on Linux Kernel
+//
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#include <i2cLinux.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+
+typedef struct
+{
+    I2c driver;
+    struct i2c_client *client;
+} Context;
+
+static void initDriverFct(Context *ctx);
+
+#define NBR_CHAR_PER_BYTE (5)
+#define ESCAPE_CHAR (1)
+
+static void logBuffer(const char *message, const void *data, size_t length)
+{
+    size_t bufferLength = length * NBR_CHAR_PER_BYTE + ESCAPE_CHAR;
+    char *buf = kzalloc(bufferLength, GFP_KERNEL);
+
+    if (buf != NULL)
+    {
+        char *ptr = buf;
+        char *end = buf + bufferLength;
+
+        uint8_t *_data = (uint8_t *) data;
+
+        for (size_t index = 0; index < length && ptr < end; index++)
+        {
+            ptr += sprintf(ptr, index < (length - 1) ? "0x%02x " : "0x%02x", _data[index]);
+        }
+
+        printk("%s length: %d [%s]\n", message, length, buf, bufferLength, ptr, end);
+
+        kfree(buf);
+    }
+
+}
+
+
+/*
+ * Private Section
+ */
+
+static int32_t i2cKernelSend(I2c *i2c, uint8_t address, const void *data, size_t num)
+{
+    int32_t res = -EIO;
+
+    if (i2c != NULL && data != NULL)
+    {
+        Context *ctx = container_of(i2c, Context, driver);
+
+        dev_dbg(&ctx->client->dev, "I2C Write Address: 0x%x\n", address);
+
+        logBuffer("Write: ", data, num);
+
+        char *buf = kzalloc(num, GFP_KERNEL);
+
+        if (buf != NULL)
+        {
+            memcpy(buf, data, num);
+            int status = i2c_master_send(ctx->client, (const char *) buf, (int) num);
+            res = status == num ? ARM_DRIVER_OK : status;
+
+            kfree(buf);
+        }
+    }
+
+    return res;
+}
+
+int32_t i2cKernelRead(I2c *i2c, uint8_t address, void *data, size_t num)
+{
+    int32_t res = -EIO;
+
+    if (i2c != NULL && data != NULL)
+    {
+        Context *ctx = container_of(i2c, Context, driver);
+
+        dev_dbg(&ctx->client->dev, "I2C Read Address: 0x%x \n", address);
+
+        char *buf = kzalloc(num, GFP_KERNEL);
+
+        if (buf != NULL)
+        {
+            int status = i2c_master_recv(ctx->client, (char *) buf, num);
+
+            res = status == num ? 0 : status;
+
+            if (res == ARM_DRIVER_OK)
+            {
+                memcpy(data, buf, num);
+                logBuffer("Read: ", data, num);
+            }
+
+            kfree(buf);
+        }
+
+
+    }
+
+    return res;
+}
+
+/*
+ * Public Section
+ */
+
+I2c *i2cBoreasLinuxInit(struct i2c_client *client)
+{
+    I2c *driver = NULL;
+
+    if (client != NULL)
+    {
+        Context *ctx = kzalloc(sizeof(Context), GFP_KERNEL);
+
+        printk("[PF-Debug] I2C Client 0x%8x", client);
+
+        if (ctx != NULL)
+        {
+            ctx->client = client;
+            initDriverFct(ctx);
+            driver = &ctx->driver;
+        }
+    }
+
+    return driver;
+}
+
+bool i2cBoreasLinuxFree(I2c *i2c)
+{
+    bool res = false;
+
+    if (i2c != NULL)
+    {
+        Context *ctx = container_of(i2c, Context, driver);
+
+        dev_info(&ctx->client->dev, "I2C Linux Wrapper Free\n");
+
+        kfree(ctx);
+
+        res = true;
+    }
+
+    return res;
+}
+
+/*
+ * Private Section
+ */
+
+void initDriverFct(Context *ctx)
+{
+    ctx->driver.write = i2cKernelSend;
+    ctx->driver.read = i2cKernelRead;
+}

drivers/input/misc/bos0614_mmi/i2cLinux.h

@@ -0,0 +1,35 @@
+//
+// Description: Boréas I2C Wrapper for Linux Implementation
+//
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#ifndef BOREAS_HAPTIC_DRIVER_LINUX_I2CLINUX_H
+#define BOREAS_HAPTIC_DRIVER_LINUX_I2CLINUX_H
+
+#include "libs/dk-core/src/bsp/drivers/i2c/i2c.h"
+#include <linux/i2c.h>
+
+I2c *i2cBoreasLinuxInit(struct i2c_client *client);
+
+bool i2cBoreasLinuxFree(I2c * i2c);
+
+#endif //BOREAS_HAPTIC_DRIVER_LINUX_I2CLINUX_H

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitattributes

@@ -0,0 +1,21 @@
+# Set the default behavior, in case people don't have core.autocrlf set.
+* text=auto
+# Explicitly declare text files you want to always be normalized and converted
+# to native line endings on checkout.
+*.c text
+*.h text
+*.txt text
+*.xsd text
+*.pdsc text
+*.svd text
+*.bat text
+# Declare files that will always have CRLF line endings on checkout.
+*.uvproj text eol=crlf
+*.uvproj text eol=crlf
+# Denote all files that are truly binary and should not be modified.
+*.png binary
+*.jpg binary
+*.a filter=lfs diff=lfs merge=lfs -text
+*.lib filter=lfs diff=lfs merge=lfs -text
+*.exe filter=lfs diff=lfs merge=lfs -text
+CMSIS/Utilities/Linux-gcc-*/* filter=lfs diff=lfs merge=lfs -text

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/.gitignore

@@ -0,0 +1,10 @@
+*.breadcrumb
+*.junit
+**/__pycache__
+Local_Release/
+CMSIS/Documentation/
+CMSIS/RTOS2/RTX/Library/ARM/MDK/RTX_CM.uvguix.*
+CMSIS/CoreValidation/Tests/build
+CMSIS/CoreValidation/Tests/bootloader/build
+*.uvguix.*
+*.uvmpw.uvgui.*

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_CAN.h

@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2015-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        13. Sept 2017
+ * $Revision:    V1.2
+ *
+ * Project:      CAN (Controller Area Network) Driver definitions
+ */
+
+/* History:
+ *  Version 1.2
+ *    Added ARM_CAN_UNIT_STATE_BUS_OFF unit state and
+ *    ARM_CAN_EVENT_UNIT_INACTIVE unit event
+ *  Version 1.1
+ *    ARM_CAN_STATUS made volatile
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_CAN_H_
+#define DRIVER_CAN_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2)  /* API version */
+
+
+/****** CAN Bitrate selection codes *****/
+typedef enum _ARM_CAN_BITRATE_SELECT {
+  ARM_CAN_BITRATE_NOMINAL,              ///< Select nominal (flexible data-rate arbitration) bitrate
+  ARM_CAN_BITRATE_FD_DATA               ///< Select flexible data-rate data bitrate
+} ARM_CAN_BITRATE_SELECT;
+
+/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/
+#define ARM_CAN_BIT_PROP_SEG_Pos        0UL       ///< bits 7..0
+#define ARM_CAN_BIT_PROP_SEG_Msk       (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos)
+#define ARM_CAN_BIT_PROP_SEG(x)      (((x)     << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk)
+
+/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/
+#define ARM_CAN_BIT_PHASE_SEG1_Pos      8UL       ///< bits 15..8
+#define ARM_CAN_BIT_PHASE_SEG1_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos)
+#define ARM_CAN_BIT_PHASE_SEG1(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk)
+
+/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/
+#define ARM_CAN_BIT_PHASE_SEG2_Pos      16UL      ///< bits 23..16
+#define ARM_CAN_BIT_PHASE_SEG2_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos)
+#define ARM_CAN_BIT_PHASE_SEG2(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk)
+
+/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/
+#define ARM_CAN_BIT_SJW_Pos             24UL      ///< bits 28..24
+#define ARM_CAN_BIT_SJW_Msk            (0x1FUL << ARM_CAN_BIT_SJW_Pos)
+#define ARM_CAN_BIT_SJW(x)           (((x)     << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk)
+
+/****** CAN Mode codes *****/
+typedef enum _ARM_CAN_MODE {
+  ARM_CAN_MODE_INITIALIZATION,          ///< Initialization mode
+  ARM_CAN_MODE_NORMAL,                  ///< Normal operation mode
+  ARM_CAN_MODE_RESTRICTED,              ///< Restricted operation mode
+  ARM_CAN_MODE_MONITOR,                 ///< Bus monitoring mode
+  ARM_CAN_MODE_LOOPBACK_INTERNAL,       ///< Loopback internal mode
+  ARM_CAN_MODE_LOOPBACK_EXTERNAL        ///< Loopback external mode
+} ARM_CAN_MODE;
+
+/****** CAN Filter Operation codes *****/
+typedef enum _ARM_CAN_FILTER_OPERATION {
+  ARM_CAN_FILTER_ID_EXACT_ADD,          ///< Add    exact id filter
+  ARM_CAN_FILTER_ID_EXACT_REMOVE,       ///< Remove exact id filter
+  ARM_CAN_FILTER_ID_RANGE_ADD,          ///< Add    range id filter
+  ARM_CAN_FILTER_ID_RANGE_REMOVE,       ///< Remove range id filter
+  ARM_CAN_FILTER_ID_MASKABLE_ADD,       ///< Add    maskable id filter
+  ARM_CAN_FILTER_ID_MASKABLE_REMOVE     ///< Remove maskable id filter
+} ARM_CAN_FILTER_OPERATION;
+
+/****** CAN Object Configuration codes *****/
+typedef enum _ARM_CAN_OBJ_CONFIG {
+  ARM_CAN_OBJ_INACTIVE,                 ///< CAN object inactive
+  ARM_CAN_OBJ_TX,                       ///< CAN transmit object
+  ARM_CAN_OBJ_RX,                       ///< CAN receive object
+  ARM_CAN_OBJ_RX_RTR_TX_DATA,           ///< CAN object that on RTR reception automatically transmits Data Frame
+  ARM_CAN_OBJ_TX_RTR_RX_DATA            ///< CAN object that transmits RTR and automatically receives Data Frame
+} ARM_CAN_OBJ_CONFIG;
+
+/**
+\brief CAN Object Capabilities
+*/
+typedef struct _ARM_CAN_OBJ_CAPABILITIES {
+  uint32_t tx               : 1;        ///< Object supports transmission
+  uint32_t rx               : 1;        ///< Object supports reception
+  uint32_t rx_rtr_tx_data   : 1;        ///< Object supports RTR reception and automatic Data Frame transmission
+  uint32_t tx_rtr_rx_data   : 1;        ///< Object supports RTR transmission and automatic Data Frame reception
+  uint32_t multiple_filters : 1;        ///< Object allows assignment of multiple filters to it
+  uint32_t exact_filtering  : 1;        ///< Object supports exact identifier filtering
+  uint32_t range_filtering  : 1;        ///< Object supports range identifier filtering
+  uint32_t mask_filtering   : 1;        ///< Object supports mask identifier filtering
+  uint32_t message_depth    : 8;        ///< Number of messages buffers (FIFO) for that object
+  uint32_t reserved         : 16;       ///< Reserved (must be zero)
+} ARM_CAN_OBJ_CAPABILITIES;
+
+/****** CAN Control Function Operation codes *****/
+#define ARM_CAN_CONTROL_Pos             0UL
+#define ARM_CAN_CONTROL_Msk            (0xFFUL << ARM_CAN_CONTROL_Pos)
+#define ARM_CAN_SET_FD_MODE            (1UL    << ARM_CAN_CONTROL_Pos)          ///< Set FD operation mode;                   arg: 0 = disable, 1 = enable
+#define ARM_CAN_ABORT_MESSAGE_SEND     (2UL    << ARM_CAN_CONTROL_Pos)          ///< Abort sending of CAN message;            arg = object
+#define ARM_CAN_CONTROL_RETRANSMISSION (3UL    << ARM_CAN_CONTROL_Pos)          ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state)
+#define ARM_CAN_SET_TRANSCEIVER_DELAY  (4UL    << ARM_CAN_CONTROL_Pos)          ///< Set transceiver delay;                   arg = delay in time quanta
+
+/****** CAN ID Frame Format codes *****/
+#define ARM_CAN_ID_IDE_Pos              31UL
+#define ARM_CAN_ID_IDE_Msk             (1UL    << ARM_CAN_ID_IDE_Pos)
+
+/****** CAN Identifier encoding *****/
+#define ARM_CAN_STANDARD_ID(id)        (id & 0x000007FFUL)                      ///< CAN identifier in standard format (11-bits)
+#define ARM_CAN_EXTENDED_ID(id)       ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits)
+
+/**
+\brief CAN Message Information
+*/
+typedef struct _ARM_CAN_MSG_INFO {
+  uint32_t id;                          ///< CAN identifier with frame format specifier (bit 31)
+  uint32_t rtr              : 1;        ///< Remote transmission request frame
+  uint32_t edl              : 1;        ///< Flexible data-rate format extended data length
+  uint32_t brs              : 1;        ///< Flexible data-rate format with bitrate switch 
+  uint32_t esi              : 1;        ///< Flexible data-rate format error state indicator
+  uint32_t dlc              : 4;        ///< Data length code
+  uint32_t reserved         : 24;
+} ARM_CAN_MSG_INFO;
+
+/****** CAN specific error code *****/
+#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1)          ///< Bitrate selection not supported
+#define ARM_CAN_INVALID_BITRATE        (ARM_DRIVER_ERROR_SPECIFIC - 2)          ///< Requested bitrate not supported
+#define ARM_CAN_INVALID_BIT_PROP_SEG   (ARM_DRIVER_ERROR_SPECIFIC - 3)          ///< Propagation segment value not supported
+#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4)          ///< Phase segment 1 value not supported
+#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5)          ///< Phase segment 2 value not supported
+#define ARM_CAN_INVALID_BIT_SJW        (ARM_DRIVER_ERROR_SPECIFIC - 6)          ///< SJW value not supported
+#define ARM_CAN_NO_MESSAGE_AVAILABLE   (ARM_DRIVER_ERROR_SPECIFIC - 7)          ///< Message is not available
+
+/****** CAN Status codes *****/
+#define ARM_CAN_UNIT_STATE_INACTIVE    (0U)             ///< Unit state: Not active on bus (initialization)
+#define ARM_CAN_UNIT_STATE_ACTIVE      (1U)             ///< Unit state: Active on bus (can generate active error frame)
+#define ARM_CAN_UNIT_STATE_PASSIVE     (2U)             ///< Unit state: Error passive (can not generate active error frame)
+#define ARM_CAN_UNIT_STATE_BUS_OFF     (3U)             ///< Unit state: Bus-off (can recover to active state)
+#define ARM_CAN_LEC_NO_ERROR           (0U)             ///< Last error code: No error
+#define ARM_CAN_LEC_BIT_ERROR          (1U)             ///< Last error code: Bit error
+#define ARM_CAN_LEC_STUFF_ERROR        (2U)             ///< Last error code: Bit stuffing error
+#define ARM_CAN_LEC_CRC_ERROR          (3U)             ///< Last error code: CRC error
+#define ARM_CAN_LEC_FORM_ERROR         (4U)             ///< Last error code: Illegal fixed-form bit
+#define ARM_CAN_LEC_ACK_ERROR          (5U)             ///< Last error code: Acknowledgment error
+
+/**
+\brief CAN Status
+*/
+typedef volatile struct _ARM_CAN_STATUS {
+  uint32_t unit_state       : 4;        ///< Unit bus state
+  uint32_t last_error_code  : 4;        ///< Last error code
+  uint32_t tx_error_count   : 8;        ///< Transmitter error count
+  uint32_t rx_error_count   : 8;        ///< Receiver error count
+  uint32_t reserved         : 8;
+} ARM_CAN_STATUS;
+
+
+/****** CAN Unit Event *****/
+#define ARM_CAN_EVENT_UNIT_INACTIVE    (0U)             ///< Unit entered Inactive state
+#define ARM_CAN_EVENT_UNIT_ACTIVE      (1U)             ///< Unit entered Error Active state
+#define ARM_CAN_EVENT_UNIT_WARNING     (2U)             ///< Unit entered Error Warning state (one or both error counters >= 96)
+#define ARM_CAN_EVENT_UNIT_PASSIVE     (3U)             ///< Unit entered Error Passive state
+#define ARM_CAN_EVENT_UNIT_BUS_OFF     (4U)             ///< Unit entered Bus-off state
+
+/****** CAN Send/Receive Event *****/
+#define ARM_CAN_EVENT_SEND_COMPLETE    (1UL << 0)       ///< Send complete
+#define ARM_CAN_EVENT_RECEIVE          (1UL << 1)       ///< Message received
+#define ARM_CAN_EVENT_RECEIVE_OVERRUN  (1UL << 2)       ///< Received message overrun
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_CAN_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_CAN_CAPABILITIES
+
+  \fn          int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,
+                                           ARM_CAN_SignalObjectEvent_t cb_object_event)
+  \brief       Initialize CAN interface and register signal (callback) functions.
+  \param[in]   cb_unit_event   Pointer to \ref ARM_CAN_SignalUnitEvent callback function
+  \param[in]   cb_object_event Pointer to \ref ARM_CAN_SignalObjectEvent callback function
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_Uninitialize (void)
+  \brief       De-initialize CAN interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state)
+  \brief       Control CAN interface power.
+  \param[in]   state  Power state
+                 - \ref ARM_POWER_OFF :  power off: no operation possible
+                 - \ref ARM_POWER_LOW :  low power mode: retain state, detect and signal wake-up events
+                 - \ref ARM_POWER_FULL : power on: full operation at maximum performance
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_CAN_GetClock (void)
+  \brief       Retrieve CAN base clock frequency.
+  \return      base clock frequency
+
+  \fn          int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments)
+  \brief       Set bitrate for CAN interface.
+  \param[in]   select       Bitrate selection
+                 - \ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate
+                 - \ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate
+  \param[in]   bitrate      Bitrate
+  \param[in]   bit_segments Bit segments settings
+                 - \ref ARM_CAN_BIT_PROP_SEG(x) :   number of time quanta for propagation time segment
+                 - \ref ARM_CAN_BIT_PHASE_SEG1(x) : number of time quanta for phase buffer segment 1
+                 - \ref ARM_CAN_BIT_PHASE_SEG2(x) : number of time quanta for phase buffer Segment 2
+                 - \ref ARM_CAN_BIT_SJW(x) :        number of time quanta for (re-)synchronization jump width
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode)
+  \brief       Set operating mode for CAN interface.
+  \param[in]   mode   Operating mode
+                 - \ref ARM_CAN_MODE_INITIALIZATION :    initialization mode
+                 - \ref ARM_CAN_MODE_NORMAL :            normal operation mode
+                 - \ref ARM_CAN_MODE_RESTRICTED :        restricted operation mode
+                 - \ref ARM_CAN_MODE_MONITOR :           bus monitoring mode
+                 - \ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode
+                 - \ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode
+  \return      \ref execution_status
+
+  \fn          ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx)
+  \brief       Retrieve capabilities of an object.
+  \param[in]   obj_idx  Object index
+  \return      \ref ARM_CAN_OBJ_CAPABILITIES
+
+  \fn          int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg)
+  \brief       Add or remove filter for message reception.
+  \param[in]   obj_idx      Object index of object that filter should be or is assigned to
+  \param[in]   operation    Operation on filter
+                 - \ref ARM_CAN_FILTER_ID_EXACT_ADD :       add    exact id filter
+                 - \ref ARM_CAN_FILTER_ID_EXACT_REMOVE :    remove exact id filter
+                 - \ref ARM_CAN_FILTER_ID_RANGE_ADD :       add    range id filter
+                 - \ref ARM_CAN_FILTER_ID_RANGE_REMOVE :    remove range id filter
+                 - \ref ARM_CAN_FILTER_ID_MASKABLE_ADD :    add    maskable id filter
+                 - \ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter
+  \param[in]   id           ID or start of ID range (depending on filter type)
+  \param[in]   arg          Mask or end of ID range (depending on filter type)
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg)
+  \brief       Configure object.
+  \param[in]   obj_idx  Object index
+  \param[in]   obj_cfg  Object configuration state
+                 - \ref ARM_CAN_OBJ_INACTIVE :       deactivate object
+                 - \ref ARM_CAN_OBJ_RX :             configure object for reception
+                 - \ref ARM_CAN_OBJ_TX :             configure object for transmission
+                 - \ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame
+                 - \ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size)
+  \brief       Send message on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[in]   msg_info Pointer to CAN message information
+  \param[in]   data     Pointer to data buffer
+  \param[in]   size     Number of data bytes to send
+  \return      value >= 0  number of data bytes accepted to send
+  \return      value < 0   \ref execution_status
+
+  \fn          int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size)
+  \brief       Read message received on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[out]  msg_info Pointer to read CAN message information
+  \param[out]  data     Pointer to data buffer for read data
+  \param[in]   size     Maximum number of data bytes to read
+  \return      value >= 0  number of data bytes read
+  \return      value < 0   \ref execution_status
+
+  \fn          int32_t ARM_CAN_Control (uint32_t control, uint32_t arg)
+  \brief       Control CAN interface.
+  \param[in]   control  Operation
+                 - \ref ARM_CAN_SET_FD_MODE :            set FD operation mode
+                 - \ref ARM_CAN_ABORT_MESSAGE_SEND :     abort sending of CAN message
+                 - \ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission
+                 - \ref ARM_CAN_SET_TRANSCEIVER_DELAY :  set transceiver delay
+  \param[in]   arg      Argument of operation
+  \return      \ref execution_status
+
+  \fn          ARM_CAN_STATUS ARM_CAN_GetStatus (void)
+  \brief       Get CAN status.
+  \return      CAN status \ref ARM_CAN_STATUS
+
+  \fn          void ARM_CAN_SignalUnitEvent (uint32_t event)
+  \brief       Signal CAN unit event.
+  \param[in]   event \ref CAN_unit_events
+  \return      none
+
+  \fn          void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event)
+  \brief       Signal CAN object event.
+  \param[in]   obj_idx  Object index
+  \param[in]   event \ref CAN_events
+  \return      none
+*/
+
+typedef void (*ARM_CAN_SignalUnitEvent_t)   (uint32_t event);                   ///< Pointer to \ref ARM_CAN_SignalUnitEvent   : Signal CAN Unit Event.
+typedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event.
+
+
+/**
+\brief CAN Device Driver Capabilities.
+*/
+typedef struct _ARM_CAN_CAPABILITIES {
+  uint32_t num_objects            : 8;  ///< Number of \ref can_objects available
+  uint32_t reentrant_operation    : 1;  ///< Support for reentrant calls to \ref ARM_CAN_MessageSend, \ref ARM_CAN_MessageRead, \ref ARM_CAN_ObjectConfigure and abort message sending used by \ref ARM_CAN_Control
+  uint32_t fd_mode                : 1;  ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \ref ARM_CAN_Control)
+  uint32_t restricted_mode        : 1;  ///< Support for restricted operation mode (set by \ref ARM_CAN_SetMode)
+  uint32_t monitor_mode           : 1;  ///< Support for bus monitoring mode (set by \ref ARM_CAN_SetMode)
+  uint32_t internal_loopback      : 1;  ///< Support for internal loopback mode (set by \ref ARM_CAN_SetMode)
+  uint32_t external_loopback      : 1;  ///< Support for external loopback mode (set by \ref ARM_CAN_SetMode)
+  uint32_t reserved               : 18; ///< Reserved (must be zero)
+} ARM_CAN_CAPABILITIES;
+
+
+/**
+\brief Access structure of the CAN Driver.
+*/
+typedef struct _ARM_DRIVER_CAN {
+  ARM_DRIVER_VERSION       (*GetVersion)            (void);                             ///< Pointer to \ref ARM_CAN_GetVersion            : Get driver version.
+  ARM_CAN_CAPABILITIES     (*GetCapabilities)       (void);                             ///< Pointer to \ref ARM_CAN_GetCapabilities       : Get driver capabilities.
+  int32_t                  (*Initialize)            (ARM_CAN_SignalUnitEvent_t   cb_unit_event,                     
+                                                     ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \ref ARM_CAN_Initialize : Initialize CAN interface.
+  int32_t                  (*Uninitialize)          (void);                             ///< Pointer to \ref ARM_CAN_Uninitialize          : De-initialize CAN interface.
+  int32_t                  (*PowerControl)          (ARM_POWER_STATE          state);   ///< Pointer to \ref ARM_CAN_PowerControl          : Control CAN interface power.
+  uint32_t                 (*GetClock)              (void);                             ///< Pointer to \ref ARM_CAN_GetClock              : Retrieve CAN base clock frequency.
+  int32_t                  (*SetBitrate)            (ARM_CAN_BITRATE_SELECT   select,
+                                                     uint32_t                 bitrate,
+                                                     uint32_t                 bit_segments);       ///< Pointer to \ref ARM_CAN_SetBitrate : Set bitrate for CAN interface.
+  int32_t                  (*SetMode)               (ARM_CAN_MODE             mode);    ///< Pointer to \ref ARM_CAN_SetMode               : Set operating mode for CAN interface.
+  ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t                 obj_idx); ///< Pointer to \ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object.
+  int32_t                  (*ObjectSetFilter)       (uint32_t                 obj_idx,
+                                                     ARM_CAN_FILTER_OPERATION operation,
+                                                     uint32_t                 id,
+                                                     uint32_t                 arg);     ///< Pointer to \ref ARM_CAN_ObjectSetFilter       : Add or remove filter for message reception.
+  int32_t                  (*ObjectConfigure)       (uint32_t                 obj_idx,
+                                                     ARM_CAN_OBJ_CONFIG       obj_cfg); ///< Pointer to \ref ARM_CAN_ObjectConfigure       : Configure object.
+  int32_t                  (*MessageSend)           (uint32_t                 obj_idx,
+                                                     ARM_CAN_MSG_INFO        *msg_info,
+                                                     const uint8_t           *data,
+                                                     uint8_t                  size);    ///< Pointer to \ref ARM_CAN_MessageSend           : Send message on CAN bus.
+  int32_t                  (*MessageRead)           (uint32_t                 obj_idx,
+                                                     ARM_CAN_MSG_INFO        *msg_info,
+                                                     uint8_t                 *data,
+                                                     uint8_t                  size);    ///< Pointer to \ref ARM_CAN_MessageRead           : Read message received on CAN bus.
+  int32_t                  (*Control)               (uint32_t                 control,
+                                                     uint32_t                 arg);     ///< Pointer to \ref ARM_CAN_Control               : Control CAN interface.
+  ARM_CAN_STATUS           (*GetStatus)             (void);                             ///< Pointer to \ref ARM_CAN_GetStatus             : Get CAN status.
+} const ARM_DRIVER_CAN;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_CAN_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_Common.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.0
+ *
+ * Project:      Common Driver definitions
+ */
+
+/* History:
+ *  Version 2.0
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Added General return codes definitions
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_COMMON_H_
+#define DRIVER_COMMON_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+  uint16_t api;                         ///< API version
+  uint16_t drv;                         ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK                 0 ///< Operation succeeded 
+#define ARM_DRIVER_ERROR             -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors 
+
+/**
+\brief General power states
+*/ 
+typedef enum _ARM_POWER_STATE {
+  ARM_POWER_OFF,                        ///< Power off: no operation possible
+  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* DRIVER_COMMON_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_ETH.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.1
+ *
+ * Project:      Ethernet PHY and MAC Driver common definitions
+ */
+
+/* History:
+ *  Version 2.1
+ *    ARM_ETH_LINK_INFO made volatile
+ *  Version 2.0
+ *    Removed ARM_ETH_STATUS enumerator
+ *    Removed ARM_ETH_MODE enumerator
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_H_
+#define DRIVER_ETH_H_
+
+#include "Driver_Common.h"
+
+/**
+\brief Ethernet Media Interface type
+*/
+#define ARM_ETH_INTERFACE_MII           (0)     ///< Media Independent Interface (MII)
+#define ARM_ETH_INTERFACE_RMII          (1)     ///< Reduced Media Independent Interface (RMII)
+#define ARM_ETH_INTERFACE_SMII          (2)     ///< Serial Media Independent Interface (SMII)
+
+/**
+\brief Ethernet link speed
+*/
+#define ARM_ETH_SPEED_10M               (0)     ///< 10 Mbps link speed
+#define ARM_ETH_SPEED_100M              (1)     ///< 100 Mbps link speed
+#define ARM_ETH_SPEED_1G                (2)     ///< 1 Gpbs link speed
+
+/**
+\brief Ethernet duplex mode
+*/
+#define ARM_ETH_DUPLEX_HALF             (0)     ///< Half duplex link
+#define ARM_ETH_DUPLEX_FULL             (1)     ///< Full duplex link
+
+/**
+\brief Ethernet link state
+*/
+typedef enum _ARM_ETH_LINK_STATE {
+  ARM_ETH_LINK_DOWN,                    ///< Link is down
+  ARM_ETH_LINK_UP                       ///< Link is up
+} ARM_ETH_LINK_STATE;
+
+/**
+\brief Ethernet link information
+*/
+typedef volatile struct _ARM_ETH_LINK_INFO {
+  uint32_t speed    : 2;                ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
+  uint32_t duplex   : 1;                ///< Duplex mode: 0= Half, 1= Full
+  uint32_t reserved : 29;
+} ARM_ETH_LINK_INFO;
+
+/**
+\brief Ethernet MAC Address
+*/
+typedef struct _ARM_ETH_MAC_ADDR {
+  uint8_t b[6];                         ///< MAC Address (6 bytes), MSB first
+} ARM_ETH_MAC_ADDR;
+
+#endif /* DRIVER_ETH_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_ETH_MAC.h

@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.1
+ *
+ * Project:      Ethernet MAC (Media Access Control) Driver definitions
+ */
+
+/* History:
+ *  Version 2.1
+ *    Added ARM_ETH_MAC_SLEEP Control
+ *  Version 2.0
+ *    Changed MAC Address handling:
+ *      moved from ARM_ETH_MAC_Initialize
+ *      to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress
+ *    Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter
+ *    Extended ARM_ETH_MAC_SendFrame function with flags
+ *    Added ARM_ETH_MAC_Control function:
+ *      more control options (Broadcast, Multicast, Checksum offload, VLAN, ...)
+ *      replaces ARM_ETH_MAC_SetMode
+ *      replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx
+ *    Added optional event on transmitted frame
+ *    Added support for PTP (Precision Time Protocol) through new functions:
+ *       ARM_ETH_MAC_ControlTimer
+ *       ARM_ETH_MAC_GetRxFrameTime
+ *       ARM_ETH_MAC_GetTxFrameTime
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Name space prefix ARM_ added
+ *  Version 1.01
+ *    Renamed capabilities items for checksum offload
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_MAC_H_
+#define DRIVER_ETH_MAC_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,1)  /* API version */
+
+
+#define _ARM_Driver_ETH_MAC_(n)      Driver_ETH_MAC##n
+#define  ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n)
+
+
+/****** Ethernet MAC Control Codes *****/
+
+#define ARM_ETH_MAC_CONFIGURE           (0x01)      ///< Configure MAC; arg = configuration
+#define ARM_ETH_MAC_CONTROL_TX          (0x02)      ///< Transmitter; arg: 0=disabled (default), 1=enabled
+#define ARM_ETH_MAC_CONTROL_RX          (0x03)      ///< Receiver; arg: 0=disabled (default), 1=enabled
+#define ARM_ETH_MAC_FLUSH               (0x04)      ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_...
+#define ARM_ETH_MAC_SLEEP               (0x05)      ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
+#define ARM_ETH_MAC_VLAN_FILTER         (0x06)      ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)
+
+/*----- Ethernet MAC Configuration -----*/
+#define ARM_ETH_MAC_SPEED_Pos            0
+#define ARM_ETH_MAC_SPEED_Msk           (3UL                 << ARM_ETH_MAC_SPEED_Pos)
+#define ARM_ETH_MAC_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_MAC_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_MAC_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_MAC_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_MAC_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_MAC_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_MAC_DUPLEX_Pos           2
+#define ARM_ETH_MAC_DUPLEX_Msk          (1UL                 << ARM_ETH_MAC_DUPLEX_Pos)
+#define ARM_ETH_MAC_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_MAC_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_MAC_LOOPBACK            (1UL << 4)  ///< Loop-back test mode
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5)  ///< Receiver Checksum offload
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6)  ///< Transmitter Checksum offload
+#define ARM_ETH_MAC_ADDRESS_BROADCAST   (1UL << 7)  ///< Accept frames with Broadcast address
+#define ARM_ETH_MAC_ADDRESS_MULTICAST   (1UL << 8)  ///< Accept frames with any Multicast address
+#define ARM_ETH_MAC_ADDRESS_ALL         (1UL << 9)  ///< Accept frames with any address (Promiscuous Mode)
+
+/*----- Ethernet MAC Flush Flags -----*/
+#define ARM_ETH_MAC_FLUSH_RX            (1UL << 0)  ///< Flush Receive buffer
+#define ARM_ETH_MAC_FLUSH_TX            (1UL << 1)  ///< Flush Transmit buffer
+
+/*----- Ethernet MAC VLAN Filter Flag -----*/
+#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit)
+
+
+/****** Ethernet MAC Frame Transmit Flags *****/
+#define ARM_ETH_MAC_TX_FRAME_FRAGMENT   (1UL << 0)  ///< Indicate frame fragment
+#define ARM_ETH_MAC_TX_FRAME_EVENT      (1UL << 1)  ///< Generate event when frame is transmitted
+#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP  (1UL << 2)  ///< Capture frame time stamp
+
+
+/****** Ethernet MAC Timer Control Codes *****/
+#define ARM_ETH_MAC_TIMER_GET_TIME      (0x01)      ///< Get current time
+#define ARM_ETH_MAC_TIMER_SET_TIME      (0x02)      ///< Set new time
+#define ARM_ETH_MAC_TIMER_INC_TIME      (0x03)      ///< Increment current time
+#define ARM_ETH_MAC_TIMER_DEC_TIME      (0x04)      ///< Decrement current time
+#define ARM_ETH_MAC_TIMER_SET_ALARM     (0x05)      ///< Set alarm time
+#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK  (0x06)      ///< Adjust clock frequency; time->ns: correction factor * 2^31
+
+
+/**
+\brief Ethernet MAC Time
+*/
+typedef struct _ARM_ETH_MAC_TIME {
+  uint32_t ns;                          ///< Nano seconds
+  uint32_t sec;                         ///< Seconds
+} ARM_ETH_MAC_TIME;
+
+
+/****** Ethernet MAC Event *****/
+#define ARM_ETH_MAC_EVENT_RX_FRAME      (1UL << 0)  ///< Frame Received
+#define ARM_ETH_MAC_EVENT_TX_FRAME      (1UL << 1)  ///< Frame Transmitted
+#define ARM_ETH_MAC_EVENT_WAKEUP        (1UL << 2)  ///< Wake-up (on Magic Packet)
+#define ARM_ETH_MAC_EVENT_TIMER_ALARM   (1UL << 3)  ///< Timer Alarm
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_ETH_MAC_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)
+  \brief       Initialize Ethernet MAC Device.
+  \param[in]   cb_event  Pointer to \ref ARM_ETH_MAC_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Uninitialize (void)
+  \brief       De-initialize Ethernet MAC Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet MAC Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Get Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Set Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr,
+                                                           uint32_t          num_addr)
+  \brief       Configure Address Filter.
+  \param[in]   ptr_addr  Pointer to addresses
+  \param[in]   num_addr  Number of addresses to configure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)
+  \brief       Send Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer with data to send
+  \param[in]   len    Frame buffer length in bytes
+  \param[in]   flags  Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)
+  \brief       Read data of received Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer for data to read into
+  \param[in]   len    Frame buffer length in bytes
+  \return      number of data bytes read or execution status
+                 - value >= 0: number of data bytes read
+                 - value < 0: error occurred, value is execution status as defined with \ref execution_status 
+*/
+/**
+  \fn          uint32_t ARM_ETH_MAC_GetRxFrameSize (void)
+  \brief       Get size of received Ethernet frame.
+  \return      number of bytes in received frame
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of received Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of transmitted Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)
+  \brief       Control Ethernet Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)
+  \brief       Control Precision Timer.
+  \param[in]   control  Operation
+  \param[in]   time     Pointer to time structure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+  \brief       Read Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[out]  data      Pointer where the result is written to
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+  \brief       Write Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[in]   data      16-bit data to write
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_ETH_MAC_SignalEvent (uint32_t event)
+  \brief       Callback function that signals a Ethernet Event.
+  \param[in]   event  event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event.
+
+
+/**
+\brief Ethernet MAC Capabilities
+*/
+typedef struct _ARM_ETH_MAC_CAPABILITIES {
+  uint32_t checksum_offload_rx_ip4  : 1;        ///< 1 = IPv4 header checksum verified on receive
+  uint32_t checksum_offload_rx_ip6  : 1;        ///< 1 = IPv6 checksum verification supported on receive
+  uint32_t checksum_offload_rx_udp  : 1;        ///< 1 = UDP payload checksum verified on receive
+  uint32_t checksum_offload_rx_tcp  : 1;        ///< 1 = TCP payload checksum verified on receive
+  uint32_t checksum_offload_rx_icmp : 1;        ///< 1 = ICMP payload checksum verified on receive
+  uint32_t checksum_offload_tx_ip4  : 1;        ///< 1 = IPv4 header checksum generated on transmit
+  uint32_t checksum_offload_tx_ip6  : 1;        ///< 1 = IPv6 checksum generation supported on transmit
+  uint32_t checksum_offload_tx_udp  : 1;        ///< 1 = UDP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_tcp  : 1;        ///< 1 = TCP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_icmp : 1;        ///< 1 = ICMP payload checksum generated on transmit
+  uint32_t media_interface          : 2;        ///< Ethernet Media Interface type
+  uint32_t mac_address              : 1;        ///< 1 = driver provides initial valid MAC address
+  uint32_t event_rx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated
+  uint32_t event_tx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated
+  uint32_t event_wakeup             : 1;        ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated
+  uint32_t precision_timer          : 1;        ///< 1 = Precision Timer supported
+  uint32_t reserved                 : 15;       ///< Reserved (must be zero)
+} ARM_ETH_MAC_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Ethernet MAC Driver
+*/
+typedef struct _ARM_DRIVER_ETH_MAC {
+  ARM_DRIVER_VERSION       (*GetVersion)      (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version.
+  ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities.
+  int32_t                  (*Initialize)      (ARM_ETH_MAC_SignalEvent_t cb_event);                  ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device.
+  int32_t                  (*Uninitialize)    (void);                                                ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device.
+  int32_t                  (*PowerControl)    (ARM_POWER_STATE state);                               ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power.
+  int32_t                  (*GetMacAddress)   (      ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address.
+  int32_t                  (*SetMacAddress)   (const ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address.
+  int32_t                  (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter.
+  int32_t                  (*SendFrame)       (const uint8_t *frame, uint32_t len, uint32_t flags);  ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame.
+  int32_t                  (*ReadFrame)       (      uint8_t *frame, uint32_t len);                  ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame.
+  uint32_t                 (*GetRxFrameSize)  (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame.
+  int32_t                  (*GetRxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame.
+  int32_t                  (*GetTxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame.
+  int32_t                  (*ControlTimer)    (uint32_t control, ARM_ETH_MAC_TIME *time);            ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer.
+  int32_t                  (*Control)         (uint32_t control, uint32_t arg);                      ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface.
+  int32_t                  (*PHY_Read)        (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface.
+  int32_t                  (*PHY_Write)       (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface.
+} const ARM_DRIVER_ETH_MAC;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_ETH_MAC_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_ETH_PHY.h

@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.1
+ *
+ * Project:      Ethernet PHY (Physical Transceiver) Driver definitions
+ */
+
+/* History:
+ *  Version 2.1
+ *    ARM_ETH_LINK_INFO made volatile
+ *  Version 2.0
+ *    changed parameter "mode" in function ARM_ETH_PHY_SetMode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_PHY_H_
+#define DRIVER_ETH_PHY_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,1)  /* API version */
+
+
+#define _ARM_Driver_ETH_PHY_(n)      Driver_ETH_PHY##n
+#define  ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n)
+
+
+/****** Ethernet PHY Mode *****/
+#define ARM_ETH_PHY_SPEED_Pos            0
+#define ARM_ETH_PHY_SPEED_Msk           (3UL                 << ARM_ETH_PHY_SPEED_Pos)
+#define ARM_ETH_PHY_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_PHY_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_PHY_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_PHY_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_PHY_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_PHY_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_PHY_DUPLEX_Pos           2
+#define ARM_ETH_PHY_DUPLEX_Msk          (1UL                 << ARM_ETH_PHY_DUPLEX_Pos)
+#define ARM_ETH_PHY_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_PHY_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_PHY_AUTO_NEGOTIATE      (1UL << 3)                                      ///< Auto Negotiation mode
+#define ARM_ETH_PHY_LOOPBACK            (1UL << 4)                                      ///< Loop-back test mode
+#define ARM_ETH_PHY_ISOLATE             (1UL << 5)                                      ///< Isolate PHY from MII/RMII interface
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t  fn_read,
+                                               ARM_ETH_PHY_Write_t fn_write)
+  \brief       Initialize Ethernet PHY Device.
+  \param[in]   fn_read   Pointer to \ref ARM_ETH_MAC_PHY_Read
+  \param[in]   fn_write  Pointer to \ref ARM_ETH_MAC_PHY_Write
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Uninitialize (void)
+  \brief       De-initialize Ethernet PHY Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet PHY Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetInterface (uint32_t interface)
+  \brief       Set Ethernet Media Interface.
+  \param[in]   interface  Media Interface type
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetMode (uint32_t mode)
+  \brief       Set Ethernet PHY Device Operation mode.
+  \param[in]   mode  Operation Mode
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)
+  \brief       Get Ethernet PHY Device Link state.
+  \return      current link status \ref ARM_ETH_LINK_STATE
+*/
+/**
+  \fn          ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)
+  \brief       Get Ethernet PHY Device Link information.
+  \return      current link parameters \ref ARM_ETH_LINK_INFO
+*/
+
+
+typedef int32_t (*ARM_ETH_PHY_Read_t)  (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register.
+typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register.
+
+
+/**
+\brief Access structure of the Ethernet PHY Driver
+*/
+typedef struct _ARM_DRIVER_ETH_PHY {
+  ARM_DRIVER_VERSION (*GetVersion)   (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version.
+  int32_t            (*Initialize)   (ARM_ETH_PHY_Read_t  fn_read,
+                                      ARM_ETH_PHY_Write_t fn_write);  ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device.
+  int32_t            (*Uninitialize) (void);                          ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device.
+  int32_t            (*PowerControl) (ARM_POWER_STATE state);         ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power.
+  int32_t            (*SetInterface) (uint32_t interface);            ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface.
+  int32_t            (*SetMode)      (uint32_t mode);                 ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode.
+  ARM_ETH_LINK_STATE (*GetLinkState) (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state.
+  ARM_ETH_LINK_INFO  (*GetLinkInfo)  (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information.
+} const ARM_DRIVER_ETH_PHY;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_ETH_PHY_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_Flash.h

@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        19. Apr 2018
+ * $Revision:    V2.2
+ *
+ * Project:      Flash Driver definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    Padding bytes added to ARM_FLASH_INFO
+ *  Version 2.1
+ *    ARM_FLASH_STATUS made volatile
+ *  Version 2.0
+ *    Renamed driver NOR -> Flash (more generic)
+ *    Non-blocking operation
+ *    Added Events, Status and Capabilities
+ *    Linked Flash information (GetInfo)
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_FLASH_H_
+#define DRIVER_FLASH_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+#define _ARM_Driver_Flash_(n)      Driver_Flash##n
+#define  ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n)
+
+
+#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 }
+
+/**
+\brief Flash Sector information
+*/
+typedef struct _ARM_FLASH_SECTOR {
+  uint32_t start;                       ///< Sector Start address
+  uint32_t end;                         ///< Sector End address (start+size-1)
+} const ARM_FLASH_SECTOR;
+
+/**
+\brief Flash information
+*/
+typedef struct _ARM_FLASH_INFO {
+  ARM_FLASH_SECTOR *sector_info;        ///< Sector layout information (NULL=Uniform sectors)
+  uint32_t          sector_count;       ///< Number of sectors
+  uint32_t          sector_size;        ///< Uniform sector size in bytes (0=sector_info used) 
+  uint32_t          page_size;          ///< Optimal programming page size in bytes
+  uint32_t          program_unit;       ///< Smallest programmable unit in bytes
+  uint8_t           erased_value;       ///< Contents of erased memory (usually 0xFF)
+  uint8_t           reserved[3];        ///< Reserved (must be zero)
+} const ARM_FLASH_INFO;
+
+
+/**
+\brief Flash Status
+*/
+typedef volatile struct _ARM_FLASH_STATUS {
+  uint32_t busy     : 1;                ///< Flash busy flag
+  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)
+  uint32_t reserved : 30;
+} ARM_FLASH_STATUS;
+
+
+/****** Flash Event *****/
+#define ARM_FLASH_EVENT_READY           (1UL << 0)  ///< Flash Ready
+#define ARM_FLASH_EVENT_ERROR           (1UL << 1)  ///< Read/Program/Erase Error
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_FLASH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)
+  \brief       Initialize the Flash Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_Flash_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_Uninitialize (void)
+  \brief       De-initialize the Flash Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)
+  \brief       Control the Flash interface power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)
+  \brief       Read data from Flash.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Flash.
+  \param[in]   cnt   Number of data items to read.
+  \return      number of data items read or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)
+  \brief       Program data to Flash.
+  \param[in]   addr  Data address.
+  \param[in]   data  Pointer to a buffer containing the data to be programmed to Flash.
+  \param[in]   cnt   Number of data items to program.
+  \return      number of data items programmed or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseSector (uint32_t addr)
+  \brief       Erase Flash Sector.
+  \param[in]   addr  Sector address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseChip (void)
+  \brief       Erase complete Flash.
+               Optional function for faster full chip erase.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_FLASH_STATUS ARM_Flash_GetStatus (void)
+  \brief       Get Flash status.
+  \return      Flash status \ref ARM_FLASH_STATUS
+*/
+/**
+  \fn          ARM_FLASH_INFO * ARM_Flash_GetInfo (void)
+  \brief       Get Flash information.
+  \return      Pointer to Flash information \ref ARM_FLASH_INFO
+*/
+
+/**
+  \fn          void ARM_Flash_SignalEvent (uint32_t event)
+  \brief       Signal Flash event.
+  \param[in]   event  Event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event);    ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event.
+
+
+/**
+\brief Flash Driver Capabilities.
+*/
+typedef struct _ARM_FLASH_CAPABILITIES {
+  uint32_t event_ready  : 1;            ///< Signal Flash Ready event
+  uint32_t data_width   : 2;            ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
+  uint32_t erase_chip   : 1;            ///< Supports EraseChip operation
+  uint32_t reserved     : 28;           ///< Reserved (must be zero)
+} ARM_FLASH_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Flash Driver
+*/
+typedef struct _ARM_DRIVER_FLASH {
+  ARM_DRIVER_VERSION     (*GetVersion)     (void);                                          ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version.
+  ARM_FLASH_CAPABILITIES (*GetCapabilities)(void);                                          ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)     (ARM_Flash_SignalEvent_t cb_event);              ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface.
+  int32_t                (*Uninitialize)   (void);                                          ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface.
+  int32_t                (*PowerControl)   (ARM_POWER_STATE state);                         ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power.
+  int32_t                (*ReadData)       (uint32_t addr,       void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash.
+  int32_t                (*ProgramData)    (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash.
+  int32_t                (*EraseSector)    (uint32_t addr);                                 ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector.
+  int32_t                (*EraseChip)      (void);                                          ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash.
+  ARM_FLASH_STATUS       (*GetStatus)      (void);                                          ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status.
+  ARM_FLASH_INFO *       (*GetInfo)        (void);                                          ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information.
+} const ARM_DRIVER_FLASH;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_FLASH_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_I2C.h

@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.3
+ *
+ * Project:      I2C (Inter-Integrated Circuit) Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    ARM_I2C_STATUS made volatile
+ *  Version 2.2
+ *    Removed function ARM_I2C_MasterTransfer in order to simplify drivers
+ *      and added back parameter "xfer_pending" to functions
+ *      ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *  Version 2.1
+ *    Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending"
+ *      from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *    Added function ARM_I2C_GetDataCount
+ *    Removed flag "address_nack" from ARM_I2C_STATUS
+ *    Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE
+ *      with event ARM_I2C_EVENT_TRANSFER_DONE
+ *    Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE
+ *    Removed parameter "arg" from function ARM_I2C_SignalEvent
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_I2C_H_
+#define DRIVER_I2C_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+/****** I2C Control Codes *****/
+
+#define ARM_I2C_OWN_ADDRESS             (0x01)      ///< Set Own Slave Address; arg = address 
+#define ARM_I2C_BUS_SPEED               (0x02)      ///< Set Bus Speed; arg = speed
+#define ARM_I2C_BUS_CLEAR               (0x03)      ///< Execute Bus clear: send nine clock pulses
+#define ARM_I2C_ABORT_TRANSFER          (0x04)      ///< Abort Master/Slave Transmit/Receive
+
+/*----- I2C Bus Speed -----*/
+#define ARM_I2C_BUS_SPEED_STANDARD      (0x01)      ///< Standard Speed (100kHz)
+#define ARM_I2C_BUS_SPEED_FAST          (0x02)      ///< Fast Speed     (400kHz)
+#define ARM_I2C_BUS_SPEED_FAST_PLUS     (0x03)      ///< Fast+ Speed    (  1MHz)
+#define ARM_I2C_BUS_SPEED_HIGH          (0x04)      ///< High Speed     (3.4MHz)
+
+
+/****** I2C Address Flags *****/
+
+#define ARM_I2C_ADDRESS_10BIT           (0x0400)    ///< 10-bit address flag
+#define ARM_I2C_ADDRESS_GC              (0x8000)    ///< General Call flag
+
+
+/**
+\brief I2C Status
+*/
+typedef volatile struct _ARM_I2C_STATUS {
+  uint32_t busy             : 1;        ///< Busy flag
+  uint32_t mode             : 1;        ///< Mode: 0=Slave, 1=Master
+  uint32_t direction        : 1;        ///< Direction: 0=Transmitter, 1=Receiver
+  uint32_t general_call     : 1;        ///< General Call indication (cleared on start of next Slave operation)
+  uint32_t arbitration_lost : 1;        ///< Master lost arbitration (cleared on start of next Master operation)
+  uint32_t bus_error        : 1;        ///< Bus error detected (cleared on start of next Master/Slave operation)
+  uint32_t reserved         : 26;
+} ARM_I2C_STATUS;
+
+
+/****** I2C Event *****/
+#define ARM_I2C_EVENT_TRANSFER_DONE       (1UL << 0)  ///< Master/Slave Transmit/Receive finished
+#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1)  ///< Master/Slave Transmit/Receive incomplete transfer
+#define ARM_I2C_EVENT_SLAVE_TRANSMIT      (1UL << 2)  ///< Addressed as Slave Transmitter but transmit operation is not set.
+#define ARM_I2C_EVENT_SLAVE_RECEIVE       (1UL << 3)  ///< Addressed as Slave Receiver but receive operation is not set.
+#define ARM_I2C_EVENT_ADDRESS_NACK        (1UL << 4)  ///< Address not acknowledged from Slave
+#define ARM_I2C_EVENT_GENERAL_CALL        (1UL << 5)  ///< Slave addressed with general call address
+#define ARM_I2C_EVENT_ARBITRATION_LOST    (1UL << 6)  ///< Master lost arbitration
+#define ARM_I2C_EVENT_BUS_ERROR           (1UL << 7)  ///< Bus error detected (START/STOP at illegal position)
+#define ARM_I2C_EVENT_BUS_CLEAR           (1UL << 8)  ///< Bus clear finished
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_I2C_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_I2C_CAPABILITIES
+
+  \fn          int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
+  \brief       Initialize I2C Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_I2C_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_Uninitialize (void)
+  \brief       De-initialize I2C Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)
+  \brief       Control I2C Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start transmitting data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[in]   data          Pointer to buffer with data to transmit to I2C Slave
+  \param[in]   num           Number of data bytes to transmit
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start receiving data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[out]  data          Pointer to buffer for data to receive from I2C Slave
+  \param[in]   num           Number of data bytes to receive
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)
+  \brief       Start transmitting data as I2C Slave.
+  \param[in]   data  Pointer to buffer with data to transmit to I2C Master
+  \param[in]   num   Number of data bytes to transmit
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)
+  \brief       Start receiving data as I2C Slave.
+  \param[out]  data  Pointer to buffer for data to receive from I2C Master
+  \param[in]   num   Number of data bytes to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data bytes transferred; -1 when Slave is not addressed by Master
+
+  \fn          int32_t ARM_I2C_Control (uint32_t control, uint32_t arg)
+  \brief       Control I2C Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+
+  \fn          ARM_I2C_STATUS ARM_I2C_GetStatus (void)
+  \brief       Get I2C status.
+  \return      I2C status \ref ARM_I2C_STATUS
+
+  \fn          void ARM_I2C_SignalEvent (uint32_t event)
+  \brief       Signal I2C Events.
+  \param[in]   event  \ref I2C_events notification mask
+*/
+
+typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event.
+
+
+/**
+\brief I2C Driver Capabilities.
+*/
+typedef struct _ARM_I2C_CAPABILITIES {
+  uint32_t address_10_bit : 1;          ///< supports 10-bit addressing
+  uint32_t reserved       : 31;         ///< Reserved (must be zero)
+} ARM_I2C_CAPABILITIES;
+
+
+/**
+\brief Access structure of the I2C Driver.
+*/
+typedef struct _ARM_DRIVER_I2C {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                                                                ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version.
+  ARM_I2C_CAPABILITIES (*GetCapabilities)(void);                                                                ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_I2C_SignalEvent_t cb_event);                                      ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface.
+  int32_t              (*Uninitialize)   (void);                                                                ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);                                               ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power.
+  int32_t              (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master.
+  int32_t              (*MasterReceive)  (uint32_t addr,       uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master.
+  int32_t              (*SlaveTransmit)  (               const uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave.
+  int32_t              (*SlaveReceive)   (                     uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave.
+  int32_t              (*GetDataCount)   (void);                                                                ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg);                                      ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface.
+  ARM_I2C_STATUS       (*GetStatus)      (void);                                                                ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status.
+} const ARM_DRIVER_I2C;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_I2C_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_MCI.h

@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.3
+ *
+ * Project:      MCI (Memory Card Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    ARM_MCI_STATUS made volatile
+ *  Version 2.2
+ *    Added timeout and error flags to ARM_MCI_STATUS
+ *    Added support for controlling optional RST_n pin (eMMC)
+ *    Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK)
+ *    Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT
+ *  Version 2.1
+ *    Decoupled SPI mode from MCI driver
+ *    Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP
+ *  Version 2.0
+ *    Added support for:
+ *      SD UHS-I (Ultra High Speed)
+ *      SD I/O Interrupt
+ *      Read Wait (SD I/O)
+ *      Suspend/Resume (SD I/O)
+ *      MMC Interrupt
+ *      MMC Boot
+ *      Stream Data transfer (MMC)
+ *      VCCQ Power Supply Control (eMMC)
+ *      Command Completion Signal (CCS) for CE-ATA
+ *    Added ARM_MCI_Control function
+ *    Added ARM_MCI_GetStatus function
+ *    Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions
+ *      (replaced by ARM_MCI_Control)
+ *    Changed ARM_MCI_CardPower function (voltage parameter)
+ *    Changed ARM_MCI_SendCommnad function (flags parameter)
+ *    Changed ARM_MCI_SetupTransfer function (mode parameter)
+ *    Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_MCI_H_
+#define DRIVER_MCI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+/****** MCI Send Command Flags *****/
+#define ARM_MCI_RESPONSE_Pos             0
+#define ARM_MCI_RESPONSE_Msk            (3UL << ARM_MCI_RESPONSE_Pos)
+#define ARM_MCI_RESPONSE_NONE           (0UL << ARM_MCI_RESPONSE_Pos)   ///< No response expected (default)
+#define ARM_MCI_RESPONSE_SHORT          (1UL << ARM_MCI_RESPONSE_Pos)   ///< Short response (48-bit)
+#define ARM_MCI_RESPONSE_SHORT_BUSY     (2UL << ARM_MCI_RESPONSE_Pos)   ///< Short response with busy signal (48-bit)
+#define ARM_MCI_RESPONSE_LONG           (3UL << ARM_MCI_RESPONSE_Pos)   ///< Long response (136-bit)
+
+#define ARM_MCI_RESPONSE_INDEX          (1UL << 2)  ///< Check command index in response
+#define ARM_MCI_RESPONSE_CRC            (1UL << 3)  ///< Check CRC in response
+
+#define ARM_MCI_WAIT_BUSY               (1UL << 4)  ///< Wait until busy before sending the command
+
+#define ARM_MCI_TRANSFER_DATA           (1UL << 5)  ///< Activate Data transfer
+
+#define ARM_MCI_CARD_INITIALIZE         (1UL << 6)  ///< Execute Memory Card initialization sequence
+
+#define ARM_MCI_INTERRUPT_COMMAND       (1UL << 7)  ///< Send Interrupt command (CMD40 - MMC only)
+#define ARM_MCI_INTERRUPT_RESPONSE      (1UL << 8)  ///< Send Interrupt response (CMD40 - MMC only)
+
+#define ARM_MCI_BOOT_OPERATION          (1UL << 9)  ///< Execute Boot operation (MMC only)
+#define ARM_MCI_BOOT_ALTERNATIVE        (1UL << 10) ///< Execute Alternative Boot operation (MMC only)
+#define ARM_MCI_BOOT_ACK                (1UL << 11) ///< Expect Boot Acknowledge (MMC only)
+
+#define ARM_MCI_CCSD                    (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device
+#define ARM_MCI_CCS                     (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device
+
+
+/****** MCI Setup Transfer Mode *****/
+#define ARM_MCI_TRANSFER_READ           (0UL << 0)  ///< Data Read Transfer (from MCI)
+#define ARM_MCI_TRANSFER_WRITE          (1UL << 0)  ///< Data Write Transfer (to MCI)
+#define ARM_MCI_TRANSFER_BLOCK          (0UL << 1)  ///< Block Data transfer (default)
+#define ARM_MCI_TRANSFER_STREAM         (1UL << 1)  ///< Stream Data transfer (MMC only)
+
+
+/****** MCI Control Codes *****/
+#define ARM_MCI_BUS_SPEED               (0x01)      ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s
+#define ARM_MCI_BUS_SPEED_MODE          (0x02)      ///< Set Bus Speed Mode as specified with arg
+#define ARM_MCI_BUS_CMD_MODE            (0x03)      ///< Set CMD Line Mode as specified with arg
+#define ARM_MCI_BUS_DATA_WIDTH          (0x04)      ///< Set Bus Data Width as specified with arg
+#define ARM_MCI_DRIVER_STRENGTH         (0x05)      ///< Set SD UHS-I Driver Strength as specified with arg 
+#define ARM_MCI_CONTROL_RESET           (0x06)      ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active 
+#define ARM_MCI_CONTROL_CLOCK_IDLE      (0x07)      ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled
+#define ARM_MCI_UHS_TUNING_OPERATION    (0x08)      ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute
+#define ARM_MCI_UHS_TUNING_RESULT       (0x09)      ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error
+#define ARM_MCI_DATA_TIMEOUT            (0x0A)      ///< Set Data timeout; arg = timeout in bus cycles
+#define ARM_MCI_CSS_TIMEOUT             (0x0B)      ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles
+#define ARM_MCI_MONITOR_SDIO_INTERRUPT  (0x0C)      ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled
+#define ARM_MCI_CONTROL_READ_WAIT       (0x0D)      ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled
+#define ARM_MCI_SUSPEND_TRANSFER        (0x0E)      ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer
+#define ARM_MCI_RESUME_TRANSFER         (0x0F)      ///< Resume Data transfer (SD I/O)
+
+/*----- MCI Bus Speed Mode -----*/
+#define ARM_MCI_BUS_DEFAULT_SPEED       (0x00)      ///< SD/MMC: Default Speed mode up to 25/26MHz
+#define ARM_MCI_BUS_HIGH_SPEED          (0x01)      ///< SD/MMC: High    Speed mode up to 50/52MHz
+#define ARM_MCI_BUS_UHS_SDR12           (0x02)      ///< SD: SDR12  (Single Data Rate) up to  25MHz,  12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR25           (0x03)      ///< SD: SDR25  (Single Data Rate) up to  50MHz,  25  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR50           (0x04)      ///< SD: SDR50  (Single Data Rate) up to 100MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR104          (0x05)      ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_DDR50           (0x06)      ///< SD: DDR50  (Dual Data Rate)   up to  50MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+
+/*----- MCI CMD Line Mode -----*/
+#define ARM_MCI_BUS_CMD_PUSH_PULL       (0x00)      ///< Push-Pull CMD line (default)
+#define ARM_MCI_BUS_CMD_OPEN_DRAIN      (0x01)      ///< Open Drain CMD line (MMC only)
+
+/*----- MCI Bus Data Width -----*/
+#define ARM_MCI_BUS_DATA_WIDTH_1        (0x00)      ///< Bus data width: 1 bit (default)
+#define ARM_MCI_BUS_DATA_WIDTH_4        (0x01)      ///< Bus data width: 4 bits
+#define ARM_MCI_BUS_DATA_WIDTH_8        (0x02)      ///< Bus data width: 8 bits
+#define ARM_MCI_BUS_DATA_WIDTH_4_DDR    (0x03)      ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only
+#define ARM_MCI_BUS_DATA_WIDTH_8_DDR    (0x04)      ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only
+
+/*----- MCI Driver Strength -----*/
+#define ARM_MCI_DRIVER_TYPE_A           (0x01)      ///< SD UHS-I Driver Type A
+#define ARM_MCI_DRIVER_TYPE_B           (0x00)      ///< SD UHS-I Driver Type B (default)
+#define ARM_MCI_DRIVER_TYPE_C           (0x02)      ///< SD UHS-I Driver Type C
+#define ARM_MCI_DRIVER_TYPE_D           (0x03)      ///< SD UHS-I Driver Type D
+
+
+/****** MCI Card Power *****/
+#define ARM_MCI_POWER_VDD_Pos            0
+#define ARM_MCI_POWER_VDD_Msk           (0x0FUL << ARM_MCI_POWER_VDD_Pos)
+#define ARM_MCI_POWER_VDD_OFF           (0x01UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) turned off
+#define ARM_MCI_POWER_VDD_3V3           (0x02UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 3.3V
+#define ARM_MCI_POWER_VDD_1V8           (0x03UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 1.8V
+#define ARM_MCI_POWER_VCCQ_Pos           4
+#define ARM_MCI_POWER_VCCQ_Msk          (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)
+#define ARM_MCI_POWER_VCCQ_OFF          (0x01UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ turned off
+#define ARM_MCI_POWER_VCCQ_3V3          (0x02UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 3.3V
+#define ARM_MCI_POWER_VCCQ_1V8          (0x03UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.8V
+#define ARM_MCI_POWER_VCCQ_1V2          (0x04UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.2V
+
+
+/**
+\brief MCI Status
+*/
+typedef volatile struct _ARM_MCI_STATUS {
+  uint32_t command_active   : 1;        ///< Command active flag
+  uint32_t command_timeout  : 1;        ///< Command timeout flag (cleared on start of next command)
+  uint32_t command_error    : 1;        ///< Command error flag (cleared on start of next command)
+  uint32_t transfer_active  : 1;        ///< Transfer active flag
+  uint32_t transfer_timeout : 1;        ///< Transfer timeout flag (cleared on start of next command)
+  uint32_t transfer_error   : 1;        ///< Transfer error flag (cleared on start of next command)
+  uint32_t sdio_interrupt   : 1;        ///< SD I/O Interrupt flag (cleared on start of monitoring)
+  uint32_t ccs              : 1;        ///< CCS flag (cleared on start of next command)
+  uint32_t reserved         : 24;
+} ARM_MCI_STATUS;
+
+
+/****** MCI Card Event *****/
+#define ARM_MCI_EVENT_CARD_INSERTED     (1UL << 0)  ///< Memory Card inserted
+#define ARM_MCI_EVENT_CARD_REMOVED      (1UL << 1)  ///< Memory Card removed
+#define ARM_MCI_EVENT_COMMAND_COMPLETE  (1UL << 2)  ///< Command completed
+#define ARM_MCI_EVENT_COMMAND_TIMEOUT   (1UL << 3)  ///< Command timeout
+#define ARM_MCI_EVENT_COMMAND_ERROR     (1UL << 4)  ///< Command response error (CRC error or invalid response)
+#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5)  ///< Data transfer completed
+#define ARM_MCI_EVENT_TRANSFER_TIMEOUT  (1UL << 6)  ///< Data transfer timeout
+#define ARM_MCI_EVENT_TRANSFER_ERROR    (1UL << 7)  ///< Data transfer CRC failed
+#define ARM_MCI_EVENT_SDIO_INTERRUPT    (1UL << 8)  ///< SD I/O Interrupt
+#define ARM_MCI_EVENT_CCS               (1UL << 9)  ///< Command Completion Signal (CCS)
+#define ARM_MCI_EVENT_CCS_TIMEOUT       (1UL << 10) ///< Command Completion Signal (CCS) Timeout
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_MCI_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_MCI_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)
+  \brief         Initialize the Memory Card Interface
+  \param[in]     cb_event  Pointer to \ref ARM_MCI_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Uninitialize (void)
+  \brief         De-initialize Memory Card Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)
+  \brief         Control Memory Card Interface Power.
+  \param[in]     state   Power state \ref ARM_POWER_STATE
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_CardPower (uint32_t voltage)
+  \brief         Set Memory Card Power supply voltage.
+  \param[in]     voltage  Memory Card Power supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadCD (void)
+  \brief         Read Card Detect (CD) state.
+  \return        1:card detected, 0:card not detected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadWP (void)
+  \brief         Read Write Protect (WP) state.
+  \return        1:write protected, 0:not write protected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_SendCommand (uint32_t  cmd,
+                                              uint32_t  arg,
+                                              uint32_t  flags,
+                                              uint32_t *response)
+  \brief         Send Command to card and get the response.
+  \param[in]     cmd       Memory Card command
+  \param[in]     arg       Command argument
+  \param[in]     flags     Command flags
+  \param[out]    response  Pointer to buffer for response
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_SetupTransfer (uint8_t *data,
+                                                uint32_t block_count,
+                                                uint32_t block_size,
+                                                uint32_t mode)
+  \brief         Setup read or write transfer operation.
+  \param[in,out] data         Pointer to data block(s) to be written or read
+  \param[in]     block_count  Number of blocks
+  \param[in]     block_size   Size of a block in bytes
+  \param[in]     mode         Transfer mode
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_AbortTransfer (void)
+  \brief         Abort current read/write data transfer.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Control (uint32_t control, uint32_t arg)
+  \brief         Control MCI Interface.
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation (optional)
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_MCI_STATUS ARM_MCI_GetStatus (void)
+  \brief         Get MCI status.
+  \return        MCI status \ref ARM_MCI_STATUS
+*/
+
+/**
+  \fn            void ARM_MCI_SignalEvent (uint32_t event)
+  \brief         Callback function that signals a MCI Card Event.
+  \param[in]     event \ref mci_event_gr
+  \return        none
+*/
+
+typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event.
+
+
+/**
+\brief  MCI Driver Capabilities.
+*/
+typedef struct _ARM_MCI_CAPABILITIES {
+  uint32_t cd_state          : 1;       ///< Card Detect State available
+  uint32_t cd_event          : 1;       ///< Signal Card Detect change event
+  uint32_t wp_state          : 1;       ///< Write Protect State available
+  uint32_t vdd               : 1;       ///< Supports VDD Card Power Supply Control
+  uint32_t vdd_1v8           : 1;       ///< Supports 1.8 VDD Card Power Supply
+  uint32_t vccq              : 1;       ///< Supports VCCQ Card Power Supply Control (eMMC)
+  uint32_t vccq_1v8          : 1;       ///< Supports 1.8 VCCQ Card Power Supply (eMMC)
+  uint32_t vccq_1v2          : 1;       ///< Supports 1.2 VCCQ Card Power Supply (eMMC)
+  uint32_t data_width_4      : 1;       ///< Supports 4-bit data
+  uint32_t data_width_8      : 1;       ///< Supports 8-bit data
+  uint32_t data_width_4_ddr  : 1;       ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t data_width_8_ddr  : 1;       ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t high_speed        : 1;       ///< Supports SD/MMC High Speed Mode
+  uint32_t uhs_signaling     : 1;       ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling 
+  uint32_t uhs_tuning        : 1;       ///< Supports SD UHS-I tuning 
+  uint32_t uhs_sdr50         : 1;       ///< Supports SD UHS-I SDR50  (Single Data Rate) up to  50MB/s
+  uint32_t uhs_sdr104        : 1;       ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s
+  uint32_t uhs_ddr50         : 1;       ///< Supports SD UHS-I DDR50  (Dual   Data Rate) up to  50MB/s
+  uint32_t uhs_driver_type_a : 1;       ///< Supports SD UHS-I Driver Type A
+  uint32_t uhs_driver_type_c : 1;       ///< Supports SD UHS-I Driver Type C
+  uint32_t uhs_driver_type_d : 1;       ///< Supports SD UHS-I Driver Type D 
+  uint32_t sdio_interrupt    : 1;       ///< Supports SD I/O Interrupt 
+  uint32_t read_wait         : 1;       ///< Supports Read Wait (SD I/O)
+  uint32_t suspend_resume    : 1;       ///< Supports Suspend/Resume (SD I/O)
+  uint32_t mmc_interrupt     : 1;       ///< Supports MMC Interrupt 
+  uint32_t mmc_boot          : 1;       ///< Supports MMC Boot 
+  uint32_t rst_n             : 1;       ///< Supports RST_n Pin Control (eMMC)
+  uint32_t ccs               : 1;       ///< Supports Command Completion Signal (CCS) for CE-ATA
+  uint32_t ccs_timeout       : 1;       ///< Supports Command Completion Signal (CCS) timeout for CE-ATA
+  uint32_t reserved          : 3;       ///< Reserved (must be zero)
+} ARM_MCI_CAPABILITIES;
+
+
+/**
+\brief  Access structure of the MCI Driver.
+*/
+typedef struct _ARM_DRIVER_MCI {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                           ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version.
+  ARM_MCI_CAPABILITIES (*GetCapabilities)(void);                           ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface.
+  int32_t              (*Uninitialize)   (void);                           ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);          ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power.
+  int32_t              (*CardPower)      (uint32_t voltage);               ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage.
+  int32_t              (*ReadCD)         (void);                           ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state.
+  int32_t              (*ReadWP)         (void);                           ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state.
+  int32_t              (*SendCommand)    (uint32_t cmd, 
+                                          uint32_t arg, 
+                                          uint32_t flags,
+                                          uint32_t *response);             ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response.
+  int32_t              (*SetupTransfer)  (uint8_t *data,
+                                          uint32_t block_count,
+                                          uint32_t block_size,
+                                          uint32_t mode);                  ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation.
+  int32_t              (*AbortTransfer)  (void);                           ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface.
+  ARM_MCI_STATUS       (*GetStatus)      (void);                           ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status.
+} const ARM_DRIVER_MCI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_MCI_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_NAND.h

@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        14. Nov 2017
+ * $Revision:    V2.3
+ *
+ * Project:      NAND Flash Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    Extended ARM_NAND_ECC_INFO structure
+ *  Version 2.2
+ *    ARM_NAND_STATUS made volatile
+ *  Version 2.1
+ *    Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (command agnostic)
+ *    Added support for:
+ *      NV-DDR & NV-DDR2 Interface (ONFI specification)
+ *      VCC, VCCQ and VPP Power Supply Control
+ *      WP (Write Protect) Control
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_NAND_H_
+#define DRIVER_NAND_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+/****** NAND Device Power *****/
+#define ARM_NAND_POWER_VCC_Pos           0
+#define ARM_NAND_POWER_VCC_Msk          (0x07UL << ARM_NAND_POWER_VCC_Pos)
+#define ARM_NAND_POWER_VCC_OFF          (0x01UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC Power off
+#define ARM_NAND_POWER_VCC_3V3          (0x02UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 3.3V
+#define ARM_NAND_POWER_VCC_1V8          (0x03UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 1.8V
+#define ARM_NAND_POWER_VCCQ_Pos          3
+#define ARM_NAND_POWER_VCCQ_Msk         (0x07UL << ARM_NAND_POWER_VCCQ_Pos)
+#define ARM_NAND_POWER_VCCQ_OFF         (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off
+#define ARM_NAND_POWER_VCCQ_3V3         (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V
+#define ARM_NAND_POWER_VCCQ_1V8         (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V
+#define ARM_NAND_POWER_VPP_OFF          (1UL << 6)                          ///< VPP off
+#define ARM_NAND_POWER_VPP_ON           (1Ul << 7)                          ///< VPP on
+
+
+/****** NAND Control Codes *****/
+#define ARM_NAND_BUS_MODE               (0x01)      ///< Set Bus Mode as specified with arg
+#define ARM_NAND_BUS_DATA_WIDTH         (0x02)      ///< Set Bus Data Width as specified with arg
+#define ARM_NAND_DRIVER_STRENGTH        (0x03)      ///< Set Driver Strength as specified with arg
+#define ARM_NAND_DEVICE_READY_EVENT     (0x04)      ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled 
+#define ARM_NAND_DRIVER_READY_EVENT     (0x05)      ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled 
+
+/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_BUS_INTERFACE_Pos       4
+#define ARM_NAND_BUS_INTERFACE_Msk      (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)
+#define ARM_NAND_BUS_SDR                (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface:    SDR  (Single Data Rate) - Traditional interface (default)
+#define ARM_NAND_BUS_DDR                (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR  (Double Data Rate)
+#define ARM_NAND_BUS_DDR2               (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR2 (Double Data Rate)
+#define ARM_NAND_BUS_TIMING_MODE_Pos     0
+#define ARM_NAND_BUS_TIMING_MODE_Msk    (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)
+#define ARM_NAND_BUS_TIMING_MODE_0      (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 0 (default)
+#define ARM_NAND_BUS_TIMING_MODE_1      (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 1
+#define ARM_NAND_BUS_TIMING_MODE_2      (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 2
+#define ARM_NAND_BUS_TIMING_MODE_3      (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 3
+#define ARM_NAND_BUS_TIMING_MODE_4      (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 4 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_5      (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 5 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_6      (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 6 (NV-DDR2 only)
+#define ARM_NAND_BUS_TIMING_MODE_7      (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 7 (NV-DDR2 only)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos    8
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1
+#define ARM_NAND_BUS_DDR2_DO_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2
+#define ARM_NAND_BUS_DDR2_DO_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos    12
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1
+#define ARM_NAND_BUS_DDR2_DI_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2
+#define ARM_NAND_BUS_DDR2_DI_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4
+#define ARM_NAND_BUS_DDR2_VEN           (1UL << 16)                               ///< DDR2 Enable external VREFQ as reference
+#define ARM_NAND_BUS_DDR2_CMPD          (1UL << 17)                               ///< DDR2 Enable complementary DQS (DQS_c) signal
+#define ARM_NAND_BUS_DDR2_CMPR          (1UL << 18)                               ///< DDR2 Enable complementary RE_n (RE_c) signal
+
+/*----- NAND Data Bus Width -----*/
+#define ARM_NAND_BUS_DATA_WIDTH_8       (0x00)      ///< Bus Data Width:  8 bit (default)
+#define ARM_NAND_BUS_DATA_WIDTH_16      (0x01)      ///< Bus Data Width: 16 bit
+
+/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_DRIVER_STRENGTH_18     (0x00)      ///< Driver Strength 2.0x = 18 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_25     (0x01)      ///< Driver Strength 1.4x = 25 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_35     (0x02)      ///< Driver Strength 1.0x = 35 Ohms (default)
+#define ARM_NAND_DRIVER_STRENGTH_50     (0x03)      ///< Driver Strength 0.7x = 50 Ohms
+
+
+/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_ECC_INDEX_Pos           0
+#define ARM_NAND_ECC_INDEX_Msk          (0xFFUL << ARM_NAND_ECC_INDEX_Pos)
+#define ARM_NAND_ECC(n)                 ((n) & ARM_NAND_ECC_INDEX_Msk)     ///< Select ECC
+#define ARM_NAND_ECC0                   (1UL << 8)                         ///< Use ECC0 of selected ECC
+#define ARM_NAND_ECC1                   (1UL << 9)                         ///< Use ECC1 of selected ECC
+
+/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_DRIVER_DONE_EVENT      (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE
+
+/****** NAND Sequence Execution Code *****/
+#define ARM_NAND_CODE_SEND_CMD1         (1UL << 17) ///< Send Command 1
+#define ARM_NAND_CODE_SEND_ADDR_COL1    (1UL << 18) ///< Send Column Address 1
+#define ARM_NAND_CODE_SEND_ADDR_COL2    (1UL << 19) ///< Send Column Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW1    (1UL << 20) ///< Send Row Address 1
+#define ARM_NAND_CODE_SEND_ADDR_ROW2    (1UL << 21) ///< Send Row Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW3    (1UL << 22) ///< Send Row Address 3
+#define ARM_NAND_CODE_INC_ADDR_ROW      (1UL << 23) ///< Auto-increment Row Address
+#define ARM_NAND_CODE_WRITE_DATA        (1UL << 24) ///< Write Data
+#define ARM_NAND_CODE_SEND_CMD2         (1UL << 25) ///< Send Command 2
+#define ARM_NAND_CODE_WAIT_BUSY         (1UL << 26) ///< Wait while R/Bn busy
+#define ARM_NAND_CODE_READ_DATA         (1UL << 27) ///< Read Data
+#define ARM_NAND_CODE_SEND_CMD3         (1UL << 28) ///< Send Command 3
+#define ARM_NAND_CODE_READ_STATUS       (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0)
+
+/*----- NAND Sequence Execution Code: Command -----*/
+#define ARM_NAND_CODE_CMD1_Pos           0
+#define ARM_NAND_CODE_CMD1_Msk          (0xFFUL << ARM_NAND_CODE_CMD1_Pos)
+#define ARM_NAND_CODE_CMD2_Pos           8
+#define ARM_NAND_CODE_CMD2_Msk          (0xFFUL << ARM_NAND_CODE_CMD2_Pos)
+#define ARM_NAND_CODE_CMD3_Pos           16
+#define ARM_NAND_CODE_CMD3_Msk          (0xFFUL << ARM_NAND_CODE_CMD3_Pos)
+
+/*----- NAND Sequence Execution Code: Column Address -----*/
+#define ARM_NAND_CODE_ADDR_COL1_Pos      0
+#define ARM_NAND_CODE_ADDR_COL1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)
+#define ARM_NAND_CODE_ADDR_COL2_Pos      8
+#define ARM_NAND_CODE_ADDR_COL2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)
+
+/*----- NAND Sequence Execution Code: Row Address -----*/
+#define ARM_NAND_CODE_ADDR_ROW1_Pos      0
+#define ARM_NAND_CODE_ADDR_ROW1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)
+#define ARM_NAND_CODE_ADDR_ROW2_Pos      8
+#define ARM_NAND_CODE_ADDR_ROW2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)
+#define ARM_NAND_CODE_ADDR_ROW3_Pos      16
+#define ARM_NAND_CODE_ADDR_ROW3_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)
+
+
+/****** NAND specific error codes *****/
+#define ARM_NAND_ERROR_ECC              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< ECC generation/correction failed
+
+
+/**
+\brief NAND ECC (Error Correction Code) Information
+*/
+typedef struct _ARM_NAND_ECC_INFO {
+  uint32_t type             :  2;       ///< Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare
+  uint32_t page_layout      :  1;       ///< Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1|
+  uint32_t page_count       :  3;       ///< Number of virtual pages: N = 2 ^ page_count
+  uint32_t page_size        :  4;       ///< Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description)
+  uint32_t reserved         : 14;       ///< Reserved (must be zero)
+  uint32_t correctable_bits :  8;       ///< Number of correctable bits (based on 512 byte codeword size)
+  uint16_t codeword_size     [2];       ///< Number of bytes over which ECC is calculated
+  uint16_t ecc_size          [2];       ///< ECC size in bytes (rounded up)
+  uint16_t ecc_offset        [2];       ///< ECC offset in bytes (where ECC starts in Spare)
+  /* Extended description */
+  uint16_t virtual_page_size [2];       ///< Virtual Page size in bytes (Main/Spare)
+  uint16_t codeword_offset   [2];       ///< Codeword offset in bytes (where ECC protected data starts in Main/Spare)
+  uint16_t codeword_gap      [2];       ///< Codeword gap in bytes till next protected data
+  uint16_t ecc_gap           [2];       ///< ECC gap in bytes till next generated ECC
+} ARM_NAND_ECC_INFO;
+
+
+/**
+\brief NAND Status
+*/
+typedef volatile struct _ARM_NAND_STATUS {
+  uint32_t busy      : 1;               ///< Driver busy flag
+  uint32_t ecc_error : 1;               ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence)
+  uint32_t reserved  : 30;
+} ARM_NAND_STATUS;
+
+
+/****** NAND Event *****/
+#define ARM_NAND_EVENT_DEVICE_READY     (1UL << 0)  ///< Device Ready: R/Bn rising edge
+#define ARM_NAND_EVENT_DRIVER_READY     (1UL << 1)  ///< Driver Ready
+#define ARM_NAND_EVENT_DRIVER_DONE      (1UL << 2)  ///< Driver operation done
+#define ARM_NAND_EVENT_ECC_ERROR        (1UL << 3)  ///< ECC could not correct data
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_NAND_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event)
+  \brief         Initialize the NAND Interface.
+  \param[in]     cb_event  Pointer to \ref ARM_NAND_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Uninitialize (void)
+  \brief         De-initialize the NAND Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)
+  \brief         Control the NAND interface power.
+  \param[in]     state  Power state
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_DevicePower (uint32_t voltage)
+  \brief         Set device power supply voltage.
+  \param[in]     voltage  NAND Device supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)
+  \brief         Control WPn (Write Protect).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Write Protect off
+                - \b true  Write Protect on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)
+  \brief         Control CEn (Chip Enable).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Chip Enable off
+                - \b true  Chip Enable on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)
+  \brief         Get Device Busy pin state.
+  \param[in]     dev_num  Device number
+  \return        1=busy, 0=not busy, or error
+*/
+/**
+  \fn            int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)
+  \brief         Send command to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     cmd      Command
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)
+  \brief         Send address to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     addr     Address
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)
+  \brief         Read data from NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer for data to read from NAND device
+  \param[in]     cnt      Number of data items to read
+  \param[in]     mode     Operation mode
+  \return        number of data items read or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)
+  \brief         Write data to NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer with data to write to NAND device
+  \param[in]     cnt      Number of data items to write
+  \param[in]     mode     Operation mode
+  \return        number of data items written or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                                   uint32_t addr_col, uint32_t addr_row,
+                                                   void *data, uint32_t data_cnt,
+                                                   uint8_t *status, uint32_t *count)
+  \brief         Execute sequence of operations.
+  \param[in]     dev_num  Device number
+  \param[in]     code     Sequence code
+  \param[in]     cmd      Command(s)
+  \param[in]     addr_col Column address
+  \param[in]     addr_row Row address
+  \param[in,out] data     Pointer to data to be written or read 
+  \param[in]     data_cnt Number of data items in one iteration
+  \param[out]    status   Pointer to status read
+  \param[in,out] count    Number of iterations
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_AbortSequence (uint32_t dev_num)
+  \brief         Abort sequence execution.
+  \param[in]     dev_num  Device number
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)
+  \brief         Control NAND Interface.
+  \param[in]     dev_num  Device number
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)
+  \brief         Get NAND status.
+  \param[in]     dev_num  Device number
+  \return        NAND status \ref ARM_NAND_STATUS
+*/
+/**
+  \fn            int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)
+  \brief         Inquire about available ECC.
+  \param[in]     index   Inquire ECC index
+  \param[out]    info    Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved
+  \return        \ref execution_status
+*/
+
+/**
+  \fn            void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)
+  \brief         Signal NAND event.
+  \param[in]     dev_num  Device number
+  \param[in]     event    Event notification mask
+  \return        none
+*/
+
+typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event);    ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event.
+
+
+/**
+\brief NAND Driver Capabilities.
+*/
+typedef struct _ARM_NAND_CAPABILITIES {
+  uint32_t event_device_ready  : 1;     ///< Signal Device Ready event (R/Bn rising edge)
+  uint32_t reentrant_operation : 1;     ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData)
+  uint32_t sequence_operation  : 1;     ///< Supports Sequence operation (ExecuteSequence, AbortSequence)
+  uint32_t vcc                 : 1;     ///< Supports VCC Power Supply Control
+  uint32_t vcc_1v8             : 1;     ///< Supports 1.8 VCC Power Supply
+  uint32_t vccq                : 1;     ///< Supports VCCQ I/O Power Supply Control
+  uint32_t vccq_1v8            : 1;     ///< Supports 1.8 VCCQ I/O Power Supply
+  uint32_t vpp                 : 1;     ///< Supports VPP High Voltage Power Supply Control
+  uint32_t wp                  : 1;     ///< Supports WPn (Write Protect) Control
+  uint32_t ce_lines            : 4;     ///< Number of CEn (Chip Enable) lines: ce_lines + 1
+  uint32_t ce_manual           : 1;     ///< Supports manual CEn (Chip Enable) Control
+  uint32_t rb_monitor          : 1;     ///< Supports R/Bn (Ready/Busy) Monitoring
+  uint32_t data_width_16       : 1;     ///< Supports 16-bit data
+  uint32_t ddr                 : 1;     ///< Supports NV-DDR  Data Interface (ONFI)
+  uint32_t ddr2                : 1;     ///< Supports NV-DDR2 Data Interface (ONFI)
+  uint32_t sdr_timing_mode     : 3;     ///< Fastest (highest) SDR     Timing Mode supported (ONFI)
+  uint32_t ddr_timing_mode     : 3;     ///< Fastest (highest) NV_DDR  Timing Mode supported (ONFI)
+  uint32_t ddr2_timing_mode    : 3;     ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)
+  uint32_t driver_strength_18  : 1;     ///< Supports Driver Strength 2.0x = 18 Ohms
+  uint32_t driver_strength_25  : 1;     ///< Supports Driver Strength 1.4x = 25 Ohms
+  uint32_t driver_strength_50  : 1;     ///< Supports Driver Strength 0.7x = 50 Ohms
+  uint32_t reserved            : 2;     ///< Reserved (must be zero)
+} ARM_NAND_CAPABILITIES;
+
+
+/**
+\brief Access structure of the NAND Driver.
+*/
+typedef struct _ARM_DRIVER_NAND {
+  ARM_DRIVER_VERSION    (*GetVersion)     (void);                                                             ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version.
+  ARM_NAND_CAPABILITIES (*GetCapabilities)(void);                                                             ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)     (ARM_NAND_SignalEvent_t cb_event);                                  ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface.
+  int32_t               (*Uninitialize)   (void);                                                             ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface.
+  int32_t               (*PowerControl)   (ARM_POWER_STATE state);                                            ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power.
+  int32_t               (*DevicePower)    (uint32_t voltage);                                                 ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage.
+  int32_t               (*WriteProtect)   (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect).
+  int32_t               (*ChipEnable)     (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable).
+  int32_t               (*GetDeviceBusy)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state.
+  int32_t               (*SendCommand)    (uint32_t dev_num, uint8_t cmd);                                    ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device.
+  int32_t               (*SendAddress)    (uint32_t dev_num, uint8_t addr);                                   ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device.
+  int32_t               (*ReadData)       (uint32_t dev_num,       void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device.
+  int32_t               (*WriteData)      (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device.
+  int32_t               (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                           uint32_t addr_col, uint32_t addr_row,
+                                           void *data, uint32_t data_cnt,
+                                           uint8_t *status, uint32_t *count);                                 ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations.
+  int32_t               (*AbortSequence)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution. 
+  int32_t               (*Control)        (uint32_t dev_num, uint32_t control, uint32_t arg);                 ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface.
+  ARM_NAND_STATUS       (*GetStatus)      (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status.
+  int32_t               (*InquireECC)     ( int32_t index, ARM_NAND_ECC_INFO *info);                          ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC. 
+} const ARM_DRIVER_NAND;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_NAND_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_SAI.h

@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V1.1
+ *
+ * Project:      SAI (Serial Audio Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 1.1
+ *    ARM_SAI_STATUS made volatile
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_SAI_H_
+#define DRIVER_SAI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1)  /* API version */
+
+
+/****** SAI Control Codes *****/
+
+#define ARM_SAI_CONTROL_Msk             (0xFFU)
+#define ARM_SAI_CONFIGURE_TX            (0x01U)     ///< Configure Transmitter;  arg1 and arg2 provide additional configuration
+#define ARM_SAI_CONFIGURE_RX            (0x02U)     ///< Configure Receiver;     arg1 and arg2 provide additional configuration
+#define ARM_SAI_CONTROL_TX              (0x03U)     ///< Control Transmitter;    arg1.0: 0=disable (default), 1=enable; arg1.1: mute
+#define ARM_SAI_CONTROL_RX              (0x04U)     ///< Control Receiver;       arg1.0: 0=disable (default), 1=enable
+#define ARM_SAI_MASK_SLOTS_TX           (0x05U)     ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
+#define ARM_SAI_MASK_SLOTS_RX           (0x06U)     ///< Mask Receiver    slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
+#define ARM_SAI_ABORT_SEND              (0x07U)     ///< Abort \ref ARM_SAI_Send
+#define ARM_SAI_ABORT_RECEIVE           (0x08U)     ///< Abort \ref ARM_SAI_Receive
+
+/*----- SAI Control Codes: Configuration Parameters: Mode -----*/
+#define ARM_SAI_MODE_Pos                 8
+#define ARM_SAI_MODE_Msk                (1U << ARM_SAI_MODE_Pos)
+#define ARM_SAI_MODE_MASTER             (1U << ARM_SAI_MODE_Pos)                ///< Master Mode
+#define ARM_SAI_MODE_SLAVE              (0U << ARM_SAI_MODE_Pos)                ///< Slave Mode (default)
+
+/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/
+#define ARM_SAI_SYNCHRONIZATION_Pos      9
+#define ARM_SAI_SYNCHRONIZATION_Msk     (1U << ARM_SAI_SYNCHRONIZATION_Pos)
+#define ARM_SAI_ASYNCHRONOUS            (0U << ARM_SAI_SYNCHRONIZATION_Pos)     ///< Asynchronous (default)
+#define ARM_SAI_SYNCHRONOUS             (1U << ARM_SAI_SYNCHRONIZATION_Pos)     ///< Synchronous
+
+/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/
+#define ARM_SAI_PROTOCOL_Pos             10
+#define ARM_SAI_PROTOCOL_Msk            (7U << ARM_SAI_PROTOCOL_Pos)
+#define ARM_SAI_PROTOCOL_USER           (0U << ARM_SAI_PROTOCOL_Pos)            ///< User defined (default) 
+#define ARM_SAI_PROTOCOL_I2S            (1U << ARM_SAI_PROTOCOL_Pos)            ///< I2S
+#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED  (2U << ARM_SAI_PROTOCOL_Pos)            ///< MSB (left) justified 
+#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED  (3U << ARM_SAI_PROTOCOL_Pos)            ///< LSB (right) justified
+#define ARM_SAI_PROTOCOL_PCM_SHORT      (4U << ARM_SAI_PROTOCOL_Pos)            ///< PCM with short frame
+#define ARM_SAI_PROTOCOL_PCM_LONG       (5U << ARM_SAI_PROTOCOL_Pos)            ///< PCM with long frame
+#define ARM_SAI_PROTOCOL_AC97           (6U << ARM_SAI_PROTOCOL_Pos)            ///< AC'97
+
+/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/
+#define ARM_SAI_DATA_SIZE_Pos            13
+#define ARM_SAI_DATA_SIZE_Msk                    (0x1FU  << ARM_SAI_DATA_SIZE_Pos)
+#define ARM_SAI_DATA_SIZE(n)            ((((n)-1)&0x1FU) << ARM_SAI_DATA_SIZE_Pos)  ///< Data size in bits (8..32)
+
+/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/
+#define ARM_SAI_BIT_ORDER_Pos            18
+#define ARM_SAI_BIT_ORDER_Msk           (1U << ARM_SAI_BIT_ORDER_Pos)
+#define ARM_SAI_MSB_FIRST               (0U << ARM_SAI_BIT_ORDER_Pos)           ///< Data is transferred with MSB first (default)
+#define ARM_SAI_LSB_FIRST               (1U << ARM_SAI_BIT_ORDER_Pos)           ///< Data is transferred with LSB first; User Protocol only (ignored otherwise)
+
+/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/
+#define ARM_SAI_MONO_MODE               (1U << 19)                              ///< Mono Mode (only for I2S, MSB/LSB justified)
+
+/*----- SAI Control Codes:Configuration Parameters: Companding -----*/
+#define ARM_SAI_COMPANDING_Pos           20
+#define ARM_SAI_COMPANDING_Msk          (3U << ARM_SAI_COMPANDING_Pos)
+#define ARM_SAI_COMPANDING_NONE         (0U << ARM_SAI_COMPANDING_Pos)          ///< No companding (default)
+#define ARM_SAI_COMPANDING_A_LAW        (2U << ARM_SAI_COMPANDING_Pos)          ///< A-Law companding
+#define ARM_SAI_COMPANDING_U_LAW        (3U << ARM_SAI_COMPANDING_Pos)          ///< u-Law companding
+
+/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/
+#define ARM_SAI_CLOCK_POLARITY_Pos       23
+#define ARM_SAI_CLOCK_POLARITY_Msk      (1U << ARM_SAI_CLOCK_POLARITY_Pos)
+#define ARM_SAI_CLOCK_POLARITY_0        (0U << ARM_SAI_CLOCK_POLARITY_Pos)      ///< Drive on falling edge, Capture on rising  edge (default)
+#define ARM_SAI_CLOCK_POLARITY_1        (1U << ARM_SAI_CLOCK_POLARITY_Pos)      ///< Drive on rising  edge, Capture on falling edge
+
+/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/
+#define ARM_SAI_MCLK_PIN_Pos             24
+#define ARM_SAI_MCLK_PIN_Msk            (3U << ARM_SAI_MCLK_PIN_Pos)
+#define ARM_SAI_MCLK_PIN_INACTIVE       (0U << ARM_SAI_MCLK_PIN_Pos)            ///< MCLK not used (default)
+#define ARM_SAI_MCLK_PIN_OUTPUT         (1U << ARM_SAI_MCLK_PIN_Pos)            ///< MCLK is output (Master only)
+#define ARM_SAI_MCLK_PIN_INPUT          (2U << ARM_SAI_MCLK_PIN_Pos)            ///< MCLK is input  (Master only)
+
+
+/****** SAI Configuration (arg1) *****/
+
+/*----- SAI Configuration (arg1): Frame Length -----*/
+#define ARM_SAI_FRAME_LENGTH_Pos          0
+#define ARM_SAI_FRAME_LENGTH_Msk                  (0x3FFU  << ARM_SAI_FRAME_LENGTH_Pos)
+#define ARM_SAI_FRAME_LENGTH(n)          ((((n)-1)&0x3FFU) << ARM_SAI_FRAME_LENGTH_Pos)     ///< Frame length in bits (8..1024); default depends on protocol and data
+
+/*----- SAI Configuration (arg1): Frame Sync Width -----*/
+#define ARM_SAI_FRAME_SYNC_WIDTH_Pos      10
+#define ARM_SAI_FRAME_SYNC_WIDTH_Msk              (0xFFU  << ARM_SAI_FRAME_SYNC_WIDTH_Pos)
+#define ARM_SAI_FRAME_SYNC_WIDTH(n)      ((((n)-1)&0xFFU) << ARM_SAI_FRAME_SYNC_WIDTH_Pos)  ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/
+#define ARM_SAI_FRAME_SYNC_POLARITY_Pos   18
+#define ARM_SAI_FRAME_SYNC_POLARITY_Msk  (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)
+#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)            ///< Frame Sync is active high (default); User Protocol only (ignored otherwise)
+#define ARM_SAI_FRAME_SYNC_POLARITY_LOW  (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)            ///< Frame Sync is active low; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Frame Sync Early -----*/
+#define ARM_SAI_FRAME_SYNC_EARLY         (1U << 19)                                         ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Count -----*/
+#define ARM_SAI_SLOT_COUNT_Pos            20
+#define ARM_SAI_SLOT_COUNT_Msk                    (0x1FU  << ARM_SAI_SLOT_COUNT_Pos)
+#define ARM_SAI_SLOT_COUNT(n)            ((((n)-1)&0x1FU) << ARM_SAI_SLOT_COUNT_Pos)        ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Size -----*/
+#define ARM_SAI_SLOT_SIZE_Pos             25
+#define ARM_SAI_SLOT_SIZE_Msk            (3U << ARM_SAI_SLOT_SIZE_Pos)
+#define ARM_SAI_SLOT_SIZE_DEFAULT        (0U << ARM_SAI_SLOT_SIZE_Pos)                      ///< Slot size is equal to data size (default)
+#define ARM_SAI_SLOT_SIZE_16             (1U << ARM_SAI_SLOT_SIZE_Pos)                      ///< Slot size = 16 bits; User Protocol only (ignored otherwise)
+#define ARM_SAI_SLOT_SIZE_32             (3U << ARM_SAI_SLOT_SIZE_Pos)                      ///< Slot size = 32 bits; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Offset -----*/
+#define ARM_SAI_SLOT_OFFSET_Pos           27
+#define ARM_SAI_SLOT_OFFSET_Msk               (0x1FU  << ARM_SAI_SLOT_OFFSET_Pos)
+#define ARM_SAI_SLOT_OFFSET(n)           (((n)&0x1FU) << ARM_SAI_SLOT_OFFSET_Pos)           ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise)
+
+/****** SAI Configuration (arg2) *****/
+
+/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/
+#define ARM_SAI_AUDIO_FREQ_Msk          (0x0FFFFFU)                                         ///< Audio frequency mask
+
+/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/
+#define ARM_SAI_MCLK_PRESCALER_Pos       20
+#define ARM_SAI_MCLK_PRESCALER_Msk      (0xFFFU << ARM_SAI_MCLK_PRESCALER_Pos)
+#define ARM_SAI_MCLK_PRESCALER(n)       ((((n)-1)&0xFFFU) << ARM_SAI_MCLK_PRESCALER_Pos)    ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1)
+
+
+/****** SAI specific error codes *****/
+#define ARM_SAI_ERROR_SYNCHRONIZATION       (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Synchronization not supported
+#define ARM_SAI_ERROR_PROTOCOL              (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Protocol not supported
+#define ARM_SAI_ERROR_DATA_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified Data size not supported
+#define ARM_SAI_ERROR_BIT_ORDER             (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported
+#define ARM_SAI_ERROR_MONO_MODE             (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Mono mode not supported
+#define ARM_SAI_ERROR_COMPANDING            (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Companding not supported
+#define ARM_SAI_ERROR_CLOCK_POLARITY        (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock polarity not supported
+#define ARM_SAI_ERROR_AUDIO_FREQ            (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Audio frequency not supported
+#define ARM_SAI_ERROR_MCLK_PIN              (ARM_DRIVER_ERROR_SPECIFIC - 9)     ///< Specified MCLK Pin setting not supported
+#define ARM_SAI_ERROR_MCLK_PRESCALER        (ARM_DRIVER_ERROR_SPECIFIC - 10)    ///< Specified MCLK Prescaler not supported
+#define ARM_SAI_ERROR_FRAME_LENGHT          (ARM_DRIVER_ERROR_SPECIFIC - 11)    ///< Specified Frame length not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH      (ARM_DRIVER_ERROR_SPECIFIC - 12)    ///< Specified Frame Sync width not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY   (ARM_DRIVER_ERROR_SPECIFIC - 13)    ///< Specified Frame Sync polarity not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_EARLY      (ARM_DRIVER_ERROR_SPECIFIC - 14)    ///< Specified Frame Sync early not supported
+#define ARM_SAI_ERROR_SLOT_COUNT            (ARM_DRIVER_ERROR_SPECIFIC - 15)    ///< Specified Slot count not supported
+#define ARM_SAI_ERROR_SLOT_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 16)    ///< Specified Slot size not supported
+#define ARM_SAI_ERROR_SLOT_OFFESET          (ARM_DRIVER_ERROR_SPECIFIC - 17)    ///< Specified Slot offset not supported
+
+
+/**
+\brief SAI Status
+*/
+typedef volatile struct _ARM_SAI_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t frame_error      : 1;        ///< Sync Frame error detected (cleared on start of next send/receive operation)
+  uint32_t reserved         : 27;
+} ARM_SAI_STATUS;
+
+
+/****** SAI Event *****/
+#define ARM_SAI_EVENT_SEND_COMPLETE     (1U << 0)   ///< Send completed
+#define ARM_SAI_EVENT_RECEIVE_COMPLETE  (1U << 1)   ///< Receive completed
+#define ARM_SAI_EVENT_TX_UNDERFLOW      (1U << 2)   ///< Transmit data not available
+#define ARM_SAI_EVENT_RX_OVERFLOW       (1U << 3)   ///< Receive data overflow
+#define ARM_SAI_EVENT_FRAME_ERROR       (1U << 4)   ///< Sync Frame error in Slave mode (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SAI_CAPABILITIES
+
+  \fn          int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
+  \brief       Initialize SAI Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SAI_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Uninitialize (void)
+  \brief       De-initialize SAI Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control SAI Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Send (const void *data, uint32_t num)
+  \brief       Start sending data to SAI transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SAI transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from SAI receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SAI receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_SAI_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_SAI_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
+  \brief       Control SAI Interface.
+  \param[in]   control  Operation
+  \param[in]   arg1     Argument 1 of operation (optional)
+  \param[in]   arg2     Argument 2 of operation (optional)
+  \return      common \ref execution_status and driver specific \ref sai_execution_status
+
+  \fn          ARM_SAI_STATUS ARM_SAI_GetStatus (void)
+  \brief       Get SAI status.
+  \return      SAI status \ref ARM_SAI_STATUS
+
+  \fn          void ARM_SAI_SignalEvent (uint32_t event)
+  \brief       Signal SAI Events.
+  \param[in]   event \ref SAI_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event.
+
+
+/**
+\brief SAI Driver Capabilities.
+*/
+typedef struct _ARM_SAI_CAPABILITIES {
+  uint32_t asynchronous          : 1;   ///< supports asynchronous Transmit/Receive
+  uint32_t synchronous           : 1;   ///< supports synchronous Transmit/Receive
+  uint32_t protocol_user         : 1;   ///< supports user defined Protocol
+  uint32_t protocol_i2s          : 1;   ///< supports I2S Protocol
+  uint32_t protocol_justified    : 1;   ///< supports MSB/LSB justified Protocol
+  uint32_t protocol_pcm          : 1;   ///< supports PCM short/long frame Protocol
+  uint32_t protocol_ac97         : 1;   ///< supports AC'97 Protocol
+  uint32_t mono_mode             : 1;   ///< supports Mono mode
+  uint32_t companding            : 1;   ///< supports Companding
+  uint32_t mclk_pin              : 1;   ///< supports MCLK (Master Clock) pin
+  uint32_t event_frame_error     : 1;   ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR
+  uint32_t reserved              : 21;  ///< Reserved (must be zero)
+} ARM_SAI_CAPABILITIES;
+
+
+/**
+\brief Access structure of the SAI Driver.
+*/
+typedef struct _ARM_DRIVER_SAI {
+  ARM_DRIVER_VERSION   (*GetVersion)      (void);                                            ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version.
+  ARM_SAI_CAPABILITIES (*GetCapabilities) (void);                                            ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)      (ARM_SAI_SignalEvent_t cb_event);                  ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface.
+  int32_t              (*Uninitialize)    (void);                                            ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface.
+  int32_t              (*PowerControl)    (ARM_POWER_STATE state);                           ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power.
+  int32_t              (*Send)            (const void *data, uint32_t num);                  ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface.
+  int32_t              (*Receive)         (      void *data, uint32_t num);                  ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface.
+  uint32_t             (*GetTxCount)      (void);                                            ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count.
+  uint32_t             (*GetRxCount)      (void);                                            ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count.
+  int32_t              (*Control)         (uint32_t control, uint32_t arg1, uint32_t arg2);  ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface.
+  ARM_SAI_STATUS       (*GetStatus)       (void);                                            ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status.
+} const ARM_DRIVER_SAI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_SAI_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_SPI.h

@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.2
+ *
+ * Project:      SPI (Serial Peripheral Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    ARM_SPI_STATUS made volatile
+ *  Version 2.1
+ *    Renamed status flag "tx_rx_busy" to "busy"
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *      Half-duplex Modes
+ *      Configurable number of data bits
+ *      Support for TI Mode and Microwire
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added "send_done_event" to Capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_SPI_H_
+#define DRIVER_SPI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+/****** SPI Control Codes *****/
+
+#define ARM_SPI_CONTROL_Pos              0
+#define ARM_SPI_CONTROL_Msk             (0xFFUL << ARM_SPI_CONTROL_Pos)
+
+/*----- SPI Control Codes: Mode -----*/
+#define ARM_SPI_MODE_INACTIVE           (0x00UL << ARM_SPI_CONTROL_Pos)     ///< SPI Inactive
+#define ARM_SPI_MODE_MASTER             (0x01UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
+#define ARM_SPI_MODE_SLAVE              (0x02UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output on MISO, Input on MOSI)
+#define ARM_SPI_MODE_MASTER_SIMPLEX     (0x03UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
+#define ARM_SPI_MODE_SLAVE_SIMPLEX      (0x04UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output/Input on MISO)
+
+/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
+#define ARM_SPI_FRAME_FORMAT_Pos         8
+#define ARM_SPI_FRAME_FORMAT_Msk        (7UL << ARM_SPI_FRAME_FORMAT_Pos)
+#define ARM_SPI_CPOL0_CPHA0             (0UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 0 (default)
+#define ARM_SPI_CPOL0_CPHA1             (1UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 1
+#define ARM_SPI_CPOL1_CPHA0             (2UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 0
+#define ARM_SPI_CPOL1_CPHA1             (3UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 1
+#define ARM_SPI_TI_SSI                  (4UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Texas Instruments Frame Format
+#define ARM_SPI_MICROWIRE               (5UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< National Microwire Frame Format
+
+/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_SPI_DATA_BITS_Pos            12
+#define ARM_SPI_DATA_BITS_Msk           (0x3FUL << ARM_SPI_DATA_BITS_Pos)
+#define ARM_SPI_DATA_BITS(n)            (((n) & 0x3F) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits
+
+/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
+#define ARM_SPI_BIT_ORDER_Pos            18
+#define ARM_SPI_BIT_ORDER_Msk           (1UL << ARM_SPI_BIT_ORDER_Pos)
+#define ARM_SPI_MSB_LSB                 (0UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from MSB to LSB (default)
+#define ARM_SPI_LSB_MSB                 (1UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from LSB to MSB
+
+/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
+#define ARM_SPI_SS_MASTER_MODE_Pos       19
+#define ARM_SPI_SS_MASTER_MODE_Msk      (3UL << ARM_SPI_SS_MASTER_MODE_Pos)
+#define ARM_SPI_SS_MASTER_UNUSED        (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default)
+#define ARM_SPI_SS_MASTER_SW            (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled
+#define ARM_SPI_SS_MASTER_HW_OUTPUT     (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output
+#define ARM_SPI_SS_MASTER_HW_INPUT      (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input
+#define ARM_SPI_SS_SLAVE_MODE_Pos        21
+#define ARM_SPI_SS_SLAVE_MODE_Msk       (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)
+#define ARM_SPI_SS_SLAVE_HW             (0UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Hardware monitored (default)
+#define ARM_SPI_SS_SLAVE_SW             (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Software controlled
+
+
+/*----- SPI Control Codes: Miscellaneous Controls  -----*/
+#define ARM_SPI_SET_BUS_SPEED           (0x10UL << ARM_SPI_CONTROL_Pos)     ///< Set Bus Speed in bps; arg = value
+#define ARM_SPI_GET_BUS_SPEED           (0x11UL << ARM_SPI_CONTROL_Pos)     ///< Get Bus Speed in bps
+#define ARM_SPI_SET_DEFAULT_TX_VALUE    (0x12UL << ARM_SPI_CONTROL_Pos)     ///< Set default Transmit value; arg = value
+#define ARM_SPI_CONTROL_SS              (0x13UL << ARM_SPI_CONTROL_Pos)     ///< Control Slave Select; arg: 0=inactive, 1=active 
+#define ARM_SPI_ABORT_TRANSFER          (0x14UL << ARM_SPI_CONTROL_Pos)     ///< Abort current data transfer
+
+
+/****** SPI Slave Select Signal definitions *****/
+#define ARM_SPI_SS_INACTIVE              0                                  ///< SPI Slave Select Signal Inactive
+#define ARM_SPI_SS_ACTIVE                1                                  ///< SPI Slave Select Signal Active
+
+
+/****** SPI specific error codes *****/
+#define ARM_SPI_ERROR_MODE              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_SPI_ERROR_FRAME_FORMAT      (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Frame Format not supported
+#define ARM_SPI_ERROR_DATA_BITS         (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_SPI_ERROR_BIT_ORDER         (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported
+#define ARM_SPI_ERROR_SS_MODE           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Slave Select Mode not supported
+
+
+/**
+\brief SPI Status
+*/
+typedef volatile struct _ARM_SPI_STATUS {
+  uint32_t busy       : 1;              ///< Transmitter/Receiver busy flag
+  uint32_t data_lost  : 1;              ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
+  uint32_t mode_fault : 1;              ///< Mode fault detected; optional (cleared on start of transfer operation)
+  uint32_t reserved   : 29;
+} ARM_SPI_STATUS;
+
+
+/****** SPI Event *****/
+#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0)  ///< Data Transfer completed
+#define ARM_SPI_EVENT_DATA_LOST         (1UL << 1)  ///< Data lost: Receive overflow / Transmit underflow
+#define ARM_SPI_EVENT_MODE_FAULT        (1UL << 2)  ///< Master Mode Fault (SS deactivated when Master)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_SPI_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SPI_CAPABILITIES
+
+  \fn          int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)
+  \brief       Initialize SPI Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SPI_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Uninitialize (void)
+  \brief       De-initialize SPI Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control SPI Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Send (const void *data, uint32_t num)
+  \brief       Start sending data to SPI transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SPI transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from SPI receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Transfer (const void *data_out,
+                                               void *data_in,
+                                         uint32_t    num)
+  \brief       Start sending/receiving data to/from SPI transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to SPI transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_SPI_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data items transferred
+
+  \fn          int32_t ARM_SPI_Control (uint32_t control, uint32_t arg)
+  \brief       Control SPI Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref spi_execution_status
+
+  \fn          ARM_SPI_STATUS ARM_SPI_GetStatus (void)
+  \brief       Get SPI status.
+  \return      SPI status \ref ARM_SPI_STATUS
+
+  \fn          void ARM_SPI_SignalEvent (uint32_t event)
+  \brief       Signal SPI Events.
+  \param[in]   event \ref SPI_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event.
+
+
+/**
+\brief SPI Driver Capabilities.
+*/
+typedef struct _ARM_SPI_CAPABILITIES {
+  uint32_t simplex          : 1;        ///< supports Simplex Mode (Master and Slave)
+  uint32_t ti_ssi           : 1;        ///< supports TI Synchronous Serial Interface
+  uint32_t microwire        : 1;        ///< supports Microwire Interface
+  uint32_t event_mode_fault : 1;        ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT
+  uint32_t reserved         : 28;       ///< Reserved (must be zero)
+} ARM_SPI_CAPABILITIES;
+
+
+/**
+\brief Access structure of the SPI Driver.
+*/
+typedef struct _ARM_DRIVER_SPI {
+  ARM_DRIVER_VERSION   (*GetVersion)      (void);                             ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version.
+  ARM_SPI_CAPABILITIES (*GetCapabilities) (void);                             ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)      (ARM_SPI_SignalEvent_t cb_event);   ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface.
+  int32_t              (*Uninitialize)    (void);                             ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface.
+  int32_t              (*PowerControl)    (ARM_POWER_STATE state);            ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power.
+  int32_t              (*Send)            (const void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface.
+  int32_t              (*Receive)         (      void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface.
+  int32_t              (*Transfer)        (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num);                  ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI.
+  uint32_t             (*GetDataCount)    (void);                             ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count.
+  int32_t              (*Control)         (uint32_t control, uint32_t arg);   ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface.
+  ARM_SPI_STATUS       (*GetStatus)       (void);                             ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status.
+} const ARM_DRIVER_SPI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_SPI_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_Storage.h

@@ -0,0 +1,419 @@
+/*
+ * Copyright (c) 2006-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef DRIVER_STORAGE_H_
+#define DRIVER_STORAGE_H_
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1)  /* API version */
+
+
+#define _ARM_Driver_Storage_(n)      Driver_Storage##n
+#define  ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)
+
+#define ARM_STORAGE_INVALID_OFFSET  (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's
+                                                            ///  address space). A storage block may never start at this address.
+
+#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL)          ///< Invalid address within the processor's memory address space.
+                                                            ///  Refer to memory-mapped storage, i.e. \ref ARM_DRIVER_STORAGE::ResolveAddress().
+
+/****** Storage specific error codes *****/
+#define ARM_STORAGE_ERROR_NOT_ERASABLE      (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.
+#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE  (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.
+#define ARM_STORAGE_ERROR_PROTECTED         (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.
+
+/**
+ * \brief Attributes of the storage range within a storage block.
+ */
+typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {
+  uint32_t erasable      :  1;   ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.
+                                 ///   @note if 'erasable' is 0 (i.e. the 'erase' operation isn't available) then
+                                 ///   'erase_unit' (see below) is immaterial and should be 0.
+  uint32_t programmable  :  1;   ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.
+                                 ///    Writes are typically achieved through the ProgramData operation (following an erase);
+                                 ///    if storage isn't erasable (see 'erasable' above) but is memory-mapped
+                                 ///    (i.e. 'memory_mapped'), it can be written directly using memory-store operations.
+  uint32_t executable    :  1;   ///< This storage block can hold program data; the processor can fetch and execute code
+                                 ///    sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO).
+  uint32_t protectable   :  1;   ///< The entire block can be protected from program and erase operations. Once protection
+                                 ///    is enabled for a block, its 'erasable' and 'programmable' bits are turned off.
+  uint32_t reserved      : 28;
+  uint32_t erase_unit;           ///< Minimum erase size in bytes.
+                                 ///    The offset of the start of the erase-range should also be aligned with this value.
+                                 ///    Applicable if the 'erasable' attribute is set for the block.
+                                 ///    @note if 'erasable' (see above) is 0 (i.e. the 'erase' operation isn't available) then
+                                 ///    'erase_unit' is immaterial and should be 0.
+  uint32_t protection_unit;      ///< Minimum protectable size in bytes. Applicable if the 'protectable'
+                                 ///    attribute is set for the block. This should be a divisor of the block's size. A
+                                 ///    block can be considered to be made up of consecutive, individually-protectable fragments.
+} ARM_STORAGE_BLOCK_ATTRIBUTES;
+
+/**
+ * \brief A storage block is a range of memory with uniform attributes.
+ */
+typedef struct _ARM_STORAGE_BLOCK {
+  uint64_t                     addr;       ///< This is the start address of the storage block. It is
+                                           ///    expressed as an offset from the start of the storage map
+                                           ///    maintained by the owning storage controller.
+  uint64_t                     size;       ///< This is the size of the storage block, in units of bytes.
+                                           ///    Together with addr, it describes a range [addr, addr+size).
+  ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.
+} ARM_STORAGE_BLOCK;
+
+/**
+ * The check for a valid ARM_STORAGE_BLOCK.
+ */
+#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))
+
+/**
+ * \brief Values for encoding storage memory-types with respect to programmability.
+ *
+ * Please ensure that the maximum of the following memory types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.
+ */
+#define ARM_STORAGE_PROGRAMMABILITY_RAM       (0x0)
+#define ARM_STORAGE_PROGRAMMABILITY_ROM       (0x1) ///< Read-only memory.
+#define ARM_STORAGE_PROGRAMMABILITY_WORM      (0x2) ///< write-once-read-only-memory (WORM).
+#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE  (0x3) ///< re-programmable based on erase. Supports multiple writes.
+
+/**
+ * Values for encoding data-retention levels for storage blocks.
+ *
+ * Please ensure that the maximum of the following retention types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.
+ */
+#define ARM_RETENTION_WHILE_DEVICE_ACTIVE     (0x0) ///< Data is retained only during device activity.
+#define ARM_RETENTION_ACROSS_SLEEP            (0x1) ///< Data is retained across processor sleep.
+#define ARM_RETENTION_ACROSS_DEEP_SLEEP       (0x2) ///< Data is retained across processor deep-sleep.
+#define ARM_RETENTION_BATTERY_BACKED          (0x3) ///< Data is battery-backed. Device can be powered off.
+#define ARM_RETENTION_NVM                     (0x4) ///< Data is retained in non-volatile memory.
+
+/**
+ * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.
+ */
+typedef struct _ARM_STORAGE_SECURITY_FEATURES {
+  uint32_t acls                :  1; ///< Protection against internal software attacks using ACLs.
+  uint32_t rollback_protection :  1; ///< Roll-back protection. Set to true if the creator of the storage
+                                     ///    can ensure that an external attacker can't force an
+                                     ///    older firmware to run or to revert back to a previous state.
+  uint32_t tamper_proof        :  1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).
+  uint32_t internal_flash      :  1; ///< Internal flash.
+  uint32_t reserved1           : 12;
+
+  /**
+   * Encode support for hardening against various classes of attacks.
+   */
+  uint32_t software_attacks     :  1; ///< device software (malware running on the device).
+  uint32_t board_level_attacks  :  1; ///< board level attacks (debug probes, copy protection fuses.)
+  uint32_t chip_level_attacks   :  1; ///< chip level attacks (tamper-protection).
+  uint32_t side_channel_attacks :  1; ///< side channel attacks.
+  uint32_t reserved2            : 12;
+} ARM_STORAGE_SECURITY_FEATURES;
+
+#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */
+
+/**
+ * Device level metadata regarding the Storage implementation.
+ */
+typedef struct _ARM_STORAGE_INFO {
+  uint64_t                      total_storage;        ///< Total available storage, in bytes.
+  uint32_t                      program_unit;         ///< Minimum programming size in bytes.
+                                                      ///    The offset of the start of the program-range should also be aligned with this value.
+                                                      ///    Applicable only if the 'programmable' attribute is set for a block.
+                                                      ///    @note setting program_unit to 0 has the effect of disabling the size and alignment
+                                                      ///    restrictions (setting it to 1 also has the same effect).
+  uint32_t                      optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers
+                                                      ///    have internal buffers into which to receive data. Writing in chunks of
+                                                      ///    'optimal_program_unit' would achieve maximum programming speed.
+                                                      ///    Applicable only if the 'programmable' attribute is set for the underlying block(s).
+  uint32_t                      program_cycles;       ///< A measure of endurance for reprogramming.
+                                                      ///    Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.
+  uint32_t                      erased_value    :  1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).
+  uint32_t                      memory_mapped   :  1; ///< This storage device has a mapping onto the processor's memory address space.
+                                                      ///    @note For a memory-mapped block which isn't erasable but is programmable (i.e. if
+                                                      ///    'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to
+                                                      ///    the memory-mapped storage without going through the ProgramData operation.
+  uint32_t                      programmability :  4; ///< A value to indicate storage programmability.
+  uint32_t                      retention_level :  4;
+  uint32_t                      reserved        : 22;
+  ARM_STORAGE_SECURITY_FEATURES security;             ///< \ref ARM_STORAGE_SECURITY_FEATURES
+} ARM_STORAGE_INFO;
+
+/**
+\brief Operating status of the storage controller.
+*/
+typedef volatile struct _ARM_STORAGE_STATUS {
+  uint32_t busy     : 1;                ///< Controller busy flag
+  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)
+  uint32_t reserved : 30;
+} ARM_STORAGE_STATUS;
+
+/**
+ * \brief Storage Driver API Capabilities.
+ */
+typedef struct _ARM_STORAGE_CAPABILITIES {
+  uint32_t asynchronous_ops :  1; ///< Used to indicate if APIs like initialize,
+                                  ///    read, erase, program, etc. can operate in asynchronous mode.
+                                  ///    Setting this bit to 1 means that the driver is capable
+                                  ///    of launching asynchronous operations; command completion is
+                                  ///    signaled by the invocation of a completion callback. If
+                                  ///    set to 1, drivers may still complete asynchronous
+                                  ///    operations synchronously as necessary (in which case they
+                                  ///    return a positive error code to indicate synchronous completion).
+  uint32_t erase_all        :  1; ///< Supports EraseAll operation.
+  uint32_t reserved         : 30; ///< Reserved (must be zero)
+} ARM_STORAGE_CAPABILITIES;
+
+/**
+ * Command opcodes for Storage.
+ */
+typedef enum _ARM_STORAGE_OPERATION {
+  ARM_STORAGE_OPERATION_GET_VERSION,
+  ARM_STORAGE_OPERATION_GET_CAPABILITIES,
+  ARM_STORAGE_OPERATION_INITIALIZE,
+  ARM_STORAGE_OPERATION_UNINITIALIZE,
+  ARM_STORAGE_OPERATION_POWER_CONTROL,
+  ARM_STORAGE_OPERATION_READ_DATA,
+  ARM_STORAGE_OPERATION_PROGRAM_DATA,
+  ARM_STORAGE_OPERATION_ERASE,
+  ARM_STORAGE_OPERATION_ERASE_ALL,
+  ARM_STORAGE_OPERATION_GET_STATUS,
+  ARM_STORAGE_OPERATION_GET_INFO,
+  ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,
+  ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,
+  ARM_STORAGE_OPERATION_GET_BLOCK
+} ARM_STORAGE_OPERATION;
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_Storage_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_STORAGE_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback)
+  \brief       Initialize the Storage interface.
+  \param [in]  callback Pointer to \ref ARM_Storage_Callback_t.
+               Caller-defined callback to be invoked upon command completion
+               for asynchronous APIs (including the completion of
+               initialization). Use a NULL pointer when no callback
+               signals are required.
+  \return      If asynchronous activity is launched, invocation
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with a status value of ARM_DRIVER_OK or an error-code. In the
+               case of synchronous execution, control returns after completion with a
+               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_Uninitialize (void)
+  \brief       De-initialize the Storage Interface.
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with a status value of ARM_DRIVER_OK or an error-code. In the
+               case of synchronous execution, control returns after completion with a
+               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)
+  \brief       Control the Storage interface power.
+  \param[in]   state  Power state
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with a status value of ARM_DRIVER_OK or an error-code. In the
+               case of synchronous execution, control returns after completion with a
+               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size)
+  \brief       Read data from Storage.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Storage.
+  \param[in]   size  Number of bytes to read. The data buffer
+               should be at least as large as this size.
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with the number of successfully transferred bytes passed in as
+               the 'status' parameter. In the case of synchronous execution, control
+               returns after completion with a positive transfer-count. Return values
+               less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size)
+  \brief       Program data to Storage.
+  \param [in] addr This is the start address of the range to be written into. It
+               needs to be aligned to the device's \em program_unit
+               specified in \ref ARM_STORAGE_INFO.
+  \param [in] data The source of the write operation. The buffer is owned by the
+               caller and should remain accessible for the lifetime of this
+               command.
+  \param [in] size The number of bytes requested to be written. The buffer
+               should be at least as large as this size. \note 'size' should
+               be a multiple of the device's 'program_unit' (see \ref
+               ARM_STORAGE_INFO).
+  \return      If asynchronous activity is launched, an invocation returns
+               ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+               future with the number of successfully transferred bytes passed in as
+               the 'status' parameter. In the case of synchronous execution, control
+               returns after completion with a positive transfer-count. Return values
+               less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size)
+  \brief       Erase Storage range.
+  \param [in]  addr This is the start-address of the range to be erased. It must
+               start at an 'erase_unit' boundary of the underlying block.
+  \param [in]  size Size (in bytes) of the range to be erased. 'addr + size'
+               must be aligned with the 'erase_unit' of the underlying
+               block.
+  \return      If the range to be erased doesn't align with the erase_units of the
+               respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is
+               returned. If any part of the range is protected,
+               ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the range
+               is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All
+               such sanity-check failures result in the error code being
+               returned synchronously and the storage bytes within the range
+               remain unaffected. Otherwise the function executes in the
+               following ways: If asynchronous activity is launched, an
+               invocation returns ARM_DRIVER_OK, and the caller can expect to
+               receive a callback in the future with the number of successfully
+               erased bytes passed in as the 'status' parameter. In the case of
+               synchronous execution, control returns after completion with a
+               positive erase-count. Return values less than ARM_DRIVER_OK (0)
+               signify errors.
+*/
+/**
+  \fn          int32_t ARM_Storage_EraseAll (void)
+  \brief       Erase complete Storage.
+  \return      If any part of the storage range is protected,
+               ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the
+               storage range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is
+               returned. All such sanity-check failures result in the error code
+               being returned synchronously and the storage bytes within the
+               range remain unaffected. Otherwise the function executes in the
+               following ways: If asynchronous activity is launched, an
+               invocation returns ARM_DRIVER_OK, and the caller can expect to
+               receive a callback in the future with ARM_DRIVER_OK passed in as
+               the 'status' parameter. In the case of synchronous execution,
+               control returns after completion with a value of 1. Return values
+               less than ARM_DRIVER_OK (0) signify errors.
+*/
+/**
+  \fn          ARM_STORAGE_STATUS ARM_Storage_GetStatus (void)
+  \brief       Get Storage status.
+  \return      Storage status \ref ARM_STORAGE_STATUS
+*/
+/**
+  \fn          int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info)
+  \brief       Get Storage information.
+  \param[out]  info  A caller-supplied buffer capable of being filled in with an \ref ARM_STORAGE_INFO.
+  \return      ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level
+               metadata about the storage controller is filled into the supplied
+               buffer, else an appropriate error value.
+*/
+/**
+  \fn          uint32_t ARM_Storage_ResolveAddress(uint64_t addr)
+  \brief       Resolve an address relative to the storage controller into a memory address.
+  \param[in]   addr The address for which we want a resolution to the processor's physical address space. It is an offset from the
+               start of the storage map maintained by the owning storage
+               controller.
+  \return      The resolved address in the processor's address space, else ARM_STORAGE_INVALID_ADDRESS.
+*/
+/**
+  \fn          int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);
+  \brief       Advance to the successor of the current block (iterator).
+  \param[in]   prev_block An existing block (iterator) within the same storage
+               controller. The memory buffer holding this block is owned
+               by the caller. This pointer may be NULL; if so, the
+               invocation fills in the first block into the out parameter:
+               'next_block'.
+  \param[out]  next_block A caller-owned buffer large enough to be filled in with
+               the following ARM_STORAGE_BLOCK. It is legal to provide the
+               same buffer using 'next_block' as was passed in with 'prev_block'. It
+               is also legal to pass a NULL into this parameter if the
+               caller isn't interested in populating a buffer with the next
+               block, i.e. if the caller only wishes to establish the
+               presence of a next block.
+  \return      ARM_DRIVER_OK if a valid next block is found (or first block, if
+               prev_block is passed as NULL); upon successful operation, the contents
+               of the next (or first) block are filled into the buffer pointed to by
+               the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is
+               guaranteed to be true. Upon reaching the end of the sequence of blocks
+               (iterators), or in case the driver is unable to fetch information about
+               the next (or first) block, an error (negative) value is returned and an
+               invalid StorageBlock is populated into the supplied buffer. If
+               prev_block is NULL, the first block is returned.
+*/
+/**
+  \fn          int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block);
+  \brief       Find the storage block (iterator) encompassing a given storage address.
+  \param[in]   addr Storage address in bytes.
+  \param[out]  block A caller-owned buffer large enough to be filled in with the
+               ARM_STORAGE_BLOCK encapsulating the given address. This value
+               can also be passed in as NULL if the caller isn't interested
+               in populating a buffer with the block, if the caller only
+               wishes to establish the presence of a containing storage
+               block.
+  \return      ARM_DRIVER_OK if a containing storage-block is found. In this case,
+               if block is non-NULL, the buffer pointed to by it is populated with
+               the contents of the storage block, i.e. if block is valid and a block is
+               found, ARM_STORAGE_VALID_BLOCK(block) would return true following this
+               call. If there is no storage block containing the given offset, or in
+               case the driver is unable to resolve an address to a storage-block, an
+               error (negative) value is returned and an invalid StorageBlock is
+               populated into the supplied buffer.
+*/
+
+/**
+ * Provides the typedef for the callback function \ref ARM_Storage_Callback_t.
+ */
+typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);
+
+/**
+ * The set of operations constituting the Storage driver.
+ */
+typedef struct _ARM_DRIVER_STORAGE {
+  ARM_DRIVER_VERSION       (*GetVersion)     (void);                                           ///< Pointer to \ref ARM_Storage_GetVersion : Get driver version.
+  ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);                                           ///< Pointer to \ref ARM_Storage_GetCapabilities : Get driver capabilities.
+  int32_t                  (*Initialize)     (ARM_Storage_Callback_t callback);                ///< Pointer to \ref ARM_Storage_Initialize : Initialize the Storage Interface.
+  int32_t                  (*Uninitialize)   (void);                                           ///< Pointer to \ref ARM_Storage_Uninitialize : De-initialize the Storage Interface.
+  int32_t                  (*PowerControl)   (ARM_POWER_STATE state);                          ///< Pointer to \ref ARM_Storage_PowerControl : Control the Storage interface power.
+  int32_t                  (*ReadData)       (uint64_t addr, void *data, uint32_t size);       ///< Pointer to \ref ARM_Storage_ReadData : Read data from Storage.
+  int32_t                  (*ProgramData)    (uint64_t addr, const void *data, uint32_t size); ///< Pointer to \ref ARM_Storage_ProgramData : Program data to Storage.
+  int32_t                  (*Erase)          (uint64_t addr, uint32_t size);                   ///< Pointer to \ref ARM_Storage_Erase : Erase Storage range.
+  int32_t                  (*EraseAll)       (void);                                           ///< Pointer to \ref ARM_Storage_EraseAll : Erase complete Storage.
+  ARM_STORAGE_STATUS       (*GetStatus)      (void);                                           ///< Pointer to \ref ARM_Storage_GetStatus : Get Storage status.
+  int32_t                  (*GetInfo)        (ARM_STORAGE_INFO *info);                         ///< Pointer to \ref ARM_Storage_GetInfo : Get Storage information.
+  uint32_t                 (*ResolveAddress) (uint64_t addr);                                  ///< Pointer to \ref ARM_Storage_ResolveAddress : Resolve a storage address.
+  int32_t                  (*GetNextBlock)   (const ARM_STORAGE_BLOCK* prev, ARM_STORAGE_BLOCK *next); ///< Pointer to \ref ARM_Storage_GetNextBlock : fetch successor for current block.
+  int32_t                  (*GetBlock)       (uint64_t addr, ARM_STORAGE_BLOCK *block);        ///< Pointer to \ref ARM_Storage_GetBlock :
+} const ARM_DRIVER_STORAGE;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_STORAGE_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_USART.h

@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.3
+ *
+ * Project:      USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ *               Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
+ *  Version 2.2
+ *    Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions 
+ *  Version 2.1
+ *    Removed optional argument parameter from Signal Event
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *      renamed driver UART -> USART (Asynchronous & Synchronous)
+ *    Added modes:
+ *      Synchronous
+ *      Single-wire
+ *      IrDA
+ *      Smart Card  
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added events:
+ *      ARM_UART_EVENT_TX_EMPTY,     ARM_UART_EVENT_RX_TIMEOUT
+ *      ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
+ *    Added functions: SetTxThreshold, SetRxThreshold
+ *    Added "rx_timeout_event" to capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USART_H_
+#define DRIVER_USART_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+/****** USART Control Codes *****/
+
+#define ARM_USART_CONTROL_Pos                0
+#define ARM_USART_CONTROL_Msk               (0xFFUL << ARM_USART_CONTROL_Pos)
+
+/*----- USART Control Codes: Mode -----*/
+#define ARM_USART_MODE_ASYNCHRONOUS         (0x01UL << ARM_USART_CONTROL_Pos)   ///< UART (Asynchronous); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_MASTER   (0x02UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Master (generates clock signal); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_SLAVE    (0x03UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Slave (external clock signal)
+#define ARM_USART_MODE_SINGLE_WIRE          (0x04UL << ARM_USART_CONTROL_Pos)   ///< UART Single-wire (half-duplex); arg = Baudrate
+#define ARM_USART_MODE_IRDA                 (0x05UL << ARM_USART_CONTROL_Pos)   ///< UART IrDA; arg = Baudrate
+#define ARM_USART_MODE_SMART_CARD           (0x06UL << ARM_USART_CONTROL_Pos)   ///< UART Smart Card; arg = Baudrate
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_USART_DATA_BITS_Pos              8
+#define ARM_USART_DATA_BITS_Msk             (7UL << ARM_USART_DATA_BITS_Pos)
+#define ARM_USART_DATA_BITS_5               (5UL << ARM_USART_DATA_BITS_Pos)    ///< 5 Data bits
+#define ARM_USART_DATA_BITS_6               (6UL << ARM_USART_DATA_BITS_Pos)    ///< 6 Data bit
+#define ARM_USART_DATA_BITS_7               (7UL << ARM_USART_DATA_BITS_Pos)    ///< 7 Data bits
+#define ARM_USART_DATA_BITS_8               (0UL << ARM_USART_DATA_BITS_Pos)    ///< 8 Data bits (default)
+#define ARM_USART_DATA_BITS_9               (1UL << ARM_USART_DATA_BITS_Pos)    ///< 9 Data bits
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+#define ARM_USART_PARITY_Pos                 12
+#define ARM_USART_PARITY_Msk                (3UL << ARM_USART_PARITY_Pos)
+#define ARM_USART_PARITY_NONE               (0UL << ARM_USART_PARITY_Pos)       ///< No Parity (default)
+#define ARM_USART_PARITY_EVEN               (1UL << ARM_USART_PARITY_Pos)       ///< Even Parity
+#define ARM_USART_PARITY_ODD                (2UL << ARM_USART_PARITY_Pos)       ///< Odd Parity
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+#define ARM_USART_STOP_BITS_Pos              14
+#define ARM_USART_STOP_BITS_Msk             (3UL << ARM_USART_STOP_BITS_Pos)
+#define ARM_USART_STOP_BITS_1               (0UL << ARM_USART_STOP_BITS_Pos)    ///< 1 Stop bit (default)
+#define ARM_USART_STOP_BITS_2               (1UL << ARM_USART_STOP_BITS_Pos)    ///< 2 Stop bits
+#define ARM_USART_STOP_BITS_1_5             (2UL << ARM_USART_STOP_BITS_Pos)    ///< 1.5 Stop bits
+#define ARM_USART_STOP_BITS_0_5             (3UL << ARM_USART_STOP_BITS_Pos)    ///< 0.5 Stop bits
+
+/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
+#define ARM_USART_FLOW_CONTROL_Pos           16
+#define ARM_USART_FLOW_CONTROL_Msk          (3UL << ARM_USART_FLOW_CONTROL_Pos)
+#define ARM_USART_FLOW_CONTROL_NONE         (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
+#define ARM_USART_FLOW_CONTROL_RTS          (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
+#define ARM_USART_FLOW_CONTROL_CTS          (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
+#define ARM_USART_FLOW_CONTROL_RTS_CTS      (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+#define ARM_USART_CPOL_Pos                   18
+#define ARM_USART_CPOL_Msk                  (1UL << ARM_USART_CPOL_Pos)
+#define ARM_USART_CPOL0                     (0UL << ARM_USART_CPOL_Pos)         ///< CPOL = 0 (default)
+#define ARM_USART_CPOL1                     (1UL << ARM_USART_CPOL_Pos)         ///< CPOL = 1
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+#define ARM_USART_CPHA_Pos                   19
+#define ARM_USART_CPHA_Msk                  (1UL << ARM_USART_CPHA_Pos)
+#define ARM_USART_CPHA0                     (0UL << ARM_USART_CPHA_Pos)         ///< CPHA = 0 (default)
+#define ARM_USART_CPHA1                     (1UL << ARM_USART_CPHA_Pos)         ///< CPHA = 1
+
+
+/*----- USART Control Codes: Miscellaneous Controls  -----*/
+#define ARM_USART_SET_DEFAULT_TX_VALUE      (0x10UL << ARM_USART_CONTROL_Pos)   ///< Set default Transmit value (Synchronous Receive only); arg = value
+#define ARM_USART_SET_IRDA_PULSE            (0x11UL << ARM_USART_CONTROL_Pos)   ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period  
+#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Guard Time; arg = number of bit periods
+#define ARM_USART_SET_SMART_CARD_CLOCK      (0x13UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
+#define ARM_USART_CONTROL_SMART_CARD_NACK   (0x14UL << ARM_USART_CONTROL_Pos)   ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_TX                (0x15UL << ARM_USART_CONTROL_Pos)   ///< Transmitter; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_RX                (0x16UL << ARM_USART_CONTROL_Pos)   ///< Receiver; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_BREAK             (0x17UL << ARM_USART_CONTROL_Pos)   ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
+#define ARM_USART_ABORT_SEND                (0x18UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Send
+#define ARM_USART_ABORT_RECEIVE             (0x19UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Receive
+#define ARM_USART_ABORT_TRANSFER            (0x1AUL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Transfer
+
+
+
+/****** USART specific error codes *****/
+#define ARM_USART_ERROR_MODE                (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_USART_ERROR_BAUDRATE            (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified baudrate not supported
+#define ARM_USART_ERROR_DATA_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_USART_ERROR_PARITY              (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Parity not supported
+#define ARM_USART_ERROR_STOP_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified number of Stop bits not supported
+#define ARM_USART_ERROR_FLOW_CONTROL        (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Flow Control not supported
+#define ARM_USART_ERROR_CPOL                (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock Polarity not supported
+#define ARM_USART_ERROR_CPHA                (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Clock Phase not supported
+
+
+/**
+\brief USART Status
+*/
+typedef volatile struct _ARM_USART_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t rx_break         : 1;        ///< Break detected on receive (cleared on start of next receive operation)
+  uint32_t rx_framing_error : 1;        ///< Framing error detected on receive (cleared on start of next receive operation)
+  uint32_t rx_parity_error  : 1;        ///< Parity error detected on receive (cleared on start of next receive operation)
+  uint32_t reserved         : 25;
+} ARM_USART_STATUS;
+
+/**
+\brief USART Modem Control
+*/
+typedef enum _ARM_USART_MODEM_CONTROL {
+  ARM_USART_RTS_CLEAR,                  ///< Deactivate RTS
+  ARM_USART_RTS_SET,                    ///< Activate RTS
+  ARM_USART_DTR_CLEAR,                  ///< Deactivate DTR
+  ARM_USART_DTR_SET                     ///< Activate DTR
+} ARM_USART_MODEM_CONTROL;
+
+/**
+\brief USART Modem Status
+*/
+typedef volatile struct _ARM_USART_MODEM_STATUS {
+  uint32_t cts      : 1;                ///< CTS state: 1=Active, 0=Inactive
+  uint32_t dsr      : 1;                ///< DSR state: 1=Active, 0=Inactive
+  uint32_t dcd      : 1;                ///< DCD state: 1=Active, 0=Inactive
+  uint32_t ri       : 1;                ///< RI  state: 1=Active, 0=Inactive
+  uint32_t reserved : 28;
+} ARM_USART_MODEM_STATUS;
+
+
+/****** USART Event *****/
+#define ARM_USART_EVENT_SEND_COMPLETE       (1UL << 0)  ///< Send completed; however USART may still transmit data
+#define ARM_USART_EVENT_RECEIVE_COMPLETE    (1UL << 1)  ///< Receive completed
+#define ARM_USART_EVENT_TRANSFER_COMPLETE   (1UL << 2)  ///< Transfer completed
+#define ARM_USART_EVENT_TX_COMPLETE         (1UL << 3)  ///< Transmit completed (optional)
+#define ARM_USART_EVENT_TX_UNDERFLOW        (1UL << 4)  ///< Transmit data not available (Synchronous Slave)
+#define ARM_USART_EVENT_RX_OVERFLOW         (1UL << 5)  ///< Receive data overflow
+#define ARM_USART_EVENT_RX_TIMEOUT          (1UL << 6)  ///< Receive character timeout (optional)
+#define ARM_USART_EVENT_RX_BREAK            (1UL << 7)  ///< Break detected on receive
+#define ARM_USART_EVENT_RX_FRAMING_ERROR    (1UL << 8)  ///< Framing error detected on receive
+#define ARM_USART_EVENT_RX_PARITY_ERROR     (1UL << 9)  ///< Parity error detected on receive
+#define ARM_USART_EVENT_CTS                 (1UL << 10) ///< CTS state changed (optional)
+#define ARM_USART_EVENT_DSR                 (1UL << 11) ///< DSR state changed (optional)
+#define ARM_USART_EVENT_DCD                 (1UL << 12) ///< DCD state changed (optional)
+#define ARM_USART_EVENT_RI                  (1UL << 13) ///< RI  state changed (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
+  \brief       Get driver capabilities
+  \return      \ref ARM_USART_CAPABILITIES
+
+  \fn          int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
+  \brief       Initialize USART Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_USART_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Uninitialize (void)
+  \brief       De-initialize USART Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USART Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Send (const void *data, uint32_t num)
+  \brief       Start sending data to USART transmitter.
+  \param[in]   data  Pointer to buffer with data to send to USART transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from USART receiver.
+  \param[out]  data  Pointer to buffer for data to receive from USART receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Transfer (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num)
+  \brief       Start sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_USART_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_USART_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
+  \brief       Control USART Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref usart_execution_status
+
+  \fn          ARM_USART_STATUS ARM_USART_GetStatus (void)
+  \brief       Get USART status.
+  \return      USART status \ref ARM_USART_STATUS
+
+  \fn          int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
+  \brief       Set USART Modem Control line state.
+  \param[in]   control  \ref ARM_USART_MODEM_CONTROL
+  \return      \ref execution_status 
+
+  \fn          ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
+  \brief       Get USART Modem Status lines state.
+  \return      modem status \ref ARM_USART_MODEM_STATUS
+
+  \fn          void ARM_USART_SignalEvent (uint32_t event)
+  \brief       Signal USART Events.
+  \param[in]   event  \ref USART_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_USART_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
+
+
+/**
+\brief USART Device Driver Capabilities.
+*/
+typedef struct _ARM_USART_CAPABILITIES {
+  uint32_t asynchronous       : 1;      ///< supports UART (Asynchronous) mode 
+  uint32_t synchronous_master : 1;      ///< supports Synchronous Master mode
+  uint32_t synchronous_slave  : 1;      ///< supports Synchronous Slave mode
+  uint32_t single_wire        : 1;      ///< supports UART Single-wire mode
+  uint32_t irda               : 1;      ///< supports UART IrDA mode
+  uint32_t smart_card         : 1;      ///< supports UART Smart Card mode
+  uint32_t smart_card_clock   : 1;      ///< Smart Card Clock generator available
+  uint32_t flow_control_rts   : 1;      ///< RTS Flow Control available
+  uint32_t flow_control_cts   : 1;      ///< CTS Flow Control available
+  uint32_t event_tx_complete  : 1;      ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+  uint32_t event_rx_timeout   : 1;      ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+  uint32_t rts                : 1;      ///< RTS Line: 0=not available, 1=available
+  uint32_t cts                : 1;      ///< CTS Line: 0=not available, 1=available
+  uint32_t dtr                : 1;      ///< DTR Line: 0=not available, 1=available
+  uint32_t dsr                : 1;      ///< DSR Line: 0=not available, 1=available
+  uint32_t dcd                : 1;      ///< DCD Line: 0=not available, 1=available
+  uint32_t ri                 : 1;      ///< RI Line: 0=not available, 1=available
+  uint32_t event_cts          : 1;      ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
+  uint32_t event_dsr          : 1;      ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
+  uint32_t event_dcd          : 1;      ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
+  uint32_t event_ri           : 1;      ///< Signal RI change event: \ref ARM_USART_EVENT_RI
+  uint32_t reserved           : 11;     ///< Reserved (must be zero)
+} ARM_USART_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USART Driver.
+*/
+typedef struct _ARM_DRIVER_USART {
+  ARM_DRIVER_VERSION     (*GetVersion)      (void);                              ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
+  ARM_USART_CAPABILITIES (*GetCapabilities) (void);                              ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)      (ARM_USART_SignalEvent_t cb_event);  ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
+  int32_t                (*Uninitialize)    (void);                              ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
+  int32_t                (*PowerControl)    (ARM_POWER_STATE state);             ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
+  int32_t                (*Send)            (const void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
+  int32_t                (*Receive)         (      void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
+  int32_t                (*Transfer)        (const void *data_out,
+                                                   void *data_in,
+                                             uint32_t    num);                   ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
+  uint32_t               (*GetTxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
+  uint32_t               (*GetRxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
+  int32_t                (*Control)         (uint32_t control, uint32_t arg);    ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
+  ARM_USART_STATUS       (*GetStatus)       (void);                              ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
+  int32_t                (*SetModemControl) (ARM_USART_MODEM_CONTROL control);   ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
+  ARM_USART_MODEM_STATUS (*GetModemStatus)  (void);                              ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
+} const ARM_DRIVER_USART;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USART_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_USB.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.0
+ *
+ * Project:      USB Driver common definitions
+ */
+
+/* History:
+ *  Version 2.0
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added PID Types
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USB_H_
+#define DRIVER_USB_H_
+
+#include "Driver_Common.h"
+
+/* USB Role */
+#define ARM_USB_ROLE_NONE               (0)
+#define ARM_USB_ROLE_HOST               (1)
+#define ARM_USB_ROLE_DEVICE             (2)
+
+/* USB Pins */
+#define ARM_USB_PIN_DP                  (1 << 0) ///< USB D+ pin
+#define ARM_USB_PIN_DM                  (1 << 1) ///< USB D- pin
+#define ARM_USB_PIN_VBUS                (1 << 2) ///< USB VBUS pin
+#define ARM_USB_PIN_OC                  (1 << 3) ///< USB OverCurrent pin
+#define ARM_USB_PIN_ID                  (1 << 4) ///< USB ID pin
+
+/* USB Speed */
+#define ARM_USB_SPEED_LOW               (0)      ///< Low-speed USB
+#define ARM_USB_SPEED_FULL              (1)      ///< Full-speed USB
+#define ARM_USB_SPEED_HIGH              (2)      ///< High-speed USB
+
+/* USB PID Types */
+#define ARM_USB_PID_OUT                 (1)
+#define ARM_USB_PID_IN                  (9)
+#define ARM_USB_PID_SOF                 (5)
+#define ARM_USB_PID_SETUP               (13)
+#define ARM_USB_PID_DATA0               (3)
+#define ARM_USB_PID_DATA1               (11)
+#define ARM_USB_PID_DATA2               (7)
+#define ARM_USB_PID_MDATA               (15)
+#define ARM_USB_PID_ACK                 (2)
+#define ARM_USB_PID_NAK                 (10)
+#define ARM_USB_PID_STALL               (14)
+#define ARM_USB_PID_NYET                (6)
+#define ARM_USB_PID_PRE                 (12)
+#define ARM_USB_PID_ERR                 (12)
+#define ARM_USB_PID_SPLIT               (8)
+#define ARM_USB_PID_PING                (4)
+#define ARM_USB_PID_RESERVED            (0)
+
+/* USB Endpoint Address (bEndpointAddress) */
+#define ARM_USB_ENDPOINT_NUMBER_MASK    (0x0F)
+#define ARM_USB_ENDPOINT_DIRECTION_MASK (0x80)
+
+/* USB Endpoint Type */
+#define ARM_USB_ENDPOINT_CONTROL        (0)      ///< Control Endpoint
+#define ARM_USB_ENDPOINT_ISOCHRONOUS    (1)      ///< Isochronous Endpoint
+#define ARM_USB_ENDPOINT_BULK           (2)      ///< Bulk Endpoint
+#define ARM_USB_ENDPOINT_INTERRUPT      (3)      ///< Interrupt Endpoint
+
+/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */
+#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK           (0x07FF)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK   (0x1800)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1      (0x0000)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2      (0x0800)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3      (0x1000)
+
+#endif /* DRIVER_USB_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_USBD.h

@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.2
+ *
+ * Project:      USB Device Driver definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    ARM_USBD_STATE made volatile
+ *  Version 2.1
+ *    Added ARM_USBD_ReadSetupPacket function
+ *  Version 2.0
+ *    Removed ARM_USBD_DeviceConfigure function
+ *    Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function
+ *    Removed ARM_USBD_EndpointReadStart function
+ *    Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer
+ *    Added ARM_USBD_EndpointTransferGetResult function
+ *    Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USBD_H_
+#define DRIVER_USBD_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_USB.h"
+
+#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+/**
+\brief USB Device State
+*/
+typedef volatile struct _ARM_USBD_STATE {
+  uint32_t vbus     : 1;                ///< USB Device VBUS flag
+  uint32_t speed    : 2;                ///< USB Device speed setting (ARM_USB_SPEED_xxx)
+  uint32_t active   : 1;                ///< USB Device active flag
+  uint32_t reserved : 28;
+} ARM_USBD_STATE;
+
+
+/****** USB Device Event *****/
+#define ARM_USBD_EVENT_VBUS_ON          (1UL << 0)      ///< USB Device VBUS On
+#define ARM_USBD_EVENT_VBUS_OFF         (1UL << 1)      ///< USB Device VBUS Off
+#define ARM_USBD_EVENT_RESET            (1UL << 2)      ///< USB Reset occurred
+#define ARM_USBD_EVENT_HIGH_SPEED       (1UL << 3)      ///< USB switch to High Speed occurred
+#define ARM_USBD_EVENT_SUSPEND          (1UL << 4)      ///< USB Suspend occurred
+#define ARM_USBD_EVENT_RESUME           (1UL << 5)      ///< USB Resume occurred
+
+/****** USB Endpoint Event *****/
+#define ARM_USBD_EVENT_SETUP            (1UL << 0)      ///< SETUP Packet
+#define ARM_USBD_EVENT_OUT              (1UL << 1)      ///< OUT Packet(s)
+#define ARM_USBD_EVENT_IN               (1UL << 2)      ///< IN Packet(s)
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBD_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBD_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                            ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+  \brief       Initialize USB Device Interface.
+  \param[in]   cb_device_event    Pointer to \ref ARM_USBD_SignalDeviceEvent
+  \param[in]   cb_endpoint_event  Pointer to \ref ARM_USBD_SignalEndpointEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_Uninitialize (void)
+  \brief       De-initialize USB Device Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Device Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceConnect (void)
+  \brief       Connect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceDisconnect (void)
+  \brief       Disconnect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBD_STATE ARM_USBD_DeviceGetState (void)
+  \brief       Get current USB Device State.
+  \return      Device State \ref ARM_USBD_STATE
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceRemoteWakeup (void)
+  \brief       Trigger USB Remote Wakeup.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr)
+  \brief       Set USB Device Address.
+  \param[in]   dev_addr  Device Address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup)
+  \brief       Read setup packet received over Control Endpoint.
+  \param[out]  setup  Pointer to buffer for setup packet
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointConfigure (uint8_t  ep_addr,
+                                                   uint8_t  ep_type,
+                                                   uint16_t ep_max_packet_size)
+  \brief       Configure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type  Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr)
+  \brief       Unconfigure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall)
+  \brief       Set/Clear Stall for USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   stall  Operation
+                - \b false Clear
+                - \b true Set
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
+  \brief       Read data from or Write data to USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[out]  data Pointer to buffer for data to read or with data to write
+  \param[in]   num  Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr)
+  \brief       Get result of USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      number of successfully transferred data bytes
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr)
+  \brief       Abort current USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBD_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBD_SignalDeviceEvent (uint32_t event)
+  \brief       Signal USB Device Event.
+  \param[in]   event \ref USBD_dev_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event)
+  \brief       Signal USB Endpoint Event.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   event \ref USBD_ep_events
+  \return      none
+*/
+
+typedef void (*ARM_USBD_SignalDeviceEvent_t)   (uint32_t event);                    ///< Pointer to \ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event.
+typedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event);   ///< Pointer to \ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event.
+
+
+/**
+\brief USB Device Driver Capabilities.
+*/
+typedef struct _ARM_USBD_CAPABILITIES {
+  uint32_t vbus_detection  : 1;         ///< VBUS detection
+  uint32_t event_vbus_on   : 1;         ///< Signal VBUS On event
+  uint32_t event_vbus_off  : 1;         ///< Signal VBUS Off event
+  uint32_t reserved        : 29;        ///< Reserved (must be zero)
+} ARM_USBD_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USB Device Driver.
+*/
+typedef struct _ARM_DRIVER_USBD {
+  ARM_DRIVER_VERSION    (*GetVersion)                (void);                                              ///< Pointer to \ref ARM_USBD_GetVersion : Get driver version.
+  ARM_USBD_CAPABILITIES (*GetCapabilities)           (void);                                              ///< Pointer to \ref ARM_USBD_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)                (ARM_USBD_SignalDeviceEvent_t   cb_device_event,                     
+                                                      ARM_USBD_SignalEndpointEvent_t cb_endpoint_event);  ///< Pointer to \ref ARM_USBD_Initialize : Initialize USB Device Interface. 
+  int32_t               (*Uninitialize)              (void);                                              ///< Pointer to \ref ARM_USBD_Uninitialize : De-initialize USB Device Interface.
+  int32_t               (*PowerControl)              (ARM_POWER_STATE state);                             ///< Pointer to \ref ARM_USBD_PowerControl : Control USB Device Interface Power.
+  int32_t               (*DeviceConnect)             (void);                                              ///< Pointer to \ref ARM_USBD_DeviceConnect : Connect USB Device.
+  int32_t               (*DeviceDisconnect)          (void);                                              ///< Pointer to \ref ARM_USBD_DeviceDisconnect : Disconnect USB Device.
+  ARM_USBD_STATE        (*DeviceGetState)            (void);                                              ///< Pointer to \ref ARM_USBD_DeviceGetState : Get current USB Device State.
+  int32_t               (*DeviceRemoteWakeup)        (void);                                              ///< Pointer to \ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup.
+  int32_t               (*DeviceSetAddress)          (uint8_t dev_addr);                                  ///< Pointer to \ref ARM_USBD_DeviceSetAddress : Set USB Device Address.
+  int32_t               (*ReadSetupPacket)           (uint8_t *setup);                                    ///< Pointer to \ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint.
+  int32_t               (*EndpointConfigure)         (uint8_t ep_addr,
+                                                      uint8_t ep_type,
+                                                      uint16_t ep_max_packet_size);                       ///< Pointer to \ref ARM_USBD_EndpointConfigure : Configure USB Endpoint.
+  int32_t               (*EndpointUnconfigure)       (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.
+  int32_t               (*EndpointStall)             (uint8_t ep_addr, bool stall);                       ///< Pointer to \ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.
+  int32_t               (*EndpointTransfer)          (uint8_t ep_addr, uint8_t *data, uint32_t num);      ///< Pointer to \ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint.
+  uint32_t              (*EndpointTransferGetResult) (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer.
+  int32_t               (*EndpointTransferAbort)     (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer.
+  uint16_t              (*GetFrameNumber)            (void);                                              ///< Pointer to \ref ARM_USBD_GetFrameNumber : Get current USB Frame Number.
+} const ARM_DRIVER_USBD;
+
+#endif /* __DOXYGEN_MW__ */
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USBD_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_USBH.h

@@ -0,0 +1,417 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+  *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.2
+ *
+ * Project:      USB Host Driver definitions
+*/
+
+/* History:
+ *  Version 2.2
+ *    ARM_USBH_PORT_STATE made volatile
+ *  Version 2.1
+ *    Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE
+ *    Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe...
+ *    Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent
+ *  Version 2.0
+ *    Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff
+ *    Changed function ARM_USBH_EndpointCreate parameters
+ *    Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify
+ *    Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset
+ *    Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer
+ *    Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort
+ *    Added function ARM_USBH_EndpointTransferGetResult
+ *    Added function ARM_USBH_GetFrameNumber
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.20
+ *    Added API for OHCI/EHCI Host Controller Interface (HCI)
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USBH_H_
+#define DRIVER_USBH_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_USB.h"
+
+#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+/**
+\brief USB Host Port State
+*/
+typedef volatile struct _ARM_USBH_PORT_STATE {
+  uint32_t connected   : 1;             ///< USB Host Port connected flag
+  uint32_t overcurrent : 1;             ///< USB Host Port overcurrent flag
+  uint32_t speed       : 2;             ///< USB Host Port speed setting (ARM_USB_SPEED_xxx)
+  uint32_t reserved    : 28;
+} ARM_USBH_PORT_STATE;
+
+/**
+\brief USB Host Pipe Handle
+*/
+typedef uint32_t ARM_USBH_PIPE_HANDLE;
+#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE  /* Legacy name */
+
+
+/****** USB Host Packet Information *****/
+#define ARM_USBH_PACKET_TOKEN_Pos         0
+#define ARM_USBH_PACKET_TOKEN_Msk        (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos)
+#define ARM_USBH_PACKET_SETUP            (0x01UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< SETUP Packet
+#define ARM_USBH_PACKET_OUT              (0x02UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< OUT Packet
+#define ARM_USBH_PACKET_IN               (0x03UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< IN Packet
+#define ARM_USBH_PACKET_PING             (0x04UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< PING Packet
+
+#define ARM_USBH_PACKET_DATA_Pos          4
+#define ARM_USBH_PACKET_DATA_Msk         (0x0FUL << ARM_USBH_PACKET_DATA_Pos)
+#define ARM_USBH_PACKET_DATA0            (0x01UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA0 PID
+#define ARM_USBH_PACKET_DATA1            (0x02UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA1 PID
+
+#define ARM_USBH_PACKET_SPLIT_Pos         8
+#define ARM_USBH_PACKET_SPLIT_Msk        (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos)
+#define ARM_USBH_PACKET_SSPLIT           (0x08UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet
+#define ARM_USBH_PACKET_SSPLIT_S         (0x09UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data Start
+#define ARM_USBH_PACKET_SSPLIT_E         (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data End
+#define ARM_USBH_PACKET_SSPLIT_S_E       (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data All
+#define ARM_USBH_PACKET_CSPLIT           (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< CSPLIT Packet
+
+#define ARM_USBH_PACKET_PRE              (1UL << 12)                            ///< PRE Token
+
+
+/****** USB Host Port Event *****/
+#define ARM_USBH_EVENT_CONNECT           (1UL << 0)     ///< USB Device Connected to Port
+#define ARM_USBH_EVENT_DISCONNECT        (1UL << 1)     ///< USB Device Disconnected from Port
+#define ARM_USBH_EVENT_OVERCURRENT       (1UL << 2)     ///< USB Device caused Overcurrent
+#define ARM_USBH_EVENT_RESET             (1UL << 3)     ///< USB Reset completed
+#define ARM_USBH_EVENT_SUSPEND           (1UL << 4)     ///< USB Suspend occurred
+#define ARM_USBH_EVENT_RESUME            (1UL << 5)     ///< USB Resume occurred
+#define ARM_USBH_EVENT_REMOTE_WAKEUP     (1UL << 6)     ///< USB Device activated Remote Wakeup
+
+/****** USB Host Pipe Event *****/
+#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0)     ///< Transfer completed
+#define ARM_USBH_EVENT_HANDSHAKE_NAK     (1UL << 1)     ///< NAK Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_NYET    (1UL << 2)     ///< NYET Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_MDATA   (1UL << 3)     ///< MDATA Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_STALL   (1UL << 4)     ///< STALL Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_ERR     (1UL << 5)     ///< ERR Handshake received
+#define ARM_USBH_EVENT_BUS_ERROR         (1UL << 6)     ///< Bus Error detected
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event,
+                                            ARM_USBH_SignalPipeEvent_t cb_pipe_event)
+  \brief       Initialize USB Host Interface.
+  \param[in]   cb_port_event  Pointer to \ref ARM_USBH_SignalPortEvent
+  \param[in]   cb_pipe_event  Pointer to \ref ARM_USBH_SignalPipeEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_Uninitialize (void)
+  \brief       De-initialize USB Host Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortReset (uint8_t port)
+  \brief       Do Root HUB Port Reset.
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortSuspend (uint8_t port)
+  \brief       Suspend Root HUB Port (stop generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortResume (uint8_t port)
+  \brief       Resume Root HUB Port (start generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port)
+  \brief       Get current Root HUB Port State.
+  \param[in]   port  Root HUB Port Number
+  \return      Port State \ref ARM_USBH_PORT_STATE
+*/
+/**
+  \fn          ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t  dev_addr,
+                                                         uint8_t  dev_speed,
+                                                         uint8_t  hub_addr,
+                                                         uint8_t  hub_port,
+                                                         uint8_t  ep_addr,
+                                                         uint8_t  ep_type,
+                                                         uint16_t ep_max_packet_size,
+                                                         uint8_t  ep_interval)
+  \brief       Create Pipe in System.
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_addr    Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type    Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \param[in]   ep_interval        Endpoint Polling Interval
+  \return      Pipe Handle \ref ARM_USBH_PIPE_HANDLE
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                            uint8_t              dev_addr,
+                                            uint8_t              dev_speed,
+                                            uint8_t              hub_addr,
+                                            uint8_t              hub_port,
+                                            uint16_t             ep_max_packet_size)
+  \brief       Modify Pipe in System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Delete Pipe from System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Reset Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                              uint32_t             packet,
+                                              uint8_t             *data,
+                                              uint32_t             num)
+  \brief       Transfer packets through USB Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   packet     Packet information
+  \param[in]   data       Pointer to buffer with data to send or for data to receive
+  \param[in]   num        Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Get result of USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      number of successfully transferred data bytes
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Abort current USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBH_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event)
+  \brief       Signal Root HUB Port Event.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   event \ref USBH_port_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)
+  \brief       Signal Pipe Event.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   event  \ref USBH_pipe_events
+  \return      none
+*/
+
+typedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event);                    ///< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event.
+typedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event);  ///< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event.
+#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t  /* Legacy name */
+
+
+/**
+\brief USB Host Driver Capabilities.
+*/
+typedef struct _ARM_USBH_CAPABILITIES {
+  uint32_t port_mask          : 15;     ///< Root HUB available Ports Mask
+  uint32_t auto_split         :  1;     ///< Automatic SPLIT packet handling
+  uint32_t event_connect      :  1;     ///< Signal Connect event
+  uint32_t event_disconnect   :  1;     ///< Signal Disconnect event
+  uint32_t event_overcurrent  :  1;     ///< Signal Overcurrent event
+  uint32_t reserved           : 13;     ///< Reserved (must be zero)
+} ARM_USBH_CAPABILITIES;
+
+
+/**
+\brief Access structure of USB Host Driver.
+*/
+typedef struct _ARM_DRIVER_USBH {
+  ARM_DRIVER_VERSION    (*GetVersion)            (void);                                     ///< Pointer to \ref ARM_USBH_GetVersion : Get driver version.
+  ARM_USBH_CAPABILITIES (*GetCapabilities)       (void);                                     ///< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)            (ARM_USBH_SignalPortEvent_t cb_port_event,            
+                                                  ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface.
+  int32_t               (*Uninitialize)          (void);                                     ///< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface.
+  int32_t               (*PowerControl)          (ARM_POWER_STATE state);                    ///< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power.
+  int32_t               (*PortVbusOnOff)         (uint8_t port, bool vbus);                  ///< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off.
+  int32_t               (*PortReset)             (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset.
+  int32_t               (*PortSuspend)           (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs).
+  int32_t               (*PortResume)            (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs).
+  ARM_USBH_PORT_STATE   (*PortGetState)          (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State.
+  ARM_USBH_PIPE_HANDLE  (*PipeCreate)            (uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint8_t ep_addr,
+                                                  uint8_t ep_type,
+                                                  uint16_t ep_max_packet_size,
+                                                  uint8_t ep_interval);                      ///< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System.
+  int32_t               (*PipeModify)            (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                                  uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint16_t ep_max_packet_size);              ///< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System.
+  int32_t               (*PipeDelete)            (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System.
+  int32_t               (*PipeReset)             (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe.
+  int32_t               (*PipeTransfer)          (ARM_USBH_PIPE_HANDLE pipe_hndl, 
+                                                  uint32_t packet,
+                                                  uint8_t *data,
+                                                  uint32_t num);                             ///< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe.
+  uint32_t              (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer.
+  int32_t               (*PipeTransferAbort)     (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer.
+  uint16_t              (*GetFrameNumber)        (void);                                     ///< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number.                    
+} const ARM_DRIVER_USBH;
+
+
+// HCI (OHCI/EHCI)
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void)
+  \brief       Get USB Host HCI (OHCI/EHCI) driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_HCI_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)
+  \brief       Initialize USB Host HCI (OHCI/EHCI) Interface.
+  \param[in]   cb_interrupt Pointer to Interrupt Handler Routine
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Uninitialize (void)
+  \brief       De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host HCI (OHCI/EHCI) Interface Power.
+  \param[in]   state Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_USBH_HCI_Interrupt (void)
+  \brief       USB Host HCI Interrupt Handler.
+  \return      none
+*/
+
+typedef void (*ARM_USBH_HCI_Interrupt_t) (void);  ///< Pointer to Interrupt Handler Routine.
+
+
+/**
+\brief USB Host HCI (OHCI/EHCI) Driver Capabilities.
+*/
+typedef struct _ARM_USBH_HCI_CAPABILITIES {
+  uint32_t port_mask : 15;              ///< Root HUB available Ports Mask
+  uint32_t reserved  : 17;              ///< Reserved (must be zero)
+} ARM_USBH_HCI_CAPABILITIES;
+
+
+/**
+  \brief Access structure of USB Host HCI (OHCI/EHCI) Driver.
+*/
+typedef struct _ARM_DRIVER_USBH_HCI {
+  ARM_DRIVER_VERSION        (*GetVersion)      (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version.
+  ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities.
+  int32_t                   (*Initialize)      (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*Uninitialize)    (void);                                  ///< Pointer to \ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*PowerControl)    (ARM_POWER_STATE state);                 ///< Pointer to \ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power.
+  int32_t                   (*PortVbusOnOff)   (uint8_t port, bool vbus);               ///< Pointer to \ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+} const ARM_DRIVER_USBH_HCI;
+
+#endif /* __DOXYGEN_MW__ */
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USBH_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/CMSIS/Driver/Include/Driver_WiFi.h

@@ -0,0 +1,659 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        31. May 2019
+ * $Revision:    V1.0
+ *
+ * Project:      WiFi (Wireless Fidelity Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_WIFI_H_
+#define DRIVER_WIFI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_WIFI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)  /* API version */
+
+#define _ARM_Driver_WiFi_(n)      Driver_WiFi##n
+#define  ARM_Driver_WiFi_(n) _ARM_Driver_WiFi_(n)
+
+
+/****** WiFi SetOption/GetOption Function Option Codes *****/
+#define ARM_WIFI_BSSID                      1U          ///< Station/AP Set/Get BSSID of AP to connect or of AP;        data = &bssid,    len =  6, uint8_t[6]
+#define ARM_WIFI_TX_POWER                   2U          ///< Station/AP Set/Get transmit power;                         data = &power,    len =  4, uint32_t: 0 .. 20 [dBm]
+#define ARM_WIFI_LP_TIMER                   3U          ///< Station    Set/Get low-power deep-sleep time;              data = &time,     len =  4, uint32_t [seconds]: 0 = disable (default)
+#define ARM_WIFI_DTIM                       4U          ///< Station/AP Set/Get DTIM interval;                          data = &dtim,     len =  4, uint32_t [beacons]
+#define ARM_WIFI_BEACON                     5U          ///<         AP Set/Get beacon interval;                        data = &interval, len =  4, uint32_t [ms]
+#define ARM_WIFI_MAC                        6U          ///< Station/AP Set/Get MAC;                                    data = &mac,      len =  6, uint8_t[6]
+#define ARM_WIFI_IP                         7U          ///< Station/AP Set/Get IPv4 static/assigned address;           data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_SUBNET_MASK             8U          ///< Station/AP Set/Get IPv4 subnet mask;                       data = &mask,     len =  4, uint8_t[4]
+#define ARM_WIFI_IP_GATEWAY                 9U          ///< Station/AP Set/Get IPv4 gateway address;                   data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DNS1                    10U         ///< Station/AP Set/Get IPv4 primary   DNS address;             data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DNS2                    11U         ///< Station/AP Set/Get IPv4 secondary DNS address;             data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DHCP                    12U         ///< Station/AP Set/Get IPv4 DHCP client/server enable/disable; data = &dhcp,     len =  4, uint32_t: 0 = disable, non-zero = enable (default)
+#define ARM_WIFI_IP_DHCP_POOL_BEGIN         13U         ///<         AP Set/Get IPv4 DHCP pool begin address;           data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DHCP_POOL_END           14U         ///<         AP Set/Get IPv4 DHCP pool end address;             data = &ip,       len =  4, uint8_t[4]
+#define ARM_WIFI_IP_DHCP_LEASE_TIME         15U         ///<         AP Set/Get IPv4 DHCP lease time;                   data = &time,     len =  4, uint32_t [seconds]
+#define ARM_WIFI_IP6_GLOBAL                 16U         ///< Station/AP Set/Get IPv6 global address;                    data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_LINK_LOCAL             17U         ///< Station/AP Set/Get IPv6 link local address;                data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_SUBNET_PREFIX_LEN      18U         ///< Station/AP Set/Get IPv6 subnet prefix length;              data = &len,      len =  4, uint32_t: 1 .. 127
+#define ARM_WIFI_IP6_GATEWAY                19U         ///< Station/AP Set/Get IPv6 gateway address;                   data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_DNS1                   20U         ///< Station/AP Set/Get IPv6 primary   DNS address;             data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_DNS2                   21U         ///< Station/AP Set/Get IPv6 secondary DNS address;             data = &ip6,      len = 16, uint8_t[16]
+#define ARM_WIFI_IP6_DHCP_MODE              22U         ///< Station/AP Set/Get IPv6 DHCPv6 client mode;                data = &mode,     len =  4, uint32_t: ARM_WIFI_IP6_DHCP_xxx (default Off)
+
+/****** WiFi Security Type *****/
+#define ARM_WIFI_SECURITY_OPEN              0U          ///< Open
+#define ARM_WIFI_SECURITY_WEP               1U          ///< Wired Equivalent Privacy (WEP) with Pre-Sheared Key (PSK)
+#define ARM_WIFI_SECURITY_WPA               2U          ///< WiFi Protected Access (WPA) with PSK
+#define ARM_WIFI_SECURITY_WPA2              3U          ///< WiFi Protected Access II (WPA2) with PSK
+#define ARM_WIFI_SECURITY_UNKNOWN           255U        ///< Unknown
+
+/****** WiFi Protected Setup (WPS) Method *****/
+#define ARM_WIFI_WPS_METHOD_NONE            0U          ///< Not used
+#define ARM_WIFI_WPS_METHOD_PBC             1U          ///< Push Button Configuration
+#define ARM_WIFI_WPS_METHOD_PIN             2U          ///< PIN
+
+/****** WiFi IPv6 Dynamic Host Configuration Protocol (DHCP) Mode *****/
+#define ARM_WIFI_IP6_DHCP_OFF               0U          ///< Static Host Configuration (default)
+#define ARM_WIFI_IP6_DHCP_STATELESS         1U          ///< Dynamic Host Configuration stateless DHCPv6
+#define ARM_WIFI_IP6_DHCP_STATEFULL         2U          ///< Dynamic Host Configuration statefull DHCPv6
+
+/****** WiFi Event *****/
+#define ARM_WIFI_EVENT_AP_CONNECT          (1UL << 0)   ///< Access Point: Station has connected;           arg = &mac, mac (uint8_t[6])
+#define ARM_WIFI_EVENT_AP_DISCONNECT       (1UL << 1)   ///< Access Point: Station has disconnected;        arg = &mac, mac (uint8_t[6])
+#define ARM_WIFI_EVENT_ETH_RX_FRAME        (1UL << 4)   ///< Ethernet Frame Received (in bypass mode only); arg = interface (0 = Station, 1 = Access Point)
+
+
+/**
+\brief WiFi Configuration
+*/
+typedef struct {
+  const char   *ssid;                                   ///< Pointer to Service Set Identifier (SSID) null-terminated string
+  const char   *pass;                                   ///< Pointer to Password null-terminated string
+        uint8_t security;                               ///< Security type (ARM_WIFI_SECURITY_xxx)
+        uint8_t ch;                                     ///< WiFi Channel (0 = auto, otherwise = exact channel)
+        uint8_t reserved;                               ///< Reserved
+        uint8_t wps_method;                             ///< WiFi Protected Setup (WPS) method (ARM_WIFI_WPS_METHOD_xxx)
+  const char   *wps_pin;                                ///< Pointer to WiFi Protected Setup (WPS) PIN null-terminated string
+} ARM_WIFI_CONFIG_t;
+
+/**
+\brief WiFi Scan Information
+*/
+typedef struct {
+  char    ssid[32+1];                                   ///< Service Set Identifier (SSID) null-terminated string
+  uint8_t bssid[6];                                     ///< Basic Service Set Identifier (BSSID)
+  uint8_t security;                                     ///< Security type (ARM_WIFI_SECURITY_xxx)
+  uint8_t ch;                                           ///< WiFi Channel
+  uint8_t rssi;                                         ///< Received Signal Strength Indicator
+} ARM_WIFI_SCAN_INFO_t;
+
+/**
+\brief WiFi Network Information
+*/
+typedef struct {
+  char    ssid[32+1];                                   ///< Service Set Identifier (SSID) null-terminated string
+  char    pass[64+1];                                   ///< Password null-terminated string
+  uint8_t security;                                     ///< Security type (ARM_WIFI_SECURITY_xxx)
+  uint8_t ch;                                           ///< WiFi Channel
+  uint8_t rssi;                                         ///< Received Signal Strength Indicator
+} ARM_WIFI_NET_INFO_t;
+
+/****** Socket Address Family definitions *****/
+#define ARM_SOCKET_AF_INET                  1           ///< IPv4
+#define ARM_SOCKET_AF_INET6                 2           ///< IPv6
+
+/****** Socket Type definitions *****/
+#define ARM_SOCKET_SOCK_STREAM              1           ///< Stream socket
+#define ARM_SOCKET_SOCK_DGRAM               2           ///< Datagram socket
+
+/****** Socket Protocol definitions *****/
+#define ARM_SOCKET_IPPROTO_TCP              1           ///< TCP
+#define ARM_SOCKET_IPPROTO_UDP              2           ///< UDP
+
+/****** Socket Option definitions *****/
+#define ARM_SOCKET_IO_FIONBIO               1           ///< Non-blocking I/O (Set only, default = 0); opt_val = &nbio, opt_len = sizeof(nbio), nbio (integer): 0=blocking, non-blocking otherwise
+#define ARM_SOCKET_SO_RCVTIMEO              2           ///< Receive timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout)
+#define ARM_SOCKET_SO_SNDTIMEO              3           ///< Send timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout)
+#define ARM_SOCKET_SO_KEEPALIVE             4           ///< Keep-alive messages (default = 0); opt_val = &keepalive, opt_len = sizeof(keepalive), keepalive (integer): 0=disabled, enabled otherwise
+#define ARM_SOCKET_SO_TYPE                  5           ///< Socket Type (Get only); opt_val = &socket_type, opt_len = sizeof(socket_type), socket_type (integer): ARM_SOCKET_SOCK_xxx
+
+/****** Socket Function return codes *****/
+#define ARM_SOCKET_ERROR                   (-1)         ///< Unspecified error
+#define ARM_SOCKET_ESOCK                   (-2)         ///< Invalid socket
+#define ARM_SOCKET_EINVAL                  (-3)         ///< Invalid argument
+#define ARM_SOCKET_ENOTSUP                 (-4)         ///< Operation not supported
+#define ARM_SOCKET_ENOMEM                  (-5)         ///< Not enough memory
+#define ARM_SOCKET_EAGAIN                  (-6)         ///< Operation would block or timed out
+#define ARM_SOCKET_EINPROGRESS             (-7)         ///< Operation in progress
+#define ARM_SOCKET_ETIMEDOUT               (-8)         ///< Operation timed out
+#define ARM_SOCKET_EISCONN                 (-9)         ///< Socket is connected
+#define ARM_SOCKET_ENOTCONN                (-10)        ///< Socket is not connected
+#define ARM_SOCKET_ECONNREFUSED            (-11)        ///< Connection rejected by the peer
+#define ARM_SOCKET_ECONNRESET              (-12)        ///< Connection reset by the peer
+#define ARM_SOCKET_ECONNABORTED            (-13)        ///< Connection aborted locally
+#define ARM_SOCKET_EALREADY                (-14)        ///< Connection already in progress
+#define ARM_SOCKET_EADDRINUSE              (-15)        ///< Address in use
+#define ARM_SOCKET_EHOSTNOTFOUND           (-16)        ///< Host not found
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_WIFI_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_WIFI_CAPABILITIES ARM_WIFI_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_WIFI_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_WIFI_Initialize (ARM_WIFI_SignalEvent_t cb_event)
+  \brief         Initialize WiFi Module.
+  \param[in]     cb_event Pointer to \ref ARM_WIFI_SignalEvent_t
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+*/
+/**
+  \fn            int32_t ARM_WIFI_Uninitialize (void)
+  \brief         De-initialize WiFi Module.
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+*/
+/**
+  \fn            int32_t ARM_WIFI_PowerControl (ARM_POWER_STATE state)
+  \brief         Control WiFi Module Power.
+  \param[in]     state     Power state
+                   - \ref ARM_POWER_OFF                : Power off: no operation possible
+                   - \ref ARM_POWER_LOW                : Low-power mode: sleep or deep-sleep depending on \ref ARM_WIFI_LP_TIMER option set
+                   - \ref ARM_POWER_FULL               : Power on: full operation at maximum performance
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid state)
+*/
+/**
+  \fn            int32_t ARM_WIFI_GetModuleInfo (char *module_info, uint32_t max_len)
+  \brief         Get Module information.
+  \param[out]    module_info Pointer to character buffer were info string will be returned
+  \param[in]     max_len     Maximum length of string to return (including null terminator)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL module_info pointer or max_len equals to 0)
+*/
+/**
+  \fn            int32_t ARM_WIFI_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len)
+  \brief         Set WiFi Module Options.
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     option    Option to set
+  \param[in]     data      Pointer to data relevant to selected option
+  \param[in]     len       Length of data (in bytes)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL data pointer or len less than option specifies)
+*/
+/**
+  \fn            int32_t ARM_WIFI_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len)
+  \brief         Get WiFi Module Options.
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     option    Option to get
+  \param[out]    data      Pointer to memory where data for selected option will be returned
+  \param[in,out] len       Pointer to length of data (input/output)
+                   - input: maximum length of data that can be returned (in bytes)
+                   - output: length of returned data (in bytes)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL data or len pointer, or *len less than option specifies)
+*/
+/**
+  \fn            int32_t ARM_WIFI_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num)
+  \brief         Scan for available networks in range.
+  \param[out]    scan_info Pointer to array of ARM_WIFI_SCAN_INFO_t structures where available Scan Information will be returned
+  \param[in]     max_num   Maximum number of Network Information structures to return
+  \return        number of ARM_WIFI_SCAN_INFO_t structures returned or error code
+                   - value >= 0                        : Number of ARM_WIFI_SCAN_INFO_t structures returned
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL scan_info pointer or max_num equal to 0)
+*/
+/**
+  \fn            int32_t ARM_WIFI_Activate (uint32_t interface, ARM_WIFI_CONFIG_t *config)
+  \brief         Activate interface (Connect to a wireless network or activate an access point).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     config    Pointer to ARM_WIFI_CONFIG_t structure where Configuration parameters are located
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_TIMEOUT     : Timeout occurred
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported (security type, channel autodetect or WPS not supported)
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL config pointer or invalid configuration)
+*/
+/**
+  \fn            int32_t ARM_WIFI_Deactivate (uint32_t interface)
+  \brief         Deactivate interface (Disconnect from a wireless network or deactivate an access point).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface)
+*/
+/**
+  \fn            uint32_t ARM_WIFI_IsConnected (void)
+  \brief         Get station connection status.
+  \return        station connection status
+                   - value != 0: Station connected
+                   - value = 0: Station not connected
+*/
+/**
+  \fn            int32_t ARM_WIFI_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info)
+  \brief         Get station Network Information.
+  \param[out]    net_info  Pointer to ARM_WIFI_NET_INFO_t structure where station Network Information will be returned
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed (station not connected)
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL net_info pointer)
+*/
+/**
+  \fn            int32_t ARM_WIFI_BypassControl (uint32_t interface, uint32_t mode)
+  \brief         Enable or disable bypass (pass-through) mode. Transmit and receive Ethernet frames (IP layer bypassed and WiFi/Ethernet translation).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     mode
+                   - value = 1: all packets bypass internal IP stack
+                   - value = 0: all packets processed by internal IP stack
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or mode)
+*/
+/**
+  \fn            int32_t ARM_WIFI_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len)
+  \brief         Send Ethernet frame (in bypass mode only).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     frame    Pointer to frame buffer with data to send
+  \param[in]     len      Frame buffer length in bytes
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_BUSY        : Driver is busy
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL frame pointer)
+*/
+/**
+  \fn            int32_t ARM_WIFI_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len)
+  \brief         Read data of received Ethernet frame (in bypass mode only).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \param[in]     frame    Pointer to frame buffer for data to read into
+  \param[in]     len      Frame buffer length in bytes
+  \return        number of data bytes read or error code
+                   - value >= 0                        : Number of data bytes read
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL frame pointer)
+*/
+/**
+  \fn            uint32_t ARM_WIFI_EthGetRxFrameSize (uint32_t interface)
+  \brief         Get size of received Ethernet frame (in bypass mode only).
+  \param[in]     interface Interface (0 = Station, 1 = Access Point)
+  \return        number of bytes in received frame
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketCreate (int32_t af, int32_t type, int32_t protocol)
+  \brief         Create a communication socket.
+  \param[in]     af       Address family
+  \param[in]     type     Socket type
+  \param[in]     protocol Socket protocol
+  \return        status information
+                   - Socket identification number (>=0)
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ENOMEM            : Not enough memory
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)
+  \brief         Assign a local address to a socket.
+  \param[in]     socket   Socket identification number
+  \param[in]     ip       Pointer to local IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \param[in]     port     Local port number
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (address or socket already bound)
+                   - \ref ARM_SOCKET_EADDRINUSE        : Address already in use
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketListen (int32_t socket, int32_t backlog)
+  \brief         Listen for socket connections.
+  \param[in]     socket   Socket identification number
+  \param[in]     backlog  Number of connection requests that can be queued
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (socket not bound)
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_EISCONN           : Socket is already connected
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Accept a new connection on a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    ip       Pointer to buffer where address of connecting socket shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where port of connecting socket shall be returned (NULL for none)
+  \return        status information
+                   - socket identification number of accepted socket (>=0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (socket not in listen mode)
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported (socket type does not support accepting connections)
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)
+  \brief         Connect a socket to a remote host.
+  \param[in]     socket   Socket identification number
+  \param[in]     ip       Pointer to remote IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \param[in]     port     Remote port number
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_EALREADY          : Connection already in progress
+                   - \ref ARM_SOCKET_EINPROGRESS       : Operation in progress
+                   - \ref ARM_SOCKET_EISCONN           : Socket is connected
+                   - \ref ARM_SOCKET_ECONNREFUSED      : Connection rejected by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EADDRINUSE        : Address already in use
+                   - \ref ARM_SOCKET_ETIMEDOUT         : Operation timed out
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketRecv (int32_t socket, void *buf, uint32_t len)
+  \brief         Receive data on a connected socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    buf      Pointer to buffer where data should be stored
+  \param[in]     len      Length of buffer (in bytes)
+  \return        status information
+                   - number of bytes received (>0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Receive data on a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    buf      Pointer to buffer where data should be stored
+  \param[in]     len      Length of buffer (in bytes)
+  \param[out]    ip       Pointer to buffer where remote source address shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where remote source port shall be returned (NULL for none)
+  \return        status information
+                   - number of bytes received (>0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketSend (int32_t socket, const void *buf, uint32_t len)
+  \brief         Send data on a connected socket.
+  \param[in]     socket   Socket identification number
+  \param[in]     buf      Pointer to buffer containing data to send
+  \param[in]     len      Length of data (in bytes)
+  \return        status information
+                   - number of bytes sent (>0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port)
+  \brief         Send data on a socket.
+  \param[in]     socket   Socket identification number
+  \param[in]     buf      Pointer to buffer containing data to send
+  \param[in]     len      Length of data (in bytes)
+  \param[in]     ip       Pointer to remote destination IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \param[in]     port     Remote destination port number
+  \return        status information
+                   - number of bytes sent (>0)
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer
+                   - \ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Retrieve local IP address and port of a socket.
+  \param[in]     socket   Socket identification number
+  \param[out]    ip       Pointer to buffer where local address shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where local port shall be returned (NULL for none)
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)
+  \brief         Retrieve remote IP address and port of a socket
+  \param[in]     socket   Socket identification number
+  \param[out]    ip       Pointer to buffer where remote address shall be returned (NULL for none)
+  \param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \param[out]    port     Pointer to buffer where remote port shall be returned (NULL for none)
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)
+                   - \ref ARM_SOCKET_ENOTCONN          : Socket is not connected
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len)
+  \brief         Get socket option.
+  \param[in]     socket   Socket identification number
+  \param[in]     opt_id   Option identifier
+  \param[out]    opt_val  Pointer to the buffer that will receive the option value
+  \param[in,out] opt_len  Pointer to length of the option value
+                   - length of buffer on input
+                   - length of data on output
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len)
+  \brief         Set socket option.
+  \param[in]     socket   Socket identification number
+  \param[in]     opt_id   Option identifier
+  \param[in]     opt_val  Pointer to the option value
+  \param[in]     opt_len  Length of the option value in bytes
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketClose (int32_t socket)
+  \brief         Close and release a socket.
+  \param[in]     socket   Socket identification number
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_ESOCK             : Invalid socket
+                   - \ref ARM_SOCKET_EAGAIN            : Operation would block (may be called again)
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len)
+  \brief         Retrieve host IP address from host name.
+  \param[in]     name     Host name
+  \param[in]     af       Address family
+  \param[out]    ip       Pointer to buffer where resolved IP address shall be returned
+  \param[in,out] ip_len   Pointer to length of 'ip'
+                   - length of supplied 'ip' on input
+                   - length of stored 'ip' on output
+  \return        status information
+                   - 0                                 : Operation successful
+                   - \ref ARM_SOCKET_EINVAL            : Invalid argument
+                   - \ref ARM_SOCKET_ENOTSUP           : Operation not supported
+                   - \ref ARM_SOCKET_ETIMEDOUT         : Operation timed out
+                   - \ref ARM_SOCKET_EHOSTNOTFOUND     : Host not found
+                   - \ref ARM_SOCKET_ERROR             : Unspecified error
+*/
+/**
+  \fn            int32_t ARM_WIFI_Ping (const uint8_t *ip, uint32_t ip_len)
+  \brief         Probe remote host with Ping command.
+  \param[in]     ip       Pointer to remote host IP address
+  \param[in]     ip_len   Length of 'ip' address in bytes
+  \return        execution status
+                   - \ref ARM_DRIVER_OK                : Operation successful
+                   - \ref ARM_DRIVER_ERROR             : Operation failed
+                   - \ref ARM_DRIVER_ERROR_TIMEOUT     : Timeout occurred
+                   - \ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported
+                   - \ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL ip pointer or ip_len different than 4 or 16)
+*/
+/**
+  \fn            void ARM_WIFI_SignalEvent (uint32_t event, void *arg)
+  \brief         Signal WiFi Events.
+  \param[in]     event    \ref wifi_event notification mask
+  \param[in]     arg      Pointer to argument of signaled event
+  \return        none
+*/
+
+typedef void (*ARM_WIFI_SignalEvent_t) (uint32_t event, void *arg); ///< Pointer to \ref ARM_WIFI_SignalEvent : Signal WiFi Event.
+
+
+/**
+\brief WiFi Driver Capabilities.
+*/
+typedef struct {
+  uint32_t station               : 1;   ///< Station
+  uint32_t ap                    : 1;   ///< Access Point
+  uint32_t station_ap            : 1;   ///< Concurrent Station and Access Point
+  uint32_t wps_station           : 1;   ///< WiFi Protected Setup (WPS) for Station
+  uint32_t wps_ap                : 1;   ///< WiFi Protected Setup (WPS) for Access Point
+  uint32_t event_ap_connect      : 1;   ///< Access Point: event generated on Station connect
+  uint32_t event_ap_disconnect   : 1;   ///< Access Point: event generated on Station disconnect
+  uint32_t event_eth_rx_frame    : 1;   ///< Event generated on Ethernet frame reception in bypass mode
+  uint32_t bypass_mode           : 1;   ///< Bypass or pass-through mode (Ethernet interface)
+  uint32_t ip                    : 1;   ///< IP (UDP/TCP) (Socket interface)
+  uint32_t ip6                   : 1;   ///< IPv6 (Socket interface)
+  uint32_t ping                  : 1;   ///< Ping (ICMP)
+  uint32_t reserved              : 20;  ///< Reserved (must be zero)
+} ARM_WIFI_CAPABILITIES;
+
+/**
+\brief Access structure of the WiFi Driver.
+*/
+typedef struct {
+  ARM_DRIVER_VERSION    (*GetVersion)                  (void);
+  ARM_WIFI_CAPABILITIES (*GetCapabilities)             (void);
+  int32_t               (*Initialize)                  (ARM_WIFI_SignalEvent_t cb_event);
+  int32_t               (*Uninitialize)                (void);
+  int32_t               (*PowerControl)                (ARM_POWER_STATE state);
+  int32_t               (*GetModuleInfo)               (char *module_info, uint32_t max_len);
+  int32_t               (*SetOption)                   (uint32_t interface, uint32_t option, const void *data, uint32_t  len);
+  int32_t               (*GetOption)                   (uint32_t interface, uint32_t option,       void *data, uint32_t *len);
+  int32_t               (*Scan)                        (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num);
+  int32_t               (*Activate)                    (uint32_t interface, const ARM_WIFI_CONFIG_t *config);
+  int32_t               (*Deactivate)                  (uint32_t interface);
+  uint32_t              (*IsConnected)                 (void);
+  int32_t               (*GetNetInfo)                  (ARM_WIFI_NET_INFO_t *net_info);
+  int32_t               (*BypassControl)               (uint32_t interface, uint32_t mode);
+  int32_t               (*EthSendFrame)                (uint32_t interface, const uint8_t *frame, uint32_t len);
+  int32_t               (*EthReadFrame)                (uint32_t interface,       uint8_t *frame, uint32_t len);
+  uint32_t              (*EthGetRxFrameSize)           (uint32_t interface);
+  int32_t               (*SocketCreate)                (int32_t af, int32_t type, int32_t protocol);
+  int32_t               (*SocketBind)                  (int32_t socket, const uint8_t *ip, uint32_t  ip_len, uint16_t  port);
+  int32_t               (*SocketListen)                (int32_t socket, int32_t backlog);
+  int32_t               (*SocketAccept)                (int32_t socket,       uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketConnect)               (int32_t socket, const uint8_t *ip, uint32_t  ip_len, uint16_t  port);
+  int32_t               (*SocketRecv)                  (int32_t socket, void *buf, uint32_t len);
+  int32_t               (*SocketRecvFrom)              (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketSend)                  (int32_t socket, const void *buf, uint32_t len);
+  int32_t               (*SocketSendTo)                (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port);
+  int32_t               (*SocketGetSockName)           (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketGetPeerName)           (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port);
+  int32_t               (*SocketGetOpt)                (int32_t socket, int32_t opt_id,       void *opt_val, uint32_t *opt_len);
+  int32_t               (*SocketSetOpt)                (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t  opt_len);
+  int32_t               (*SocketClose)                 (int32_t socket);
+  int32_t               (*SocketGetHostByName)         (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len);
+  int32_t               (*Ping)                        (const uint8_t *ip, uint32_t ip_len);
+} const ARM_DRIVER_WIFI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_WIFI_H_ */

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/LICENSE.txt

@@ -0,0 +1,201 @@
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drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/README.md

@@ -0,0 +1,2 @@
+# cmsis
+CMSIS Driver API

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/cmsis/manifest

@@ -0,0 +1,50 @@
+pdsc: ARM.CMSIS.pdsc
+preproc:
+ - clean: CMSIS/Documentation/(Core,Core_A,DAP,Driver,DSP,NN,General,Pack,RTOS,RTOS2,SVD,Zone)
+ - doxygen: CMSIS/DoxyGen/Core/core.dxy
+ - doxygen: CMSIS/DoxyGen/Core_A/core_A.dxy
+ - doxygen: CMSIS/DoxyGen/DAP/dap.dxy
+ - doxygen: CMSIS/DoxyGen/Driver/Driver.dxy
+ - doxygen: CMSIS/DoxyGen/DSP/dsp.dxy
+ - doxygen: CMSIS/DoxyGen/General/general.dxy
+ - doxygen: CMSIS/DoxyGen/NN/nn.dxy
+ - doxygen: CMSIS/DoxyGen/Pack/Pack.dxy
+ - doxygen: CMSIS/DoxyGen/RTOS/rtos.dxy
+ - doxygen: CMSIS/DoxyGen/RTOS2/rtos.dxy
+ - doxygen: CMSIS/DoxyGen/SVD/svd.dxy
+ - doxygen: CMSIS/DoxyGen/Zone/zone.dxy
+glob:
+ - LICENSE.txt
+ - Device/**/*
+ - CMSIS/Core/Include/**/*
+ - CMSIS/Core/Include/**/*: CMSIS/Include/
+ - CMSIS/Core/Template/**/*
+ - CMSIS/Core_A/**/*
+ - CMSIS/DAP/**/*
+ - CMSIS/Driver/**/*
+ - CMSIS/DSP/Include/**/*
+ - CMSIS/DSP/Source/**/*
+ - CMSIS/DSP/Projects/**/*
+ - CMSIS/DSP/Examples/**/*
+ - CMSIS/DSP/Include/**/*: CMSIS/Include/
+ - CMSIS/DSP/Lib/**/*
+ - CMSIS/NN/**/*
+ - CMSIS/Pack/**/*
+ - CMSIS/RTOS/**/*
+ - CMSIS/RTOS2/**/*
+ - CMSIS/Utilities/ARM_Example.*: CMSIS/SVD/ARM_Example.
+ - CMSIS/Utilities/CMSIS-SVD.xsd
+ - CMSIS/Utilities/PACK.xsd
+ - CMSIS/Utilities/PackIndex.xsd
+ - CMSIS/Utilities/Win32/**/*
+ - CMSIS/Utilities/Linux-gcc-4.4.4/**/*
+ - CMSIS/Utilities/Linux-gcc-4.8.3/**/*
+ - CMSIS/Documentation/**/*
+ - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/Core/html/search/search.css
+ - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/Core_A/html/search/search.css
+ - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/Driver/html/search/search.css
+ - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/Pack/html/search/search.css
+ - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/DSP/html/search/search.css
+ - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/DAP/html/search/search.css
+ - CMSIS/DoxyGen/Doxygen_Templates/search.css: CMSIS/Documentation/NN/html/search/search.css
+ - CMSIS/DoxyGen/Zone/genmodel/**/*: CMSIS/Documentation/Zone/genmodel/

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/comm-stack-dk/data.c

@@ -0,0 +1,205 @@
+//
+// Description: Data Operation Utils
+//
+// Copyright (c) 2019 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#include <string.h>
+
+#include "data.h"
+
+/*
+ * Host to big endian
+ */
+void htoBe32(uint32_t value, uint8_t *data)
+{
+    data[0] = (value & 0xFF000000) >> 24;
+    data[1] = (value & 0x00FF0000) >> 16;
+    data[2] = (value & 0x0000FF00) >> 8;
+    data[3] = (value & 0x000000FF);
+}
+
+void htoBe16(uint16_t value, uint8_t *data)
+{
+    data[0] = (value & 0xFF00) >> 8;
+    data[1] = (value & 0x00FF);
+}
+
+void hToLe16(uint16_t value, uint8_t *data)
+{
+    data[0] = (value & 0x00FF);
+    data[1] = (value & 0xFF00) >> 8;
+}
+
+uint32_t beToH32(uint8_t *data)
+{
+
+    uint32_t value = 0;
+
+    value |= data[0] << 24;
+    value |= data[1] << 16;
+    value |= data[2] << 8;
+    value |= data[3];
+
+    return value;
+}
+
+uint16_t beToH16(uint8_t *data)
+{
+    uint32_t value = 0;
+
+    value |= data[0] << 8;
+    value |= data[1];
+
+    return value;
+}
+
+uint16_t leToH16(uint8_t *data)
+{
+    uint32_t value = 0;
+
+    value |= data[1] << 8;
+    value |= data[0];
+
+    return value;
+}
+
+uint8_t beToH8(uint8_t *data)
+{
+    uint8_t value = 0;
+    value |= data[0];
+
+    return value;
+}
+
+int16_t toInt16(int16_t data, uint8_t numBit)
+{
+    int16_t mask;
+    int16_t res = data;
+
+    if (numBit <= 16)
+    {
+        mask = (1 << numBit) - 1;
+        if (data >= (mask >> 1))
+        {
+            // Value is negative
+            res = data | ~mask;
+        }
+    }
+
+    return res;
+}
+
+int32_t toInt32(int32_t data, uint8_t numBit)
+{
+    int32_t mask;
+    int32_t res = data;
+
+    if (numBit <= 32)
+    {
+        mask = (1 << numBit) - 1;
+        if (data >= (mask >> 1))
+        {
+            // Value is negative
+            res = data | ~mask;
+        }
+    }
+
+    return res;
+}
+
+static inline uint32_t powTwo(uint32_t order)
+{
+    uint32_t powOne = 1;
+    return (powOne << order);
+}
+
+bool twoComplement(int32_t value, size_t bitLength, uint32_t *result)
+{
+    bool res = false;
+
+    uint32_t subMaxValue = powTwo(bitLength - 1);
+
+    int32_t maxValue = subMaxValue - 1;
+    int32_t minValue = -1 * subMaxValue;
+
+    if (result != NULL && value <= maxValue && value >= minValue)
+    {
+        if (value >= 0)
+        {
+            *result = value;
+        }
+        if (value < 0)
+        {
+            *result = powTwo(bitLength) + value;
+        }
+
+        res = true;
+    }
+
+    return res;
+}
+
+uint16_t endian_reverse16(uint16_t val)
+{
+    return ((val & 0xFF) < 8) | ((val & 0xFF00) > 8);
+
+}
+
+uint32_t endian_reverse32(uint32_t val)
+{
+    return ((val & 0xFF) < 24) | ((val & 0xFF00) < 8) | ((val & 0xFF0000) > 8) | ((val & 0xFF000000) > 24);
+
+}
+
+uint64_t endian_reverse64(uint64_t val)
+{
+    return ((((val) & 0xff00000000000000ull) >> 56) |
+            (((val) & 0x00ff000000000000ull) >> 40) |
+            (((val) & 0x0000ff0000000000ull) >> 24) |
+            (((val) & 0x000000ff00000000ull) >> 8) |
+            (((val) & 0x00000000ff000000ull) << 8) |
+            (((val) & 0x0000000000ff0000ull) << 24) |
+            (((val) & 0x000000000000ff00ull) << 40) |
+            (((val) & 0x00000000000000ffull) << 56));
+}
+
+void endian_reverse_array_enc(uint8_t *dst, uint8_t *array, uint8_t sizeInBytes)
+{
+    uint8_t valueIndex = sizeInBytes;
+    for (uint8_t dstIndex = 0; dstIndex < sizeInBytes; dstIndex++)
+    {
+        dst[dstIndex] = array[--valueIndex];
+    }
+}
+
+void endian_reverse_array(uint8_t *array, uint8_t sizeInBytes)
+{
+    uint8_t endIndex = sizeInBytes;
+    uint8_t value;
+
+    for (uint8_t startIndex = 0; startIndex < endIndex; startIndex++, endIndex--)
+    {
+        value = array[startIndex];
+        array[startIndex] = array[endIndex];
+        array[endIndex] = value;
+    }
+}

drivers/input/misc/bos0614_mmi/libs/dk-core/contribs/comm-stack-dk/data.h

@@ -0,0 +1,217 @@
+//
+// Description: Data Operation Utils
+//
+// Copyright (c) 2019 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#ifndef _DATA_H
+#define _DATA_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NANO_PER_UNITY    (1.0e9)
+#define MICRO_PER_UNITY   (1.0e6)
+#define MICRO_PER_MILLI   (1.0e3)
+#define MILLI_PER_UNITY   (1.0e3)
+#define UNITY_PER_KILO    (1.0e3)
+#define UNITY_PER_MEGA    (1.0e6)
+#define MEGA_PER_GIGA     (1.0e3)
+
+#define MASK_1_BIT      (0x00000001)
+#define MASK_2_BIT      (0x00000003)
+#define MASK_3_BIT      (0x00000007)
+#define MASK_4_BIT      (0x0000000F)
+#define MASK_5_BIT      (0x0000001F)
+#define MASK_6_BIT      (0x0000003F)
+#define MASK_7_BIT      (0x0000007F)
+#define MASK_8_BIT      (0x000000FF)
+#define MASK_9_BIT      (0x000001FF)
+#define MASK_10_BIT     (0x000003FF)
+#define MASK_11_BIT     (0x000007FF)
+#define MASK_12_BIT     (0x00000FFF)
+#define MASK_13_BIT     (0x00001FFF)
+#define MASK_14_BIT     (0x00003FFF)
+#define MASK_15_BIT     (0x00007FFF)
+#define MASK_16_BIT     (0x0000FFFF)
+#define MASK_17_BIT     (0x0001FFFF)
+#define MASK_18_BIT     (0x0003FFFF)
+#define MASK_19_BIT     (0x0007FFFF)
+#define MASK_20_BIT     (0x000FFFFF)
+#define MASK_21_BIT     (0x001FFFFF)
+#define MASK_22_BIT     (0x003FFFFF)
+#define MASK_23_BIT     (0x007FFFFF)
+#define MASK_24_BIT     (0x00FFFFFF)
+
+#define SHIFT_1_BIT     (0x1)
+#define SHIFT_2_BIT     (0x2)
+#define SHIFT_4_BIT     (0x4)
+#define SHIFT_8_BIT     (0x8)
+#define SHIFT_16_BIT    (0x16)
+
+#define BYTE_LENGTH_IN_BITS (8)
+
+#define container_of(ptr, type, member) ({                      \
+        const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
+        (type *)( (char *)__mptr - offsetof(type,member) );})
+
+#define PI (3.14159265)
+
+#define DATA_ARRAY_LENGTH(array) (sizeof(array)/sizeof(array[0]))
+
+void htoBe32(uint32_t value, uint8_t *data);
+
+void htoBe16(uint16_t value, uint8_t *data);
+
+void hToLe16(uint16_t value, uint8_t *data);
+
+uint32_t beToH32(uint8_t *data);
+
+uint16_t beToH16(uint8_t *data);
+
+uint16_t leToH16(uint8_t *data);
+
+int16_t toInt16(int16_t data, uint8_t numBit);
+
+int32_t toInt32(int32_t data, uint8_t numBit);
+
+float be16ToFloat(const uint8_t *data);
+
+void floatToBe16(float value, uint8_t *data);
+
+bool twoComplement(int32_t value, size_t bitLength, uint32_t *result);
+
+#define COMMUNICATION_STACK_1_BYTE (1)
+#define COMMUNICATION_STACK_2_BYTES (2)
+#define COMMUNICATION_STACK_4_BYTES (4)
+
+uint16_t endian_reverse16(uint16_t val);
+
+uint32_t endian_reverse32(uint32_t val);
+
+uint64_t endian_reverse64(uint64_t val);
+
+void endian_reverse_array(uint8_t* array, uint8_t sizeInBytes);
+
+void endian_reverse_array_enc(uint8_t* dst, uint8_t* array, uint8_t sizeInBytes);
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+
+#define htole16(x) (x)
+#define le16toh(x) (x)
+#if __GNUC__
+#define htobe16(x) __builtin_bswap16(x)
+#define be16toh(x) __builtin_bswap16(x)
+#else
+#define htobe16(x) do{x=endian_reverse16(x);} while (0)
+#define be16toh(x) do{x=endian_reverse16(x);} while (0)
+#endif //__GNUC__
+
+#define htole32(x) (x)
+#define le32toh(x) (x)
+#if __GNUC__
+#define htobe32(x) __builtin_bswap32(x)
+#define be32toh(x) __builtin_bswap32(x)
+#else
+#define htobe32(x) do{x=endian_reverse32(x);} while (0)
+#define be32toh(x) do{x=endian_reverse32(x);} while (0)
+#endif //__GNUC__
+
+#define htole64(x) (x)
+#define le64toh(x) (x)
+#if __GNUC__
+#define htobe64(x) __builtin_bswap64(x)
+#define be64toh(x) __builtin_bswap64(x)
+#else
+#define htobe64(x) do{x=endian_reverse64(x);} while (0)
+#define be64toh(x) do{x=endian_reverse64(x);} while (0)
+#endif //__GNUC__
+
+#define htolevalue(array, size) (array, size)
+#define levaluetoh(array, size) (array, size)
+
+#define htolevalue_enc(dst, array, size) (dst, array, size)
+#define levaluetoh_enc(dst, array, size) (dst, array, size)
+
+#define htobevalue(array, size) do{endian_reverse_array(array, size;} while (0)
+#define bevaluetoh(array, size) do{endian_reverse_array(array, size);} while (0)
+
+#define htobevalue_enc(dst, array, size) do{endian_reverse_array_enc(dst, array, size;} while (0)
+#define bevaluetoh_enc(dst, array, size) do{endian_reverse_array_enc(dst, array, size);} while (0)
+
+#elif BYTE_ORDER == BIG_ENDIAN
+#define htobe16(x) (x)
+#define be16toh(x) (x)
+#if __GNUC__
+#define htole16(x) __builtin_bswap16(x)
+#define le16toh(x) __builtin_bswap16(x)
+#else
+#define htole16(x) do{x=endian_reverse16(x);} while (0)
+#define le16toh(x) do{x=endian_reverse16(x);} while (0)
+#endif //__GNUC__
+
+#define htobe32(x) (x)
+#define be32toh(x) (x)
+#if __GNUC__
+#define htole32(x) __builtin_bswap32(x)
+#define le32toh(x) __builtin_bswap32(x)
+#else
+#define htole32(x) do{x=endian_reverse32(x);} while (0)
+#define le32toh(x) do{x=endian_reverse32(x);} while (0)
+#endif //__GNUC__
+
+#define htobe64(x) (x)
+#define be64toh(x) (x)
+#if __GNUC__
+#define htole64(x) __builtin_bswap64(x)
+#define le64toh(x) __builtin_bswap64(x)
+#else
+#define htole64(x) do{x=endian_reverse64(x);}while (0)
+#define le64toh(x) do{x=endian_reverse64(x);}while (0)
+#endif //__GNUC__
+
+
+#define htobevalue(array, size) (array, size)
+#define bevaluetoh(array, size) (array, size)
+
+#define htobevalue_enc(dst, array, size) (dst, array, size)
+#define bevaluetoh_end(dst, array, size) (dst, array, size)
+
+#define htolevalue(array, size) do{endian_reverse_array(array, size);}while (0)
+#define levaluetoh(array, size) do{endian_reverse_array(array, size);}while (0)
+
+#define htolevalue_enc(dst, array, size) do{endian_reverse_array_enc(dst, array, size;} while (0)
+#define levaluetoh_enc(dst, array, size) do{endian_reverse_array_enc(dst, array, size);} while (0)
+
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_DATA_H

drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/boards/boreasTime.h

@@ -0,0 +1,63 @@
+//
+// Description: Generic Time API
+//
+// Copyright (c) 2019 Boreas Technologies All rights reserved.
+// 
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#ifndef DKCORE_LAUNCHPADTIME_H
+#define DKCORE_LAUNCHPADTIME_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define MICROSECOND_IN_MILLISECOND(_us) (_us/1000)
+
+#define SECOND_IN_MILLISECOND(_s) (_s*1000)
+
+#define SECOND_IN_MICROSECOND(_s) (_s*1000000)
+
+typedef uint32_t TimeStamp;
+
+/*
+ * @brief Initiate the time service
+ *
+ * @return void
+ */
+bool timeInit(void);
+
+/*
+ * @brief Wait specific amount time in microsecond.
+ *
+ * @param[in] timeUs The time in microsecond to wait for
+ *
+ * @return void
+ */
+void timeWaitUs(uint32_t timeUs);
+
+/**
+ * @brief Get the time since platform has been initiated.
+ *
+ * @return uint32_t The time in millisecond
+ */
+TimeStamp timeGet(void);
+
+
+#endif //DKCORE_LAUNCHPADTIME_H

drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/gpio/gpio.h

@@ -0,0 +1,75 @@
+//
+// Description: Generic GPIO API
+// Created on 1/10/2020
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+// 
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+#ifndef DKCORE_GPIO_H
+#define DKCORE_GPIO_H
+
+#include <stdbool.h>
+
+typedef struct _GPIO Gpio;
+
+typedef enum
+{
+    GPIOState_High,
+    GPIOState_Low,
+    GPIOState_Invalid
+} GPIOState;
+
+typedef enum
+{
+    GPIOISR_Falling,
+    GPIOISR_Rising,
+    GPIOISR_Both,
+    GPIOISR_None,
+} GPIOIsr;
+
+typedef enum
+{
+    GPIODir_Input,
+    GPIODir_Output,
+    GPIODir_Bidirectional
+} GPIODir;
+
+typedef void(*GPIOIsrCb)(Gpio *gpio, void *context, GPIOIsr event);
+
+typedef bool(*GPIOSet)(Gpio *gpio, GPIOState state);
+
+typedef GPIOState(*GPIOGet)(Gpio *gpio);
+
+typedef bool(*GPIORegisterISR)(Gpio *gpio, GPIOIsr isrMode, GPIOIsrCb cb, void *context, bool enable);
+
+typedef bool (*GPIOClearISR)(Gpio *gpio);
+
+typedef bool (*GPIOSetDir)(Gpio *gpio, GPIODir dir);
+
+
+struct _GPIO
+{
+    GPIOSet set;
+    GPIOGet get;
+    GPIORegisterISR registerIsr;
+    GPIOClearISR clearIsr;
+    GPIOSetDir setDir;
+};
+
+#endif //DKCORE_GPIO_H

drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bos0614Driver.h

@@ -0,0 +1,49 @@
+//
+// Description: BOS0614 Driver Instantiation
+// Created on 5/5/2020
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#ifndef DKCORE_BOS0614DRIVER_H
+#define DKCORE_BOS0614DRIVER_H
+
+#include "coreDef.h"
+#include "bsp/drivers/haptic/bosDriver.h"
+#include "bsp/drivers/i2c/i2c.h"
+
+#define BOS0614_NBR_OF_CHANNEL  (4)
+#define BOS0614_CHANNEL_MASK (0xF)
+
+typedef struct
+{
+    I2c *i2c;
+    Gpio *gpioA;
+    Gpio *gpioB;
+    Gpio *gpioC;
+    Gpio *gpioD;
+} Bos0614Resource;
+
+HapticDriver *bos0614DriverI2cInit(Bos0614Resource resources);
+
+HapticDriver *bos0614DriverSpiInit(Spi *spi, Gpio *gpioA, Gpio *gpioD);
+
+
+#endif //DKCORE_BOS0614DRIVER_H

drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/haptic/bosDriver.h

@@ -0,0 +1,506 @@
+//
+// Description: Boreas Generic Haptic Driver Interface
+// Created on 2/18/2020
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#ifndef DKCORE_BOSDRIVER_H
+#define DKCORE_BOSDRIVER_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include "bsp/drivers/spi/spi.h"
+#include "bsp/drivers/gpio/gpio.h"
+
+#include "bsp/drivers/haptic/bos0614Register.h"
+
+#define INVALID_CHIP_ID (0xFF)
+#define HAPTIC_DRIVER_DEFAULT_CHANNEL (0)
+
+typedef uint8_t SliceId;
+typedef uint8_t WaveformId;
+
+typedef union
+{
+    Bos0614Register register0614;
+} Register;
+
+typedef union
+{
+    BOS0614_REGS bos0614Regs;
+} Registers;
+
+typedef enum
+{
+    GPO_InternalReset = 0,
+    GPO_SenseTrigger,
+    GPO_WaveformFifoDone,
+    GPO_ErrorNotify,
+    GPO_MaxPower,
+    GPO_ButtonState,
+    GPO_RequestToPLay,
+} GPOCtrl;
+
+typedef enum
+{
+    SensingDirection_Press = 0x00,
+    SensingDirection_Release = 0x01,
+    SensingDirection_Both
+} SensingDirection;
+
+typedef enum
+{
+    SensingDetectionMode_Threshold = 0x0,
+    SensingDetectionMode_Slope = 0x1,
+} SensingDetectionMode;
+
+typedef struct
+{
+    uint16_t debounceUs;
+    int16_t thresholdMv;
+    SensingDirection direction;
+    SensingDetectionMode mode;
+    uint8_t stabilisationMs;
+} SensingConfig;
+
+typedef enum
+{
+    BosFeature_Fifo,
+    BosFeature_Synthesizer,
+    BosFeature_Ramplayback,
+    BosFeature_SensingWithAutomaticFeedback,
+    BosFeature_SensingThresholdDetection,
+    BosFeature_GPOSignaling,
+
+    BosFeature_Length
+} BosFeature;
+
+
+typedef struct
+{
+    uint32_t sliceId;
+    int32_t mVAmp;     //milli volt amplitude
+    uint32_t mHzFreq;   //milli-Hertz
+    uint32_t cycle;
+} SynthSlice;
+
+typedef enum
+{
+    BOSERROR_NO_ERROR = 0,
+    BOSERROR_SHORT_CIRCUIT,
+    BOSERROR_UVLO,
+    BOSERROR_IDAC,
+    BOSERROR_MAX_POWER,
+    BOSERROR_OVT,
+    BOSERROR_OVV,
+    BOSERROR_Length,
+} BOSError;
+
+typedef enum
+{
+    BOS_EVENT_WAVEFORM_DONE,
+    BOS_EVENT_BUTTON_PRESS,
+    BOS_EVENT_BUTTON_RELEASE,
+    BOS_EVENT_SENSING_TRIGGER,
+    BOS_EVENT_REQUEST_TO_PLAY,
+    BOS_EVENT_NO_REQUEST_TO_PLAY,
+    BOS_EVENT_NO_EVENT
+} BOSEvent;
+
+typedef uint8_t ChannelId;
+
+typedef struct _HapticDriver HapticDriver;
+
+/*
+ * @brief Software Reset the chip
+ *
+ * @param[in] driver           The haptic driver context
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosSoftwareReset)(HapticDriver *driver);
+
+/*
+ * @brief Put device to sleep or wake it up
+ * @param[in] driver        The haptic driver context
+ * @param[in] toSleep    true for sleep, false for wakeup
+ * @return True if the operation succeeded, otherwise false
+ */
+typedef bool(*BosDeepSleep)(HapticDriver *driver, bool toSleep);
+
+/**
+ * @brief Return the chip id
+ *
+ * @param[in]   driver  The haptic driver context
+ *
+ * @return uint8_t Return the chip id
+ */
+typedef uint8_t (*BosGetChipId)(HapticDriver *driver);
+
+/*
+ * @brief Return the register value for a specific address
+ *
+ * @param[in]   driver haptic driver context
+ * @param[in]   addr  The register address
+ * @param[out]  value The pointer where to pu the read value
+ *
+ * @return bool True if the operation succeed, otherwise false
+ */
+typedef bool(*BosGetRegister)(HapticDriver *driver, uint8_t addr, uint16_t *value);
+
+/*
+ * @brief Set the specified register
+ *
+ * @param[in] driver   The haptic driver context
+ * @param[in] addr  The register address
+ * @param[in] value The register value to set
+ *
+ * @return bool
+ */
+typedef bool(*BosSetRegister)(HapticDriver *driver, uint8_t addr, uint16_t value);
+
+/*
+ * @brief Get the number of register available
+ */
+typedef size_t (*BosGetNumberOfRegister)(void);
+
+/*
+ * @brief Configure a slice which is part of a waveform (group of slice)
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] slice         Slice configuration
+ * @param[in] outputChannel The output channel of the slice
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool (*BosSynthesizerSetSlice)(HapticDriver *driver, const SynthSlice *slice, const uint8_t outputChannel);
+
+/**
+ * @brief Set the synthesizer mode
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] waveformId    The waveform id to configure
+ * @param[in] frequency     The frequency of the specified waveform
+ * @param[in] amplitude     The amplitude of the specified waveform
+ * @param[in] cycle         The amount of waveform period to play
+ * @param[in] outputChannel The output channel to play the waveform
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosSynthesizerSetWaveform)(HapticDriver *driver, WaveformId id, uint8_t startSliceId,
+                                         size_t nbrOfSlices, uint16_t cycle, uint8_t outputChannel);
+
+
+/**
+ * @brief Activate or deactivate the output
+ *
+ * @param[in] driver           The haptic driver context
+ * @param[in] activate      True if activating the output, False if deactivating the output
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosCtrlOutput)(HapticDriver *driver, bool activate);
+
+/**
+ * @brief Configure the GPO mode
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] channel       The channel specific to this IC
+ * @param[in] state         The GPO mode to configure
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BOSCtrlGPO)(HapticDriver *driver, ChannelId channelId, GPOCtrl state);
+
+/**
+ * @brief BOS Driver GPO Event Callback
+ *
+ * @param[in] driver            The haptic driver instance
+ * @param[in] channelId         The channel specific to the event occurrence
+ * @param[in] event             The pushed event
+ * @param[in] context           The client context specified on registering the callback
+ *
+ * @return void
+ */
+typedef void(*BOSEventCb)(HapticDriver *driver, ChannelId channelId, BOSEvent event, void *context);
+
+/**
+ * @brief Register for event callback registration
+ *
+ * @param[in] driver            The haptic driver instance
+ * @param[in] channelId         The channel specific to listen for event
+ * @param[in] cb                Callback to register
+ * @param[in] context           Context to forward to the callback
+ *
+ * @return True if the operation succeed, false otherwise
+ */
+typedef bool(*BOSRegisterEvents)(HapticDriver *driver, ChannelId channelId, BOSEventCb cb, void *context);
+
+/*
+ * @brief Remove from event callback registration for GPO signals
+ *
+ * @param[in] driver            The haptic driver instance
+ * @param[in] channelId         The channel specific to unregister for event
+ *
+ * @return True if the operation succeed, false otherwise
+ */
+typedef bool(*BOSUnregisterEvents)(HapticDriver *driver, ChannelId channelId);
+
+/*
+ * @brief Toggle the synthesizer play
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] start         The waveform id where the sequencer starts to play
+ * @param[in] stop          The waveform id where the sequencer stops to play
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosWaveSynthesizerPlay)(HapticDriver *driver, WaveformId start, WaveformId stop);
+
+/**
+ * @brief Configure the chip in RAM playback mode
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] samplingRate  The number of kilo sample per second to play
+ * @param[in] data          The data to write in the ram
+ * @param[in] length        The length of the data to play
+ * @param[in] channelMask   The bit mask of the channel configuration where each bit represents a channel to activate.
+ * LSB represent the channel #0 and MSB the channel #8
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosRamplayback)(HapticDriver *driver, uint32_t samplingRate, void *data, size_t length,
+                              uint8_t channelMask);
+
+/**
+ * @brief Play the content of the ram playback
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] length        The length of the data to play
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosRamPlaybackToggle)(HapticDriver *driver, size_t length);
+
+
+/**
+ * @brief Configure the chip in Fifo mode
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] samplingRate  The number of kilo sample per second to play
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosSetFifoMode)(HapticDriver *driver, uint32_t samplingRate, uint8_t outputChannel);
+
+/**
+ * @brief Write data in the fifo
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] data          The data to write in the fifo
+ * @param[in] length        The length of the data to write
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosWriteFifoSamples)(HapticDriver *driver, void *data, size_t length);
+
+/**
+ * @brief Get the fifo space avaiable in the fifo
+ *
+ * @param[in] driver            The haptic driver context
+ * @param[in] availableSpace    The available space in the fifo
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosGetFifoSpace)(HapticDriver *ctx, uint16_t *availableSpace);
+
+/**
+ * @brief Get the FIFO max available space
+ *
+ * @return uint16_t The max space available
+ */
+typedef uint16_t (*BosGetMaximumFifoSpace)(void);
+
+/**
+ * @brief Activate or deactivate the synchronization mode between chip
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] activate      True for activating and False for deactivating
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosSynch)(HapticDriver *driver, bool activate);
+
+/**
+ * @brief Referencing the voltage value passed in the array to values referencing in the chip domain
+ *
+ * @param[in]       driver  The haptic driver context
+ * @param[in|out]   data    The data to reference
+ * @param[in]       length  The length of the array to reference
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool(*BosReferencingFromVolt)(HapticDriver *driver, int16_t *data, size_t length);
+
+/*
+ * @brief Get the error status bits
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] errors        Provided error array
+ * @param[in] maxLength     Max number of error to copy in the errors array
+ *
+ * @return The amount of active errors
+ */
+typedef size_t(*BosGetError)(HapticDriver *driver, BOSError *errors, size_t maxLength);
+
+/*
+ * @brief Sensing Event Callback
+ *
+ * @param[in] channel       The IC channel from which the event has been detected
+ * @param[in] mode          The sensing detection mode
+ * @param[in] direction     The sensing threshold direction detection
+ * @param[in] arg           Application Specific arg copied when registering the callback
+ *
+ * @return void
+ */
+typedef void (*BosSensingEvent)(uint8_t channel, SensingDetectionMode mode, SensingDirection direction, void *arg);
+
+/*
+ * @brief Configures the chip for sensing
+ *
+ * @param[in] driver        The haptic driver concerned
+ * @param[in] channel       The channel to configure the sensing for.
+ * @param[in] config        Sensing configuration to apply
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool (*BosSensingConfig)(HapticDriver *driver, ChannelId channelId, SensingConfig config);
+
+/*
+ * @brief Set the automatic feedback by channel
+ *
+ * @param[in] driver        The haptic driver concerned
+ * @param[in] channelId     The channel driver which applies
+ * @param[in] id            The synthesizer waveform id to play on detection event
+ * @param[in] direction     The detection direction (press or release) which the waveform must be applied to.
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool (*BosSensingAutoPlayWave)(HapticDriver *driver, ChannelId channelId, WaveformId id,
+                                       SensingDirection direction);
+
+/*
+ * @brief Stops sensing without disabling the output
+ *
+ * @param[in] driver    The haptic driver context
+ * @param[in] channel   The channel to deactivate the sensing
+ * @param[in] direction The sensing direction (press or release) to deactivate
+ *
+ * @return True if the operation succeed, otherwise false
+ */
+typedef bool (*BosSensingStop)(HapticDriver *driver, ChannelId channelId, SensingDirection direction);
+
+/*
+ * @brief (Engineering feature) Access register shadow value of the driver
+ *
+ * @return Registers The register set corresponding to the IC
+ */
+typedef Registers *(*BosGetShadowRegisters)(HapticDriver *driver);
+
+/*
+ * @brief (Engineering feature) Set a specific register using the Register struct
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] reg           The register to set
+ *
+ * @return bool             True if the operation succeed and false if the operation failed
+ */
+typedef bool(*BosWriteRegister)(HapticDriver *driver, Register *reg);
+
+
+/*
+ * @brief (Engineering feature) Set a specific register using the Register struct
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in|out] reg       The register to read. If the operation succeed, the value of the register will be updated.
+ *
+ * @return bool             True if the operation succeed and false if the operation failed
+ */
+typedef bool(*BosReadRegister)(HapticDriver *driver, Register *reg);
+
+/*
+ * @brief (Engineering feature) Read the GPIO pin state
+ *
+ * @param[in] driver        The haptic driver context
+ * @param[in] channel       The channel specific to this IC
+ *
+ * @return GPIOState        The state of the Gpio
+ */
+typedef GPIOState(*BosGetGpioState)(HapticDriver *driver, ChannelId channelId);
+
+/**
+ * @brief Interrogate driver if a specific feature is supported
+ *
+ * @param[in] feature       The feature request
+ *
+ * @return bool             True if the feature is supported, false if not
+ */
+typedef bool (*SupportedFeature)(HapticDriver *driver, BosFeature feature);
+
+struct _HapticDriver
+{
+    BosGetChipId getChipId;
+    BosSoftwareReset softwareReset;
+    BosDeepSleep deepSleep;
+    BosGetRegister getRegister;
+    BosSetRegister setRegister;
+    BosSynthesizerSetSlice synthSetSlice;
+    BosSynthesizerSetWaveform synthSetWaveform;
+    BosWaveSynthesizerPlay wfsPlay;
+    BOSRegisterEvents registerOnEvents;
+    BOSUnregisterEvents unregisterEvents;
+    BosCtrlOutput ctrlOutput;
+    BOSCtrlGPO configGPO;
+    BosRamplayback setRamPlayback;
+    BosRamPlaybackToggle playRamPlayback;
+    BosGetFifoSpace getFifoSpace;
+    BosGetMaximumFifoSpace getMaximumFifoSpace;
+    BosSetFifoMode setFifoMode;
+    BosWriteFifoSamples writeFifoSamples;
+    BosSynch synch;
+    BosGetError getError;
+    BosReferencingFromVolt referencingFromVolt;
+    BosGetNumberOfRegister numberOfRegister;
+    BosSensingConfig configSensing;
+    BosSensingAutoPlayWave sensingAutoPlayWave;
+    BosSensingStop stopSensing;
+    SupportedFeature isSupported;
+
+    /* Engineering functions */
+    BosGetShadowRegisters getShadowRegisters;
+    BosWriteRegister writeRegister;
+    BosReadRegister readRegister;
+    BosGetGpioState getGpioState;
+};
+
+#endif //DKCORE_BOSDRIVER_H

drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/i2c/i2c.h

@@ -0,0 +1,108 @@
+//
+// Description: I2C Driver Interface
+// Created on 1/23/2020
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+// 
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#ifndef DKCORE_I2C_H
+#define DKCORE_I2C_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#include <contribs/cmsis/CMSIS/Driver/Include/Driver_Common.h>
+
+#define I2C_7BIT_ADDRESS_MASK (0x7F)
+
+typedef enum
+{
+    I2C_ADR_PIN_GND,
+    I2C_ADR_PIN_VCC,
+    I2C_ADR_PIN_SDA,
+    I2C_ADR_PIN_SCL,
+    I2C_ADR_PIN_INVALID
+} I2cAdrPins;
+
+/**
+ * @typedef I2c driver Instance
+ */
+typedef struct _i2c I2c;
+
+/**
+ * @brief I2C Master Read Primitive
+ *
+ * @param i2c       Driver instance
+ * @param address   I2C slave address
+ * @param data      Buffer for read data
+ * @param num       Length to read
+ *
+ * @return ARM_DRIVER_OK on successful operation, ERRNO on failure
+ */
+typedef int32_t(*I2cRead)(I2c *i2c, uint8_t address, void *data, size_t num);
+
+/**
+ * @brief 2C Master Read Primitive with stop configuration
+ *
+ * @param i2c       Driver instance
+ * @param address   I2C slave address
+ * @param data      Buffer for read data
+ * @param num       Length to read
+ * @param writeStop Set to true for writing stop at the end of the transaction
+ *
+ * @return ARM_DRIVER_OK on successful operation, ERRNO on failure
+ */
+typedef int32_t(*I2cReadStop)(I2c *i2c, uint8_t address, void *data, size_t num, bool writeStop);
+
+/**
+ * @brief I2C Master Write Primitive
+ *
+ * @param i2c       Driver instance
+ * @param address   I2C slave address
+ * @param data      Data buffer to write
+ * @param num       Length of the buffer to write
+ *
+ * @return ARM_DRIVER_OK on successful operation, ERRNO on failure
+ */
+typedef int32_t(*I2cWrite)(I2c *i2c, uint8_t address, const void *data, size_t num);
+
+/**
+ * @brief I2C Master Write Primitive  with stop configuration
+ *
+ * @param i2c       Driver instance
+ * @param address   I2C slave address
+ * @param data      Data buffer to write
+ * @param num       Length of the buffer to write
+ * @param writeStop Set to true for writing stop at the end of the transaction
+ *
+ * @return ARM_DRIVER_OK on successful operation, ERRNO on failure
+ */
+typedef int32_t(*I2cWriteStop)(I2c *i2c, uint8_t address, const void *data, size_t num, bool writeStop);
+
+struct _i2c
+{
+    I2cWrite write;
+    I2cWriteStop writeStop;
+    
+    I2cRead read;
+    I2cReadStop readStop;
+};
+
+#endif //DKCORE_I2C_H

drivers/input/misc/bos0614_mmi/libs/dk-core/src/bsp/drivers/spi/spi.h

@@ -0,0 +1,25 @@
+//
+// Description: Spi Driver Interface
+//
+// Created by Pascal Frederic St-Laurent
+// Copyright (c) 2019 Boreas Technologies All rights reserved.
+//
+
+#ifndef DKCORE_SPI_H
+#define DKCORE_SPI_H
+
+#include <stdint.h>
+
+typedef struct _spi Spi;
+
+typedef int32_t(*SpiSend)(Spi *spi, const void *data, uint32_t num);
+
+typedef int32_t(*SpiTransfer)(Spi *spi, const void *data_out, void *data_in, uint32_t num);
+
+struct _spi
+{
+    SpiSend send;
+    SpiTransfer transfer;
+};
+
+#endif //DKCORE_SPI_H

drivers/input/misc/bos0614_mmi/libs/dk-core/src/coreDef.h

@@ -0,0 +1,197 @@
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+
+#ifndef DK_CORE_COREDEF_H
+#define DK_CORE_COREDEF_H
+
+#include "coreDefOption.h"
+
+#ifndef NBR_OF_BUTTON
+#define NBR_OF_BUTTON 0
+#endif
+
+#ifndef NBR_OF_TL1963A
+#define NBR_OF_TL1963A 0
+#endif
+
+#ifndef NBR_OF_IQS263
+#define NBR_OF_IQS263 0
+#endif
+
+#ifndef NBR_OF_MCP45HV
+#define NBR_OF_MCP45HV 0
+#endif
+
+#ifndef NBR_OF_TCA9535
+#define NBR_OF_TCA9535 0
+#endif
+
+#ifndef NBR_OF_TCA9554A
+#define NBR_OF_TCA9554A 0
+#endif
+
+#ifndef NBR_OF_IO_EXPANDER_GPIO
+#define NBR_OF_IO_EXPANDER_GPIO 0
+#endif
+
+#ifndef NBR_OF_TCA9548A
+#define NBR_OF_TCA9548A 0
+#endif
+
+#ifndef NBR_OF_I2C_SWITCH
+#define NBR_OF_I2C_SWITCH 0
+#endif
+
+#ifndef NBR_OF_I2C_SWITCH_CHANNEL
+#define NBR_OF_I2C_SWITCH_CHANNEL 0
+#endif
+
+#ifndef NBR_OF_LED
+#define NBR_OF_LED 0
+#endif
+
+#ifndef NBR_INA226
+#define NBR_INA226 0
+#endif
+
+#ifndef NBR_OF_TMP102
+#define NBR_OF_TMP102 0
+#endif
+
+#ifndef NBR_OF_TMP1075
+#define NBR_OF_TMP1075 0
+#endif
+
+#ifndef BOS0614_NBR_OF_INSTANCE
+#define BOS0614_NBR_OF_INSTANCE 0
+#endif
+
+#ifndef BOS1211_NBR_OF_INSTANCE
+#define BOS1211_NBR_OF_INSTANCE 0
+#endif
+
+#ifndef SENSING_INSTANCE_NBR
+#define SENSING_INSTANCE_NBR 0
+#endif
+
+#ifndef SENSING_CALLBACK_SUBSCRIBER_DEPTH
+#define SENSING_CALLBACK_SUBSCRIBER_DEPTH (0)
+#endif
+
+#ifndef BOS1901_NBR_OF_INSTANCE
+#define BOS1901_NBR_OF_INSTANCE 0
+#endif
+
+#ifndef NBR_OF_TDC7200
+#define NBR_OF_TDC7200 0
+#endif
+
+
+//Trigger playback config
+#ifndef MAXIMUM_NB_OF_CHANNEL_LINKED
+#define MAXIMUM_NB_OF_CHANNEL_LINKED (3)
+#endif
+
+#ifndef ISR_PLAYBACK_INSTANCE_NBR
+#define ISR_PLAYBACK_INSTANCE_NBR (1)
+#endif
+
+
+//Streaming config
+#ifndef STREAMING_INSTANCE_NBR
+#define STREAMING_INSTANCE_NBR (8)
+#endif
+
+
+//Stack config
+#ifndef STACK_MAX_TRANSACTION_LENGTH
+#define STACK_MAX_TRANSACTION_LENGTH (128)
+#endif
+
+#ifndef STACK_MAX_PENDING_TRANSACTION
+#define STACK_MAX_PENDING_TRANSACTION (8)
+#endif
+
+
+//Player config
+#ifndef PLAYER_FEEDBACK_NBR_OF_WAVEFORM
+#define PLAYER_FEEDBACK_NBR_OF_WAVEFORM (16)
+#endif
+
+#ifndef PLAYER_INSTANCE_NBR
+#define PLAYER_INSTANCE_NBR (0)
+#endif
+
+#ifndef PLAYER_BUFFER_SIZE
+#define PLAYER_BUFFER_SIZE (5120)   // 5120 * 16bitPerSample = 10KB
+#endif
+
+#ifndef PLAYER_CALLBACK_SUBSCRIBER_DEPTH
+#define PLAYER_CALLBACK_SUBSCRIBER_DEPTH (0)
+#endif
+
+
+//Sensing config
+#ifndef SENSING_NBR_OF_CONFIG_PER_CHANNEL
+#define SENSING_NBR_OF_CONFIG_PER_CHANNEL (2)
+#endif
+
+#ifndef SENSING_CHANNEL_PER_DRIVER
+#define SENSING_CHANNEL_PER_DRIVER (1)
+#endif
+
+
+//IC Status config
+#ifndef NBR_OF_ERROR
+#define NBR_OF_ERROR (0)
+#endif
+
+#ifndef NBR_OF_HAPTIC_DRIVER
+#define NBR_OF_HAPTIC_DRIVER (0)
+#endif
+
+
+// HFEM config
+#ifndef HFEM_NBR_OF_DRIVERS
+#define HFEM_NBR_OF_DRIVERS (0)
+#endif
+
+#ifndef HFEM_MAXIMUM_NBR_OF_TRIGGER
+#define HFEM_MAXIMUM_NBR_OF_TRIGGER (0)
+#endif
+
+#ifndef HFEM_INSTANCE_MAXIMUM_NBR
+#define HFEM_INSTANCE_MAXIMUM_NBR (0)
+#endif
+
+// Captouch config
+#ifndef CAPTOUCH_MAXIMUM_INSTANCE_NBR
+#define CAPTOUCH_MAXIMUM_INSTANCE_NBR (0)
+#endif
+
+#ifndef USER_BUTTON_INDEX
+#define USER_BUTTON_INDEX   (0)
+#endif
+
+#ifndef FITNESS_TRACKER_CAPTOUCH_INDEX
+#define FITNESS_TRACKER_CAPTOUCH_INDEX  (0)
+#endif
+
+#endif //DK_CORE_COREDEF_H

drivers/input/misc/bos0614_mmi/stdint.h

@@ -0,0 +1,30 @@
+//
+// Description: @TODO
+//
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#ifndef BOREAS_HAPTIC_DRIVER_LINUX_STDINT_H
+#define BOREAS_HAPTIC_DRIVER_LINUX_STDINT_H
+
+#include <linux/types.h>
+
+#endif //BOREAS_HAPTIC_DRIVER_LINUX_STDINT_H

drivers/input/misc/bos0614_mmi/string.h

@@ -0,0 +1,30 @@
+//
+// Description: Linux String Wrapper
+//
+// Copyright (c) 2020 Boreas Technologies All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+
+#ifndef BORÉAS_HAPTIC_DRIVER_LINUX_STRING_H
+#define BORÉAS_HAPTIC_DRIVER_LINUX_STRING_H
+
+#include <linux/string.h>
+
+#endif //BORÉAS_HAPTIC_DRIVER_LINUX_STRING_H