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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 14:19:09 -04:00
Merge "ARM: dts: msm: Add clock controller nodes for SCUBA"
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qctecmdr
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3 changed files with 256 additions and 0 deletions
111
qcom/qrb2210-rb1-gdsc.dtsi
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111
qcom/qrb2210-rb1-gdsc.dtsi
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@ -0,0 +1,111 @@
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&soc {
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/* GDSCs in GCC */
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gcc_camss_top_gdsc: qcom,gdsc@1458004 {
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compatible = "qcom,gdsc";
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reg = <0x1458004 0x4>;
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regulator-name = "gcc_camss_top_gdsc";
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status = "disabled";
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};
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gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {
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compatible = "qcom,gdsc";
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reg = <0x141a004 0x4>;
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regulator-name = "gcc_usb30_prim_gdsc";
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status = "disabled";
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};
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gcc_vcodec0_gdsc: qcom,gdsc@1458098 {
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compatible = "qcom,gdsc";
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reg = <0x1458098 0x4>;
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regulator-name = "gcc_vcodec0_gdsc";
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status = "disabled";
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};
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gcc_venus_gdsc: qcom,gdsc@145807c {
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compatible = "qcom,gdsc";
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reg = <0x145807c 0x4>;
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regulator-name = "gcc_venus_gdsc";
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status = "disabled";
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};
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hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {
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compatible = "qcom,gdsc";
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reg = <0x147d074 0x4>;
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regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {
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compatible = "qcom,gdsc";
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reg = <0x147d078 0x4>;
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regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {
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compatible = "qcom,gdsc";
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reg = <0x147d060 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {
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compatible = "qcom,gdsc";
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reg = <0x147d07c 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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/* GDSCs in DISPCC */
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mdss_core_gdsc: qcom,gdsc@5f03000 {
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compatible = "qcom,gdsc";
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reg = <0x5f03000 0x4>;
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regulator-name = "mdss_core_gdsc";
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proxy-supply = <&mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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/* GDSCs in GPUCC */
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gpu_cx_hw_ctrl: syscon@5991540 {
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compatible = "syscon";
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reg = <0x5991540 0x4>;
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};
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gpu_gx_sw_reset: syscon@5991008 {
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compatible = "syscon";
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reg = <0x5991008 0x4>;
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};
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gpu_gx_domain_addr: syscon@5991508 {
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compatible = "syscon";
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reg = <0x5991508 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@599106c {
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compatible = "qcom,gdsc";
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reg = <0x599106c 0x4>;
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regulator-name = "gpu_cx_gdsc";
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hw-ctl-addr = <&gpu_cx_hw_ctrl>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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gpu_gx_gdsc: qcom,gdsc@599100c {
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compatible = "qcom,gdsc";
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reg = <0x599100c 0x4>;
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regulator-name = "gpu_gx_gdsc";
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sw-reset = <&gpu_gx_sw_reset>;
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domain-addr = <&gpu_gx_domain_addr>;
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qcom,reset-aon-logic;
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status = "disabled";
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};
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};
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@ -1,3 +1,5 @@
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#include <dt-bindings/clock/qcom,gcc-scuba.h>
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#include <dt-bindings/clock/qcom,gpucc-scuba.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/iio/qcom,spmi-vadc.h>
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#include "qrb2210-rb1-ion.dtsi"
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@ -3,6 +3,10 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/spmi/spmi.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/clock/qcom,gcc-scuba.h>
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#include <dt-bindings/clock/qcom,gpucc-scuba.h>
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#include <dt-bindings/clock/qcom,dispcc-scuba.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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/ {
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model = "Qualcomm Technologies, Inc. Qrb2210 RB1";
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@ -41,6 +45,7 @@
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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@ -63,6 +68,7 @@
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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L1_I_1: l1-icache {
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compatible = "arm,arch-cache";
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@ -81,6 +87,7 @@
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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L1_I_2: l1-icache {
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compatible = "arm,arch-cache";
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@ -99,6 +106,7 @@
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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L1_I_3: l1-icache {
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compatible = "arm,arch-cache";
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@ -611,6 +619,93 @@ dcc: dcc_v2@1be2000 {
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};
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32764>;
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clock-output-names = "chip_sleep_clk";
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#clock-cells = <0>;
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};
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};
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rpmcc: qcom,rpmcc {
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compatible = "qcom,rpmcc-scuba";
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#clock-cells = <1>;
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};
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gcc: qcom,gcc@1400000 {
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compatible = "qcom,scuba-gcc", "syscon";
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reg = <0x1400000 0x1f0000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
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vdd_mx-supply = <&VDD_MX_LEVEL>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dispcc: qcom,dispcc@5f00000 {
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compatible = "qcom,scuba-dispcc", "syscon";
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reg = <0x5f00000 0x20000>;
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reg-names = "cc_base";
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clock-names = "cfg_ahb_clk";
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clocks = <&gcc GCC_DISP_AHB_CLK>;
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gpucc: qcom,gpucc@5990000 {
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compatible = "qcom,scuba-gpucc", "syscon";
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reg = <0x5990000 0x9000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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/*qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;*/
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mccc_debug: syscon@447d200 {
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compatible = "syscon";
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reg = <0x447d200 0x100>;
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};
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cpucc_debug: syscon@f11101c {
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compatible = "syscon";
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reg = <0xf11101c 0x4>;
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};
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debugcc: qcom,cc-debug {
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compatible = "qcom,scuba-debugcc";
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status = "disabled";
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qcom,gcc = <&gcc>;
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qcom,dispcc = <&dispcc>;
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qcom,gpucc = <&gpucc>;
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qcom,mccc = <&mccc_debug>;
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qcom,cpucc = <&cpucc_debug>;
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clock-names = "xo_clk_src";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
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#clock-cells = <1>;
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};
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cpufreq_hw: qcom,cpufreq-hw {
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compatible = "qcom,cpufreq-hw";
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reg = <0xf521000 0x1400>;
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reg-names = "freq-domain0";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
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clock-names = "xo", "alternate";
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qcom,no-accumulative-counter;
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qcom,max-lut-entries = <12>;
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#freq-domain-cells = <2>;
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};
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spmi_bus: qcom,spmi@1c40000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x1c40000 0x1100>,
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@ -1050,6 +1145,8 @@ dcc: dcc_v2@1be2000 {
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#include "qrb2210-rb1-pinctrl.dtsi"
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#include "qrb2210-rb1-ion.dtsi"
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#include "msm-arm-smmu-qrb2210-rb1.dtsi"
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#include "qrb2210-rb1-qupv3.dtsi"
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#include "qrb2210-rb1-gdsc.dtsi"
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&qupv3_se1_i2c {
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#address-cells = <1>;
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@ -1160,6 +1257,52 @@ dcc: dcc_v2@1be2000 {
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};
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};
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&gcc_camss_top_gdsc {
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status = "ok"
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};
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&gcc_usb30_prim_gdsc {
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status = "ok"
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};
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&gcc_vcodec0_gdsc {
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qcom,support-hw-trigger;
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status = "ok"
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};
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&gcc_venus_gdsc {
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status = "ok"
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};
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&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
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status = "ok"
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};
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&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
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status = "ok"
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};
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&hlos1_vote_turing_mmu_tbu1_gdsc {
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status = "ok"
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};
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&hlos1_vote_turing_mmu_tbu0_gdsc {
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status = "ok"
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};
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&mdss_core_gdsc {
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qcom,support-hw-trigger;
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status = "ok"
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};
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&gpu_cx_gdsc {
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status = "ok"
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};
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&gpu_gx_gdsc {
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status = "ok"
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};
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&pm2250_vadc {
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#address-cells = <1>;
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#size-cells = <0>;
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