diff --git a/include/dt-bindings/clock/mdss-5nm-pll-clk.h b/include/dt-bindings/clock/mdss-5nm-pll-clk.h
index f33353a02102..2eb6105aa9cb 100644
--- a/include/dt-bindings/clock/mdss-5nm-pll-clk.h
+++ b/include/dt-bindings/clock/mdss-5nm-pll-clk.h
@@ -25,24 +25,35 @@
 #define SHADOW_POST_VCO_DIV_0_CLK	15
 #define SHADOW_PCLK_SRC_MUX_0_CLK	16
 #define SHADOW_PCLK_SRC_0_CLK		17
-#define VCO_CLK_1		18
-#define PLL_OUT_DIV_1_CLK	19
-#define BITCLK_SRC_1_CLK	20
-#define BYTECLK_SRC_1_CLK	21
-#define POST_BIT_DIV_1_CLK	22
-#define POST_VCO_DIV_1_CLK	23
-#define BYTECLK_MUX_1_CLK	24
-#define PCLK_SRC_MUX_1_CLK	25
-#define PCLK_SRC_1_CLK		26
-#define PCLK_MUX_1_CLK		27
-#define SHADOW_VCO_CLK_1		28
-#define SHADOW_PLL_OUT_DIV_1_CLK	29
-#define SHADOW_BITCLK_SRC_1_CLK		30
-#define SHADOW_BYTECLK_SRC_1_CLK	31
-#define SHADOW_POST_BIT_DIV_1_CLK	32
-#define SHADOW_POST_VCO_DIV_1_CLK	33
-#define SHADOW_PCLK_SRC_MUX_1_CLK	34
-#define SHADOW_PCLK_SRC_1_CLK		35
+/* CPHY clocks for DSI-0 PLL */
+#define CPHY_BYTECLK_SRC_0_CLK		18
+#define POST_VCO_DIV3_5_0_CLK		19
+#define CPHY_PCLK_SRC_MUX_0_CLK		20
+#define CPHY_PCLK_SRC_0_CLK		21
+
+#define VCO_CLK_1		22
+#define PLL_OUT_DIV_1_CLK	23
+#define BITCLK_SRC_1_CLK	24
+#define BYTECLK_SRC_1_CLK	25
+#define POST_BIT_DIV_1_CLK	26
+#define POST_VCO_DIV_1_CLK	27
+#define BYTECLK_MUX_1_CLK	28
+#define PCLK_SRC_MUX_1_CLK	29
+#define PCLK_SRC_1_CLK		30
+#define PCLK_MUX_1_CLK		31
+#define SHADOW_VCO_CLK_1		32
+#define SHADOW_PLL_OUT_DIV_1_CLK	33
+#define SHADOW_BITCLK_SRC_1_CLK		34
+#define SHADOW_BYTECLK_SRC_1_CLK	35
+#define SHADOW_POST_BIT_DIV_1_CLK	36
+#define SHADOW_POST_VCO_DIV_1_CLK	37
+#define SHADOW_PCLK_SRC_MUX_1_CLK	38
+#define SHADOW_PCLK_SRC_1_CLK		39
+/* CPHY clocks for DSI-1 PLL */
+#define CPHY_BYTECLK_SRC_1_CLK		40
+#define POST_VCO_DIV3_5_1_CLK		41
+#define CPHY_PCLK_SRC_MUX_1_CLK		42
+#define CPHY_PCLK_SRC_1_CLK		43
 
 /* DP PLL clocks */
 #define DP_VCO_CLK	0