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dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property
The width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add documentation for it. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Reviewed-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -41,6 +41,10 @@ Optional properties:
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- xlnx,include-sg: Tells configured for Scatter-mode in
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the hardware.
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Optional properties for AXI DMA:
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- xlnx,sg-length-width: Should be set to the width in bits of the length
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register as configured in h/w. Takes values {8...26}. If the property
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is missing or invalid then the default value 23 is used. This is the
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maximum value that is supported by all IP versions.
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- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
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Optional properties for VDMA:
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- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
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