mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 22:23:14 -04:00
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (54 commits) [MIPS] Remove mips_machtype for LASAT machines [MIPS] Remove mips_machtype from EMMA2RH machines [MIPS] Remove mips_machtype from ARC based machines [MIPS] MTX-1 flash partition setup move to platform devices registration [MIPS] TXx9: cleanup and fix some sparse warnings [MIPS] TXx9: rename asm-mips/mach-jmr3927 to asm-mips/mach-tx39xx [MIPS] remove machtype for group Toshiba [MIPS] separate rbtx4927_time_init() and rbtx4937_time_init() [MIPS] separate rbtx4927_arch_init() and rbtx4937_arch_init() [MIPS] txx9_cpu_clock setup move to rbtx4927_time_init() [MIPS] txx9_board_vec set directly without mips_machtype [MIPS] IP22: Add platform device for Indy volume buttons [MIPS] cmbvr4133: Remove support [MIPS] remove wrppmc_machine_power_off() [MIPS] replace inline assembler to cpu_wait() [MIPS] IP22/28: Add platform devices for HAL2 [MIPS] TXx9: Update and merge defconfigs [MIPS] TXx9: Make single kernel can support multiple boards [MIPS] TXx9: Update defconfigs [MIPS] TXx9: Reorganize PCI code ...
This commit is contained in:
Linus Torvalds
commit
7e2225d860
219 changed files with 4317 additions and 15641 deletions
|
|
@ -92,11 +92,25 @@
|
|||
#define fast_wmb() __sync()
|
||||
#define fast_rmb() __sync()
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||||
#define fast_mb() __sync()
|
||||
#ifdef CONFIG_SGI_IP28
|
||||
#define fast_iob() \
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||||
__asm__ __volatile__( \
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||||
".set push\n\t" \
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||||
".set noreorder\n\t" \
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||||
"lw $0,%0\n\t" \
|
||||
"sync\n\t" \
|
||||
"lw $0,%0\n\t" \
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||||
".set pop" \
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||||
: /* no output */ \
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||||
: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
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||||
: "memory")
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||||
#else
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||||
#define fast_iob() \
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||||
do { \
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||||
__sync(); \
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||||
__fast_iob(); \
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||||
} while (0)
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||||
#endif
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||||
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||||
#ifdef CONFIG_CPU_HAS_WB
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||||
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||||
|
|
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|||
|
|
@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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|||
"2: b 1b \n"
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||||
" .previous \n"
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||||
: "=&r" (temp), "=m" (*m)
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||||
: "ir" (bit), "m" (*m), "r" (~0));
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||||
: "i" (bit), "m" (*m), "r" (~0));
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||||
#endif /* CONFIG_CPU_MIPSR2 */
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||||
} else if (cpu_has_llsc) {
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||||
__asm__ __volatile__(
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||||
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@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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"2: b 1b \n"
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||||
" .previous \n"
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||||
: "=&r" (temp), "=m" (*m)
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||||
: "ir" (bit), "m" (*m));
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: "i" (bit), "m" (*m));
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#endif /* CONFIG_CPU_MIPSR2 */
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||||
} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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||||
|
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@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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"2: b 1b \n"
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||||
" .previous \n"
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||||
: "=&r" (temp), "=m" (*m), "=&r" (res)
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||||
: "ri" (bit), "m" (*m)
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||||
: "i" (bit), "m" (*m)
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||||
: "memory");
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||||
#endif
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||||
} else if (cpu_has_llsc) {
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||||
|
|
|
|||
|
|
@ -25,13 +25,6 @@
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|||
*/
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||||
#define MACH_UNKNOWN 0 /* whatever... */
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||||
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||||
/*
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||||
* Valid machtype values for group JAZZ
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||||
*/
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||||
#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */
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#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */
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||||
#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */
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||||
|
||||
/*
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||||
* Valid machtype for group DEC
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||||
*/
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||||
|
|
@ -47,42 +40,6 @@
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|||
#define MACH_DS5800 9 /* DECsystem 5800 */
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#define MACH_DS5900 10 /* DECsystem 5900 */
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||||
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||||
/*
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* Valid machtype for group SNI_RM
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||||
*/
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||||
#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */
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/*
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* Valid machtype for group SGI
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*/
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#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */
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#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */
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#define MACH_SGI_IP28 2 /* Indigo2 Impact */
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#define MACH_SGI_IP32 3 /* O2 */
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#define MACH_SGI_IP30 4 /* Octane, Octane2 */
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|
||||
/*
|
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* Valid machtypes for group Toshiba
|
||||
*/
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||||
#define MACH_PALLAS 0
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||||
#define MACH_TOPAS 1
|
||||
#define MACH_JMR 2
|
||||
#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */
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#define MACH_TOSHIBA_RBTX4927 4
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#define MACH_TOSHIBA_RBTX4937 5
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||||
#define MACH_TOSHIBA_RBTX4938 6
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||||
|
||||
/*
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||||
* Valid machtype for group LASAT
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||||
*/
|
||||
#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */
|
||||
#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
|
||||
|
||||
/*
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||||
* Valid machtype for group NEC EMMA2RH
|
||||
*/
|
||||
#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
|
||||
|
||||
/*
|
||||
* Valid machtype for group PMC-MSP
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -66,8 +66,10 @@
|
|||
#define PRID_IMP_RM7000 0x2700
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||||
#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
|
||||
#define PRID_IMP_RM9000 0x3400
|
||||
#define PRID_IMP_LOONGSON1 0x4200
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||||
#define PRID_IMP_R5432 0x5400
|
||||
#define PRID_IMP_R5500 0x5500
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||||
#define PRID_IMP_LOONGSON2 0x6300
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||||
|
||||
#define PRID_IMP_UNKNOWN 0xff00
|
||||
|
||||
|
|
@ -90,8 +92,6 @@
|
|||
#define PRID_IMP_24KE 0x9600
|
||||
#define PRID_IMP_74K 0x9700
|
||||
#define PRID_IMP_1004K 0x9900
|
||||
#define PRID_IMP_LOONGSON1 0x4200
|
||||
#define PRID_IMP_LOONGSON2 0x6300
|
||||
|
||||
/*
|
||||
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
* KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
|
||||
* definitions.
|
||||
*
|
||||
* Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
|
||||
* Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
|
|
@ -54,11 +54,11 @@
|
|||
*/
|
||||
#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
|
||||
#define KN4K_MB_INT_RTC (1<<1) /* RTC? */
|
||||
#define KN4K_MB_INT_MT (1<<3) /* ??? */
|
||||
#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */
|
||||
|
||||
/*
|
||||
* Bits for the MB control & status register.
|
||||
* Set to 0x00bf8001 on my system by the ROM.
|
||||
* Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
|
||||
*/
|
||||
#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
|
||||
#define KN4K_MB_CSR_F (1<<1) /* ??? */
|
||||
|
|
@ -69,7 +69,8 @@
|
|||
#define KN4K_MB_CSR_IM (1<<13) /* ??? */
|
||||
#define KN4K_MB_CSR_NC (1<<14) /* ??? */
|
||||
#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
|
||||
#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */
|
||||
#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */
|
||||
#define KN4K_MB_CSR_FW (1<<21) /* ??? */
|
||||
#define KN4K_MB_CSR_W (1<<31) /* ??? */
|
||||
|
||||
#endif /* __ASM_MIPS_DEC_KN05_H */
|
||||
|
|
|
|||
|
|
@ -1,24 +0,0 @@
|
|||
/*
|
||||
* Miguel de Icaza
|
||||
*/
|
||||
#ifndef __ASM_INVENTORY_H
|
||||
#define __ASM_INVENTORY_H
|
||||
|
||||
#include <linux/compiler.h>
|
||||
|
||||
typedef struct inventory_s {
|
||||
struct inventory_s *inv_next;
|
||||
int inv_class;
|
||||
int inv_type;
|
||||
int inv_controller;
|
||||
int inv_unit;
|
||||
int inv_state;
|
||||
} inventory_t;
|
||||
|
||||
extern int inventory_items;
|
||||
|
||||
extern void add_to_inventory(int class, int type, int controller, int unit, int state);
|
||||
extern int dump_inventory_to_user(void __user *userbuf, int size);
|
||||
extern int __init init_inventory(void);
|
||||
|
||||
#endif /* __ASM_INVENTORY_H */
|
||||
|
|
@ -160,13 +160,6 @@ static inline void * isa_bus_to_virt(unsigned long address)
|
|||
#define virt_to_bus virt_to_phys
|
||||
#define bus_to_virt phys_to_virt
|
||||
|
||||
/*
|
||||
* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
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||||
* for the processor. This implies the assumption that there is only
|
||||
* one of these busses.
|
||||
*/
|
||||
extern unsigned long isa_slot_offset;
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||||
|
||||
/*
|
||||
* Change "struct page" to physical address.
|
||||
*/
|
||||
|
|
@ -527,16 +520,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
|
|||
memcpy((void __force *) dst, src, count);
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||||
}
|
||||
|
||||
/*
|
||||
* ISA space is 'always mapped' on currently supported MIPS systems, no need
|
||||
* to explicitly ioremap() it. The fact that the ISA IO space is mapped
|
||||
* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
|
||||
* are physical addresses. The following constant pointer can be
|
||||
* used as the IO-area pointer (it can be iounmapped as well, so the
|
||||
* analogy with PCI is quite large):
|
||||
*/
|
||||
#define __ISA_IO_base ((char *)(isa_slot_offset))
|
||||
|
||||
/*
|
||||
* The caches on some architectures aren't dma-coherent and have need to
|
||||
* handle this in software. There are three types of operations that
|
||||
|
|
|
|||
|
|
@ -240,6 +240,8 @@ static inline void lasat_ndelay(unsigned int ns)
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|||
__delay(ns / lasat_ndelay_divider);
|
||||
}
|
||||
|
||||
#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000)
|
||||
|
||||
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
|
||||
|
||||
#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
|
||||
|
|
|
|||
|
|
@ -1,60 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 1999, 2000, 2005 MIPS Technologies, Inc.
|
||||
* All rights reserved.
|
||||
* Authors: Carsten Langgaard <carstenl@mips.com>
|
||||
* Maciej W. Rozycki <macro@mips.com>
|
||||
* Copyright (C) 2003, 05 Ralf Baechle (ralf@linux-mips.org)
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*/
|
||||
#ifndef __ASM_MACH_ATLAS_MC146818RTC_H
|
||||
#define __ASM_MACH_ATLAS_MC146818RTC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#include <asm/mips-boards/atlas.h>
|
||||
#include <asm/mips-boards/atlasint.h>
|
||||
|
||||
#define ARCH_RTC_LOCATION
|
||||
|
||||
#define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x) * 8)
|
||||
#define RTC_IO_EXTENT 0x100
|
||||
#define RTC_IOMAPPED 0
|
||||
#define RTC_IRQ ATLAS_INT_RTC
|
||||
|
||||
static inline unsigned char CMOS_READ(unsigned long addr)
|
||||
{
|
||||
volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
|
||||
volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
|
||||
|
||||
*ireg = addr;
|
||||
return *dreg;
|
||||
}
|
||||
|
||||
static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
|
||||
{
|
||||
volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
|
||||
volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
|
||||
|
||||
*ireg = addr;
|
||||
*dreg = data;
|
||||
}
|
||||
|
||||
#define RTC_ALWAYS_BCD 0
|
||||
|
||||
#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
|
||||
|
||||
#endif /* __ASM_MACH_ATLAS_MC146818RTC_H */
|
||||
|
|
@ -145,51 +145,6 @@ typedef volatile struct
|
|||
#define SET_VCC_VPP(VCC, VPP, SLOT)\
|
||||
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
|
||||
|
||||
/*
|
||||
* SD controller macros
|
||||
*/
|
||||
|
||||
/* Detect card. */
|
||||
#define mmc_card_inserted(_n_, _res_) \
|
||||
do { \
|
||||
BCSR * const bcsr = (BCSR *)0xAE000000; \
|
||||
unsigned long mmc_wp, board_specific; \
|
||||
if ((_n_)) { \
|
||||
mmc_wp = BCSR_BOARD_SD1_WP; \
|
||||
} else { \
|
||||
mmc_wp = BCSR_BOARD_SD0_WP; \
|
||||
} \
|
||||
board_specific = au_readl((unsigned long)(&bcsr->specific)); \
|
||||
if (!(board_specific & mmc_wp)) {/* low means card present */ \
|
||||
*(int *)(_res_) = 1; \
|
||||
} else { \
|
||||
*(int *)(_res_) = 0; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* Apply power to card slot(s).
|
||||
*/
|
||||
#define mmc_power_on(_n_) \
|
||||
do { \
|
||||
BCSR * const bcsr = (BCSR *)0xAE000000; \
|
||||
unsigned long mmc_pwr, mmc_wp, board_specific; \
|
||||
if ((_n_)) { \
|
||||
mmc_pwr = BCSR_BOARD_SD1_PWR; \
|
||||
mmc_wp = BCSR_BOARD_SD1_WP; \
|
||||
} else { \
|
||||
mmc_pwr = BCSR_BOARD_SD0_PWR; \
|
||||
mmc_wp = BCSR_BOARD_SD0_WP; \
|
||||
} \
|
||||
board_specific = au_readl((unsigned long)(&bcsr->specific)); \
|
||||
if (!(board_specific & mmc_wp)) {/* low means card present */ \
|
||||
board_specific |= mmc_pwr; \
|
||||
au_writel(board_specific, (int)(&bcsr->specific)); \
|
||||
au_sync(); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
/*
|
||||
* NAND defines
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
/*
|
||||
* include/asm-mips/mach-jmr3927/ioremap.h
|
||||
* include/asm-mips/mach-tx39xx/ioremap.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
#ifndef __ASM_MACH_JMR3927_IOREMAP_H
|
||||
#define __ASM_MACH_JMR3927_IOREMAP_H
|
||||
#ifndef __ASM_MACH_TX39XX_IOREMAP_H
|
||||
#define __ASM_MACH_TX39XX_IOREMAP_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
|
|
@ -35,4 +35,4 @@ static inline int plat_iounmap(const volatile void __iomem *addr)
|
|||
return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
|
||||
}
|
||||
|
||||
#endif /* __ASM_MACH_JMR3927_IOREMAP_H */
|
||||
#endif /* __ASM_MACH_TX39XX_IOREMAP_H */
|
||||
|
|
@ -1,7 +1,12 @@
|
|||
#ifndef __ASM_MACH_JMR3927_MANGLE_PORT_H
|
||||
#define __ASM_MACH_JMR3927_MANGLE_PORT_H
|
||||
#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H
|
||||
#define __ASM_MACH_TX39XX_MANGLE_PORT_H
|
||||
|
||||
extern unsigned long __swizzle_addr_b(unsigned long port);
|
||||
#if defined(CONFIG_TOSHIBA_JMR3927)
|
||||
extern unsigned long (*__swizzle_addr_b)(unsigned long port);
|
||||
#define NEEDS_TXX9_SWIZZLE_ADDR_B
|
||||
#else
|
||||
#define __swizzle_addr_b(port) (port)
|
||||
#endif
|
||||
#define __swizzle_addr_w(port) (port)
|
||||
#define __swizzle_addr_l(port) (port)
|
||||
#define __swizzle_addr_q(port) (port)
|
||||
|
|
@ -15,4 +20,4 @@ extern unsigned long __swizzle_addr_b(unsigned long port);
|
|||
#define ioswabq(a, x) le64_to_cpu(x)
|
||||
#define __mem_ioswabq(a, x) (x)
|
||||
|
||||
#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */
|
||||
#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
|
||||
|
|
@ -5,8 +5,8 @@
|
|||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H
|
||||
#define __ASM_MIPS_MACH_JMR3927_WAR_H
|
||||
#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H
|
||||
#define __ASM_MIPS_MACH_TX39XX_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
|
|
@ -22,4 +22,4 @@
|
|||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */
|
||||
#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */
|
||||
|
|
@ -2,9 +2,6 @@
|
|||
#define __ASM_MACH_VR41XX_IRQ_H
|
||||
|
||||
#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
|
||||
#ifdef CONFIG_NEC_CMBVR4133
|
||||
#include <asm/vr41xx/cmbvr4133.h> /* for I8259A_IRQ_BASE */
|
||||
#endif
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -27,12 +27,8 @@
|
|||
/*
|
||||
* Display register base.
|
||||
*/
|
||||
#ifdef CONFIG_MIPS_SEAD
|
||||
#define ASCII_DISPLAY_POS_BASE 0x1f0005c0
|
||||
#else
|
||||
#define ASCII_DISPLAY_WORD_BASE 0x1f000410
|
||||
#define ASCII_DISPLAY_POS_BASE 0x1f000418
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
|
|
@ -44,13 +40,8 @@
|
|||
/*
|
||||
* Reset register.
|
||||
*/
|
||||
#ifdef CONFIG_MIPS_SEAD
|
||||
#define SOFTRES_REG 0x1e800050
|
||||
#define GORESET 0x4d
|
||||
#else
|
||||
#define SOFTRES_REG 0x1f000500
|
||||
#define GORESET 0x42
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Revision register.
|
||||
|
|
|
|||
|
|
@ -1,26 +1,11 @@
|
|||
#ifndef _ASM_NAMEI_H
|
||||
#define _ASM_NAMEI_H
|
||||
|
||||
#include <linux/personality.h>
|
||||
#include <linux/stddef.h>
|
||||
/*
|
||||
* This dummy routine maybe changed to something useful
|
||||
* for /usr/gnemul/ emulation stuff.
|
||||
*/
|
||||
|
||||
#define IRIX_EMUL "/usr/gnemul/irix/"
|
||||
#define RISCOS_EMUL "/usr/gnemul/riscos/"
|
||||
|
||||
static inline char *__emul_prefix(void)
|
||||
{
|
||||
switch (current->personality) {
|
||||
case PER_IRIX32:
|
||||
case PER_IRIXN32:
|
||||
case PER_IRIX64:
|
||||
return IRIX_EMUL;
|
||||
|
||||
case PER_RISCOS:
|
||||
return RISCOS_EMUL;
|
||||
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
#define __emul_prefix() NULL
|
||||
|
||||
#endif /* _ASM_NAMEI_H */
|
||||
|
|
|
|||
|
|
@ -172,4 +172,7 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
|
|||
return channel ? 15 : 14;
|
||||
}
|
||||
|
||||
extern int pci_probe_only;
|
||||
extern unsigned int pcibios_max_latency;
|
||||
|
||||
#endif /* _ASM_PCI_H */
|
||||
|
|
|
|||
|
|
@ -1,41 +0,0 @@
|
|||
/*
|
||||
* IRIX prctl interface
|
||||
*
|
||||
* The IRIX kernel maps a page at PRDA_ADDRESS with the
|
||||
* contents of prda and fills it the bits on prda_sys.
|
||||
*/
|
||||
|
||||
#ifndef __PRCTL_H__
|
||||
#define __PRCTL_H__
|
||||
|
||||
#define PRDA_ADDRESS 0x200000L
|
||||
#define PRDA ((struct prda *) PRDA_ADDRESS)
|
||||
|
||||
struct prda_sys {
|
||||
pid_t t_pid;
|
||||
u32 t_hint;
|
||||
u32 t_dlactseq;
|
||||
u32 t_fpflags;
|
||||
u32 t_prid; /* processor type, $prid CP0 register */
|
||||
u32 t_dlendseq;
|
||||
u64 t_unused1[5];
|
||||
pid_t t_rpid;
|
||||
s32 t_resched;
|
||||
u32 t_unused[8];
|
||||
u32 t_cpu; /* current/last cpu */
|
||||
|
||||
/* FIXME: The signal information, not supported by Linux now */
|
||||
u32 t_flags; /* if true, then the sigprocmask is in userspace */
|
||||
u32 t_sigprocmask [1]; /* the sigprocmask */
|
||||
};
|
||||
|
||||
struct prda {
|
||||
char fill [0xe00];
|
||||
struct prda_sys prda_sys;
|
||||
};
|
||||
|
||||
#define t_sys prda_sys
|
||||
|
||||
ptrdiff_t prctl(int op, int v1, int v2);
|
||||
|
||||
#endif
|
||||
|
|
@ -3,4 +3,6 @@
|
|||
|
||||
#define COMMAND_LINE_SIZE 256
|
||||
|
||||
extern void setup_early_printk(void);
|
||||
|
||||
#endif /* __SETUP_H */
|
||||
|
|
|
|||
|
|
@ -119,9 +119,6 @@ struct sigaction {
|
|||
|
||||
struct k_sigaction {
|
||||
struct sigaction sa;
|
||||
#ifdef CONFIG_BINFMT_IRIX
|
||||
void (*sa_restorer)(void);
|
||||
#endif
|
||||
};
|
||||
|
||||
/* IRIX compatible stack_t */
|
||||
|
|
|
|||
|
|
@ -24,6 +24,5 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
|
|||
extern void (*board_nmi_handler_setup)(void);
|
||||
extern void (*board_ejtag_handler_setup)(void);
|
||||
extern void (*board_bind_eic_interrupt)(int irq, int regset);
|
||||
extern void (*board_watchpoint_handler)(struct pt_regs *regs);
|
||||
|
||||
#endif /* _ASM_TRAPS_H */
|
||||
|
|
|
|||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* Author: MontaVista Software, Inc.
|
||||
* source@mvista.com
|
||||
*
|
||||
* Copyright 2001-2006 MontaVista Software Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
|
||||
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef __ASM_TX4927_TX4927_H
|
||||
#define __ASM_TX4927_TX4927_H
|
||||
|
||||
#include <asm/txx9irq.h>
|
||||
|
||||
#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
|
||||
#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
|
||||
|
||||
#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE
|
||||
#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
|
||||
|
||||
|
||||
#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
|
||||
#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1)
|
||||
#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2)
|
||||
#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7)
|
||||
|
||||
#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
|
||||
|
||||
#endif /* __ASM_TX4927_TX4927_H */
|
||||
|
|
@ -1,268 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*/
|
||||
#ifndef __ASM_TX4927_TX4927_PCI_H
|
||||
#define __ASM_TX4927_TX4927_PCI_H
|
||||
|
||||
#define TX4927_CCFG_TOE 0x00004000
|
||||
#define TX4927_CCFG_WR 0x00008000
|
||||
#define TX4927_CCFG_TINTDIS 0x01000000
|
||||
|
||||
#define TX4927_PCIMEM 0x08000000
|
||||
#define TX4927_PCIMEM_SIZE 0x08000000
|
||||
#define TX4927_PCIIO 0x16000000
|
||||
#define TX4927_PCIIO_SIZE 0x01000000
|
||||
|
||||
#define TX4927_SDRAMC_REG 0xff1f8000
|
||||
#define TX4927_EBUSC_REG 0xff1f9000
|
||||
#define TX4927_PCIC_REG 0xff1fd000
|
||||
#define TX4927_CCFG_REG 0xff1fe000
|
||||
#define TX4927_IRC_REG 0xff1ff600
|
||||
#define TX4927_NR_TMR 3
|
||||
#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
|
||||
#define TX4927_CE3 0x17f00000 /* 1M */
|
||||
#define TX4927_PCIRESET_ADDR 0xbc00f006
|
||||
#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
|
||||
|
||||
#define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
|
||||
#define tx4927_imstat_ptr(n) \
|
||||
((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
|
||||
|
||||
/* bits for ISTAT3/IMASK3/IMSTAT3 */
|
||||
#define TX4927_INT3B_PCID 0
|
||||
#define TX4927_INT3B_PCIC 1
|
||||
#define TX4927_INT3B_PCIB 2
|
||||
#define TX4927_INT3B_PCIA 3
|
||||
#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
|
||||
#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
|
||||
#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
|
||||
#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
|
||||
|
||||
/* bits for PCI_CLK (S6) */
|
||||
#define TX4927_PCI_CLK_HOST 0x80
|
||||
#define TX4927_PCI_CLK_MASK (0x0f << 3)
|
||||
#define TX4927_PCI_CLK_33 (0x01 << 3)
|
||||
#define TX4927_PCI_CLK_25 (0x04 << 3)
|
||||
#define TX4927_PCI_CLK_66 (0x09 << 3)
|
||||
#define TX4927_PCI_CLK_50 (0x0c << 3)
|
||||
#define TX4927_PCI_CLK_ACK 0x04
|
||||
#define TX4927_PCI_CLK_ACE 0x02
|
||||
#define TX4927_PCI_CLK_ENDIAN 0x01
|
||||
#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
|
||||
#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
|
||||
|
||||
#define TX4927_IR_PCIC 16
|
||||
#define TX4927_IR_PCIERR 22
|
||||
#define TX4927_IR_PCIPMA 23
|
||||
#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
|
||||
#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
|
||||
#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
|
||||
#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
|
||||
#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
|
||||
#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
|
||||
#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
|
||||
|
||||
#ifdef _LANGUAGE_ASSEMBLY
|
||||
#define _CONST64(c) c
|
||||
#else
|
||||
#define _CONST64(c) c##ull
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#define tx4927_pcireset_ptr \
|
||||
((volatile unsigned char *)TX4927_PCIRESET_ADDR)
|
||||
#define tx4927_pci_clk_ptr \
|
||||
((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
|
||||
|
||||
struct tx4927_sdramc_reg {
|
||||
volatile unsigned long long cr[4];
|
||||
volatile unsigned long long unused0[4];
|
||||
volatile unsigned long long tr;
|
||||
volatile unsigned long long unused1[2];
|
||||
volatile unsigned long long cmd;
|
||||
};
|
||||
|
||||
struct tx4927_ebusc_reg {
|
||||
volatile unsigned long long cr[8];
|
||||
};
|
||||
|
||||
struct tx4927_ccfg_reg {
|
||||
volatile unsigned long long ccfg;
|
||||
volatile unsigned long long crir;
|
||||
volatile unsigned long long pcfg;
|
||||
volatile unsigned long long tear;
|
||||
volatile unsigned long long clkctr;
|
||||
volatile unsigned long long unused0;
|
||||
volatile unsigned long long garbc;
|
||||
volatile unsigned long long unused1;
|
||||
volatile unsigned long long unused2;
|
||||
volatile unsigned long long ramp;
|
||||
};
|
||||
|
||||
struct tx4927_pcic_reg {
|
||||
volatile unsigned long pciid;
|
||||
volatile unsigned long pcistatus;
|
||||
volatile unsigned long pciccrev;
|
||||
volatile unsigned long pcicfg1;
|
||||
volatile unsigned long p2gm0plbase; /* +10 */
|
||||
volatile unsigned long p2gm0pubase;
|
||||
volatile unsigned long p2gm1plbase;
|
||||
volatile unsigned long p2gm1pubase;
|
||||
volatile unsigned long p2gm2pbase; /* +20 */
|
||||
volatile unsigned long p2giopbase;
|
||||
volatile unsigned long unused0;
|
||||
volatile unsigned long pcisid;
|
||||
volatile unsigned long unused1; /* +30 */
|
||||
volatile unsigned long pcicapptr;
|
||||
volatile unsigned long unused2;
|
||||
volatile unsigned long pcicfg2;
|
||||
volatile unsigned long g2ptocnt; /* +40 */
|
||||
volatile unsigned long unused3[15];
|
||||
volatile unsigned long g2pstatus; /* +80 */
|
||||
volatile unsigned long g2pmask;
|
||||
volatile unsigned long pcisstatus;
|
||||
volatile unsigned long pcimask;
|
||||
volatile unsigned long p2gcfg; /* +90 */
|
||||
volatile unsigned long p2gstatus;
|
||||
volatile unsigned long p2gmask;
|
||||
volatile unsigned long p2gccmd;
|
||||
volatile unsigned long unused4[24]; /* +a0 */
|
||||
volatile unsigned long pbareqport; /* +100 */
|
||||
volatile unsigned long pbacfg;
|
||||
volatile unsigned long pbastatus;
|
||||
volatile unsigned long pbamask;
|
||||
volatile unsigned long pbabm; /* +110 */
|
||||
volatile unsigned long pbacreq;
|
||||
volatile unsigned long pbacgnt;
|
||||
volatile unsigned long pbacstate;
|
||||
volatile unsigned long long g2pmgbase[3]; /* +120 */
|
||||
volatile unsigned long long g2piogbase;
|
||||
volatile unsigned long g2pmmask[3]; /* +140 */
|
||||
volatile unsigned long g2piomask;
|
||||
volatile unsigned long long g2pmpbase[3]; /* +150 */
|
||||
volatile unsigned long long g2piopbase;
|
||||
volatile unsigned long pciccfg; /* +170 */
|
||||
volatile unsigned long pcicstatus;
|
||||
volatile unsigned long pcicmask;
|
||||
volatile unsigned long unused5;
|
||||
volatile unsigned long long p2gmgbase[3]; /* +180 */
|
||||
volatile unsigned long long p2giogbase;
|
||||
volatile unsigned long g2pcfgadrs; /* +1a0 */
|
||||
volatile unsigned long g2pcfgdata;
|
||||
volatile unsigned long unused6[8];
|
||||
volatile unsigned long g2pintack;
|
||||
volatile unsigned long g2pspc;
|
||||
volatile unsigned long unused7[12]; /* +1d0 */
|
||||
volatile unsigned long long pdmca; /* +200 */
|
||||
volatile unsigned long long pdmga;
|
||||
volatile unsigned long long pdmpa;
|
||||
volatile unsigned long long pdmcut;
|
||||
volatile unsigned long long pdmcnt; /* +220 */
|
||||
volatile unsigned long long pdmsts;
|
||||
volatile unsigned long long unused8[2];
|
||||
volatile unsigned long long pdmdb[4]; /* +240 */
|
||||
volatile unsigned long long pdmtdh; /* +260 */
|
||||
volatile unsigned long long pdmdms;
|
||||
};
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/*
|
||||
* PCIC
|
||||
*/
|
||||
|
||||
/* bits for G2PSTATUS/G2PMASK */
|
||||
#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
|
||||
#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
|
||||
#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
|
||||
|
||||
/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
|
||||
#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
|
||||
|
||||
/* bits for PBACFG */
|
||||
#define TX4927_PCIC_PBACFG_RPBA 0x00000004
|
||||
#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
|
||||
#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
|
||||
|
||||
/* bits for G2PMnGBASE */
|
||||
#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
|
||||
|
||||
/* bits for G2PIOGBASE */
|
||||
#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
|
||||
|
||||
/* bits for PCICSTATUS/PCICMASK */
|
||||
#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
|
||||
|
||||
/* bits for PCICCFG */
|
||||
#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
|
||||
#define TX4927_PCIC_PCICCFG_HRST 0x00000800
|
||||
#define TX4927_PCIC_PCICCFG_SRST 0x00000400
|
||||
#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
|
||||
#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
|
||||
#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
|
||||
#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
|
||||
#define TX4927_PCIC_PCICCFG_IISE 0x00000020
|
||||
#define TX4927_PCIC_PCICCFG_ATR 0x00000010
|
||||
#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
|
||||
|
||||
/* bits for P2GMnGBASE */
|
||||
#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
|
||||
#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
|
||||
|
||||
/* bits for P2GIOGBASE */
|
||||
#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
|
||||
#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
|
||||
|
||||
#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
|
||||
#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
|
||||
|
||||
/*
|
||||
* CCFG
|
||||
*/
|
||||
/* CCFG : Chip Configuration */
|
||||
#define TX4927_CCFG_PCI66 0x00800000
|
||||
#define TX4927_CCFG_PCIMIDE 0x00400000
|
||||
#define TX4927_CCFG_PCIXARB 0x00002000
|
||||
#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
|
||||
#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
|
||||
#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
|
||||
#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
|
||||
#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
|
||||
|
||||
#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
|
||||
#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
|
||||
#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
|
||||
#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
|
||||
#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
|
||||
#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
|
||||
#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
|
||||
#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
|
||||
#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
|
||||
|
||||
/* PCFG : Pin Configuration */
|
||||
#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
|
||||
#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
|
||||
|
||||
/* CLKCTR : Clock Control */
|
||||
#define TX4927_CLKCTR_PCICKD 0x00400000
|
||||
#define TX4927_CLKCTR_PCIRST 0x00000040
|
||||
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
|
||||
#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
|
||||
#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
|
||||
#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
#endif /* __ASM_TX4927_TX4927_PCI_H */
|
||||
41
include/asm-mips/txx9/generic.h
Normal file
41
include/asm-mips/txx9/generic.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* linux/include/asm-mips/txx9/generic.h
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_TXX9_GENERIC_H
|
||||
#define __ASM_TXX9_GENERIC_H
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h> /* for struct resource */
|
||||
|
||||
extern struct resource txx9_ce_res[];
|
||||
extern char txx9_pcode_str[8];
|
||||
void txx9_reg_res_init(unsigned int pcode, unsigned long base,
|
||||
unsigned long size);
|
||||
|
||||
extern unsigned int txx9_master_clock;
|
||||
extern unsigned int txx9_cpu_clock;
|
||||
extern unsigned int txx9_gbus_clock;
|
||||
|
||||
struct pci_dev;
|
||||
struct txx9_board_vec {
|
||||
const char *system;
|
||||
void (*prom_init)(void);
|
||||
void (*mem_setup)(void);
|
||||
void (*irq_setup)(void);
|
||||
void (*time_init)(void);
|
||||
void (*arch_init)(void);
|
||||
void (*device_init)(void);
|
||||
#ifdef CONFIG_PCI
|
||||
int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
|
||||
#endif
|
||||
};
|
||||
extern struct txx9_board_vec *txx9_board_vec;
|
||||
extern int (*txx9_irq_dispatch)(int pending);
|
||||
void prom_init_cmdline(void);
|
||||
char *prom_getcmdline(void);
|
||||
|
||||
#endif /* __ASM_TXX9_GENERIC_H */
|
||||
|
|
@ -7,10 +7,10 @@
|
|||
*
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*/
|
||||
#ifndef __ASM_TX3927_JMR3927_H
|
||||
#define __ASM_TX3927_JMR3927_H
|
||||
#ifndef __ASM_TXX9_JMR3927_H
|
||||
#define __ASM_TXX9_JMR3927_H
|
||||
|
||||
#include <asm/jmr3927/tx3927.h>
|
||||
#include <asm/txx9/tx3927.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/txx9irq.h>
|
||||
|
|
@ -174,4 +174,9 @@
|
|||
* INT[3:0]
|
||||
*/
|
||||
|
||||
#endif /* __ASM_TX3927_JMR3927_H */
|
||||
void jmr3927_prom_init(void);
|
||||
void jmr3927_irq_setup(void);
|
||||
struct pci_dev;
|
||||
int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
|
||||
|
||||
#endif /* __ASM_TXX9_JMR3927_H */
|
||||
36
include/asm-mips/txx9/pci.h
Normal file
36
include/asm-mips/txx9/pci.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_TXX9_PCI_H
|
||||
#define __ASM_TXX9_PCI_H
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
extern struct pci_controller txx9_primary_pcic;
|
||||
struct pci_controller *
|
||||
txx9_alloc_pci_controller(struct pci_controller *pcic,
|
||||
unsigned long mem_base, unsigned long mem_size,
|
||||
unsigned long io_base, unsigned long io_size);
|
||||
|
||||
int txx9_pci66_check(struct pci_controller *hose, int top_bus,
|
||||
int current_bus);
|
||||
extern int txx9_pci_mem_high __initdata;
|
||||
|
||||
extern int txx9_pci_option;
|
||||
#define TXX9_PCI_OPT_PICMG 0x0002
|
||||
#define TXX9_PCI_OPT_CLK_33 0x0008
|
||||
#define TXX9_PCI_OPT_CLK_66 0x0010
|
||||
#define TXX9_PCI_OPT_CLK_MASK \
|
||||
(TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
|
||||
#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK
|
||||
|
||||
enum txx9_pci_err_action {
|
||||
TXX9_PCI_ERR_REPORT,
|
||||
TXX9_PCI_ERR_IGNORE,
|
||||
TXX9_PCI_ERR_PANIC,
|
||||
};
|
||||
extern enum txx9_pci_err_action txx9_pci_err_action;
|
||||
|
||||
#endif /* __ASM_TXX9_PCI_H */
|
||||
|
|
@ -24,18 +24,42 @@
|
|||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H
|
||||
#define __ASM_TX4927_TOSHIBA_RBTX4927_H
|
||||
#ifndef __ASM_TXX9_RBTX4927_H
|
||||
#define __ASM_TXX9_RBTX4927_H
|
||||
|
||||
#include <asm/tx4927/tx4927.h>
|
||||
#ifdef CONFIG_PCI
|
||||
#include <asm/tx4927/tx4927_pci.h>
|
||||
#endif
|
||||
#include <asm/txx9/tx4927.h>
|
||||
|
||||
#define RBTX4927_PCIMEM 0x08000000
|
||||
#define RBTX4927_PCIMEM_SIZE 0x08000000
|
||||
#define RBTX4927_PCIIO 0x16000000
|
||||
#define RBTX4927_PCIIO_SIZE 0x01000000
|
||||
|
||||
#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL)
|
||||
|
||||
/* bits for ISTAT/IMASK/IMSTAT */
|
||||
#define RBTX4927_INTB_PCID 0
|
||||
#define RBTX4927_INTB_PCIC 1
|
||||
#define RBTX4927_INTB_PCIB 2
|
||||
#define RBTX4927_INTB_PCIA 3
|
||||
#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID)
|
||||
#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC)
|
||||
#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB)
|
||||
#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA)
|
||||
|
||||
#define RBTX4927_NR_IRQ_IOC 8 /* IOC */
|
||||
|
||||
#define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR)
|
||||
#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
|
||||
#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
|
||||
#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
|
||||
#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
|
||||
|
||||
#define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1))
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
|
||||
#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
|
||||
#else
|
||||
#define TBTX4927_ISA_IO_OFFSET 0
|
||||
#define RBTX4927_ISA_IO_OFFSET 0
|
||||
#endif
|
||||
|
||||
#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL
|
||||
|
|
@ -44,10 +68,12 @@
|
|||
#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
|
||||
#define RBTX4927_SW_RESET_ENABLE_SET 0x01
|
||||
|
||||
#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET)
|
||||
#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3))
|
||||
|
||||
#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
|
||||
#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5)
|
||||
void rbtx4927_prom_init(void);
|
||||
void rbtx4927_irq_setup(void);
|
||||
struct pci_dev;
|
||||
int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
|
||||
|
||||
int toshiba_rbtx4927_irq_nested(int sw_irq);
|
||||
|
||||
#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */
|
||||
#endif /* __ASM_TXX9_RBTX4927_H */
|
||||
|
|
@ -1,5 +1,4 @@
|
|||
/*
|
||||
* linux/include/asm-mips/tx4938/rbtx4938.h
|
||||
* Definitions for TX4937/TX4938
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
|
|
@ -9,12 +8,12 @@
|
|||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
#ifndef __ASM_TX_BOARDS_RBTX4938_H
|
||||
#define __ASM_TX_BOARDS_RBTX4938_H
|
||||
#ifndef __ASM_TXX9_RBTX4938_H
|
||||
#define __ASM_TXX9_RBTX4938_H
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/tx4938/tx4938.h>
|
||||
#include <asm/txx9irq.h>
|
||||
#include <asm/txx9/tx4938.h>
|
||||
|
||||
/* CS */
|
||||
#define RBTX4938_CE0 0x1c000000 /* 64M */
|
||||
|
|
@ -102,35 +101,12 @@
|
|||
* that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
|
||||
* IRQ hardware is supported.
|
||||
*/
|
||||
#define RBTX4938_NR_IRQ_LOCAL 8
|
||||
#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
|
||||
#define RBTX4938_NR_IRQ_IOC 8
|
||||
|
||||
#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
|
||||
#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
|
||||
|
||||
#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE
|
||||
#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
|
||||
#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
|
||||
#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
|
||||
#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
|
||||
#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1)
|
||||
#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7)
|
||||
|
||||
#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0
|
||||
#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7
|
||||
|
||||
#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
|
||||
#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
|
||||
#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG
|
||||
#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
|
||||
#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
|
||||
#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE
|
||||
#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
|
||||
#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
|
||||
|
||||
#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
|
||||
#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
|
||||
#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
|
||||
#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
|
||||
#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
|
||||
#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
|
||||
#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
|
||||
|
|
@ -158,11 +134,16 @@
|
|||
|
||||
|
||||
/* IOC (PCI, etc) */
|
||||
#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC)
|
||||
#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0))
|
||||
/* Onboard 10M Ether */
|
||||
#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
|
||||
#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1))
|
||||
|
||||
#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
|
||||
#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
|
||||
|
||||
#endif /* __ASM_TX_BOARDS_RBTX4938_H */
|
||||
void rbtx4938_prom_init(void);
|
||||
void rbtx4938_irq_setup(void);
|
||||
struct pci_dev;
|
||||
int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
|
||||
|
||||
#endif /* __ASM_TXX9_RBTX4938_H */
|
||||
|
|
@ -1,6 +1,4 @@
|
|||
/*
|
||||
* linux/include/asm-mips/tx4927/smsc_fdc37m81x.h
|
||||
*
|
||||
* Interface for smsc fdc48m81x Super IO chip
|
||||
*
|
||||
* Author: MontaVista Software, Inc. source@mvista.com
|
||||
|
|
@ -1,5 +1,4 @@
|
|||
/*
|
||||
* linux/include/asm-mips/tx4938/spi.h
|
||||
* Definitions for TX4937/TX4938 SPI
|
||||
*
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
|
|
@ -11,10 +10,10 @@
|
|||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
|
||||
#define __ASM_TX_BOARDS_TX4938_SPI_H
|
||||
#ifndef __ASM_TXX9_SPI_H
|
||||
#define __ASM_TXX9_SPI_H
|
||||
|
||||
extern int spi_eeprom_register(int chipid);
|
||||
extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
|
||||
|
||||
#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
|
||||
#endif /* __ASM_TXX9_SPI_H */
|
||||
|
|
@ -5,10 +5,10 @@
|
|||
*
|
||||
* Copyright (C) 2000 Toshiba Corporation
|
||||
*/
|
||||
#ifndef __ASM_TX3927_H
|
||||
#define __ASM_TX3927_H
|
||||
#ifndef __ASM_TXX9_TX3927_H
|
||||
#define __ASM_TXX9_TX3927_H
|
||||
|
||||
#include <asm/jmr3927/txx927.h>
|
||||
#include <asm/txx9/txx927.h>
|
||||
|
||||
#define TX3927_SDRAMC_REG 0xfffe8000
|
||||
#define TX3927_ROMC_REG 0xfffe9000
|
||||
|
|
@ -316,4 +316,8 @@ struct tx3927_ccfg_reg {
|
|||
#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
|
||||
#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
|
||||
|
||||
#endif /* __ASM_TX3927_H */
|
||||
struct pci_controller;
|
||||
void __init tx3927_pcic_setup(struct pci_controller *channel,
|
||||
unsigned long sdram_size, int extarb);
|
||||
|
||||
#endif /* __ASM_TXX9_TX3927_H */
|
||||
219
include/asm-mips/txx9/tx4927.h
Normal file
219
include/asm-mips/txx9/tx4927.h
Normal file
|
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* Author: MontaVista Software, Inc.
|
||||
* source@mvista.com
|
||||
*
|
||||
* Copyright 2001-2006 MontaVista Software Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
|
||||
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef __ASM_TXX9_TX4927_H
|
||||
#define __ASM_TXX9_TX4927_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/txx9irq.h>
|
||||
#include <asm/txx9/tx4927pcic.h>
|
||||
|
||||
#define TX4927_SDRAMC_REG 0xff1f8000
|
||||
#define TX4927_EBUSC_REG 0xff1f9000
|
||||
#define TX4927_PCIC_REG 0xff1fd000
|
||||
#define TX4927_CCFG_REG 0xff1fe000
|
||||
#define TX4927_IRC_REG 0xff1ff600
|
||||
#define TX4927_NR_TMR 3
|
||||
#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
|
||||
|
||||
#define TX4927_IR_INT(n) (2 + (n))
|
||||
#define TX4927_IR_SIO(n) (8 + (n))
|
||||
#define TX4927_IR_PCIC 16
|
||||
#define TX4927_IR_PCIERR 22
|
||||
#define TX4927_NUM_IR 32
|
||||
|
||||
#define TX4927_IRC_INT 2 /* IP[2] in Status register */
|
||||
|
||||
struct tx4927_sdramc_reg {
|
||||
volatile unsigned long long cr[4];
|
||||
volatile unsigned long long unused0[4];
|
||||
volatile unsigned long long tr;
|
||||
volatile unsigned long long unused1[2];
|
||||
volatile unsigned long long cmd;
|
||||
};
|
||||
|
||||
struct tx4927_ebusc_reg {
|
||||
volatile unsigned long long cr[8];
|
||||
};
|
||||
|
||||
struct tx4927_ccfg_reg {
|
||||
u64 ccfg;
|
||||
u64 crir;
|
||||
u64 pcfg;
|
||||
u64 toea;
|
||||
u64 clkctr;
|
||||
u64 unused0;
|
||||
u64 garbc;
|
||||
u64 unused1;
|
||||
u64 unused2;
|
||||
u64 ramp;
|
||||
};
|
||||
|
||||
/*
|
||||
* CCFG
|
||||
*/
|
||||
/* CCFG : Chip Configuration */
|
||||
#define TX4927_CCFG_WDRST 0x0000020000000000ULL
|
||||
#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
|
||||
#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
|
||||
#define TX4927_CCFG_TINTDIS 0x01000000
|
||||
#define TX4927_CCFG_PCI66 0x00800000
|
||||
#define TX4927_CCFG_PCIMODE 0x00400000
|
||||
#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
|
||||
#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
|
||||
#define TX4927_CCFG_BEOW 0x00010000
|
||||
#define TX4927_CCFG_WR 0x00008000
|
||||
#define TX4927_CCFG_TOE 0x00004000
|
||||
#define TX4927_CCFG_PCIARB 0x00002000
|
||||
#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
|
||||
#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
|
||||
#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
|
||||
#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
|
||||
#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
|
||||
#define TX4927_CCFG_SYSSP_MASK 0x000000c0
|
||||
#define TX4927_CCFG_ENDIAN 0x00000004
|
||||
#define TX4927_CCFG_HALT 0x00000002
|
||||
#define TX4927_CCFG_ACEHOLD 0x00000001
|
||||
#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
|
||||
|
||||
/* PCFG : Pin Configuration */
|
||||
#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
|
||||
#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
|
||||
#define TX4927_PCFG_SYSCLKEN 0x08000000
|
||||
#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
|
||||
#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
|
||||
#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
|
||||
#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
|
||||
#define TX4927_PCFG_SEL2 0x00000200
|
||||
#define TX4927_PCFG_SEL1 0x00000100
|
||||
#define TX4927_PCFG_DMASEL_ALL 0x000000ff
|
||||
#define TX4927_PCFG_DMASEL0_MASK 0x00000003
|
||||
#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
|
||||
#define TX4927_PCFG_DMASEL2_MASK 0x00000030
|
||||
#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
|
||||
#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
|
||||
#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
|
||||
#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
|
||||
#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
|
||||
#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
|
||||
#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
|
||||
#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
|
||||
#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
|
||||
#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
|
||||
#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
|
||||
#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
|
||||
#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
|
||||
#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
|
||||
#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
|
||||
#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
|
||||
#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
|
||||
#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
|
||||
|
||||
/* CLKCTR : Clock Control */
|
||||
#define TX4927_CLKCTR_ACLCKD 0x02000000
|
||||
#define TX4927_CLKCTR_PIOCKD 0x01000000
|
||||
#define TX4927_CLKCTR_DMACKD 0x00800000
|
||||
#define TX4927_CLKCTR_PCICKD 0x00400000
|
||||
#define TX4927_CLKCTR_TM0CKD 0x00100000
|
||||
#define TX4927_CLKCTR_TM1CKD 0x00080000
|
||||
#define TX4927_CLKCTR_TM2CKD 0x00040000
|
||||
#define TX4927_CLKCTR_SIO0CKD 0x00020000
|
||||
#define TX4927_CLKCTR_SIO1CKD 0x00010000
|
||||
#define TX4927_CLKCTR_ACLRST 0x00000200
|
||||
#define TX4927_CLKCTR_PIORST 0x00000100
|
||||
#define TX4927_CLKCTR_DMARST 0x00000080
|
||||
#define TX4927_CLKCTR_PCIRST 0x00000040
|
||||
#define TX4927_CLKCTR_TM0RST 0x00000010
|
||||
#define TX4927_CLKCTR_TM1RST 0x00000008
|
||||
#define TX4927_CLKCTR_TM2RST 0x00000004
|
||||
#define TX4927_CLKCTR_SIO0RST 0x00000002
|
||||
#define TX4927_CLKCTR_SIO1RST 0x00000001
|
||||
|
||||
#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
|
||||
#define tx4927_pcicptr \
|
||||
((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
|
||||
#define tx4927_ccfgptr \
|
||||
((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
|
||||
#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
|
||||
|
||||
/* utilities */
|
||||
static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
|
||||
{
|
||||
#ifdef CONFIG_32BIT
|
||||
unsigned long flags;
|
||||
local_irq_save(flags);
|
||||
#endif
|
||||
____raw_writeq(____raw_readq(adr) & ~bits, adr);
|
||||
#ifdef CONFIG_32BIT
|
||||
local_irq_restore(flags);
|
||||
#endif
|
||||
}
|
||||
static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
|
||||
{
|
||||
#ifdef CONFIG_32BIT
|
||||
unsigned long flags;
|
||||
local_irq_save(flags);
|
||||
#endif
|
||||
____raw_writeq(____raw_readq(adr) | bits, adr);
|
||||
#ifdef CONFIG_32BIT
|
||||
local_irq_restore(flags);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* These functions are not interrupt safe. */
|
||||
static inline void tx4927_ccfg_clear(__u64 bits)
|
||||
{
|
||||
____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
|
||||
& ~(TX4927_CCFG_W1CBITS | bits),
|
||||
&tx4927_ccfgptr->ccfg);
|
||||
}
|
||||
static inline void tx4927_ccfg_set(__u64 bits)
|
||||
{
|
||||
____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
|
||||
& ~TX4927_CCFG_W1CBITS) | bits,
|
||||
&tx4927_ccfgptr->ccfg);
|
||||
}
|
||||
static inline void tx4927_ccfg_change(__u64 change, __u64 new)
|
||||
{
|
||||
____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
|
||||
& ~(TX4927_CCFG_W1CBITS | change)) |
|
||||
new,
|
||||
&tx4927_ccfgptr->ccfg);
|
||||
}
|
||||
|
||||
int tx4927_report_pciclk(void);
|
||||
int tx4927_pciclk66_setup(void);
|
||||
void tx4927_irq_init(void);
|
||||
|
||||
#endif /* __ASM_TXX9_TX4927_H */
|
||||
199
include/asm-mips/txx9/tx4927pcic.h
Normal file
199
include/asm-mips/txx9/tx4927pcic.h
Normal file
|
|
@ -0,0 +1,199 @@
|
|||
/*
|
||||
* include/asm-mips/txx9/tx4927pcic.h
|
||||
* TX4927 PCI controller definitions.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_TXX9_TX4927PCIC_H
|
||||
#define __ASM_TXX9_TX4927PCIC_H
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
struct tx4927_pcic_reg {
|
||||
u32 pciid;
|
||||
u32 pcistatus;
|
||||
u32 pciccrev;
|
||||
u32 pcicfg1;
|
||||
u32 p2gm0plbase; /* +10 */
|
||||
u32 p2gm0pubase;
|
||||
u32 p2gm1plbase;
|
||||
u32 p2gm1pubase;
|
||||
u32 p2gm2pbase; /* +20 */
|
||||
u32 p2giopbase;
|
||||
u32 unused0;
|
||||
u32 pcisid;
|
||||
u32 unused1; /* +30 */
|
||||
u32 pcicapptr;
|
||||
u32 unused2;
|
||||
u32 pcicfg2;
|
||||
u32 g2ptocnt; /* +40 */
|
||||
u32 unused3[15];
|
||||
u32 g2pstatus; /* +80 */
|
||||
u32 g2pmask;
|
||||
u32 pcisstatus;
|
||||
u32 pcimask;
|
||||
u32 p2gcfg; /* +90 */
|
||||
u32 p2gstatus;
|
||||
u32 p2gmask;
|
||||
u32 p2gccmd;
|
||||
u32 unused4[24]; /* +a0 */
|
||||
u32 pbareqport; /* +100 */
|
||||
u32 pbacfg;
|
||||
u32 pbastatus;
|
||||
u32 pbamask;
|
||||
u32 pbabm; /* +110 */
|
||||
u32 pbacreq;
|
||||
u32 pbacgnt;
|
||||
u32 pbacstate;
|
||||
u64 g2pmgbase[3]; /* +120 */
|
||||
u64 g2piogbase;
|
||||
u32 g2pmmask[3]; /* +140 */
|
||||
u32 g2piomask;
|
||||
u64 g2pmpbase[3]; /* +150 */
|
||||
u64 g2piopbase;
|
||||
u32 pciccfg; /* +170 */
|
||||
u32 pcicstatus;
|
||||
u32 pcicmask;
|
||||
u32 unused5;
|
||||
u64 p2gmgbase[3]; /* +180 */
|
||||
u64 p2giogbase;
|
||||
u32 g2pcfgadrs; /* +1a0 */
|
||||
u32 g2pcfgdata;
|
||||
u32 unused6[8];
|
||||
u32 g2pintack;
|
||||
u32 g2pspc;
|
||||
u32 unused7[12]; /* +1d0 */
|
||||
u64 pdmca; /* +200 */
|
||||
u64 pdmga;
|
||||
u64 pdmpa;
|
||||
u64 pdmctr;
|
||||
u64 pdmcfg; /* +220 */
|
||||
u64 pdmsts;
|
||||
};
|
||||
|
||||
/* bits for PCICMD */
|
||||
/* see PCI_COMMAND_XXX in linux/pci_regs.h */
|
||||
|
||||
/* bits for PCISTAT */
|
||||
/* see PCI_STATUS_XXX in linux/pci_regs.h */
|
||||
|
||||
/* bits for IOBA/MBA */
|
||||
/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
|
||||
|
||||
/* bits for G2PSTATUS/G2PMASK */
|
||||
#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
|
||||
#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
|
||||
#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
|
||||
|
||||
/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
|
||||
#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
|
||||
|
||||
/* bits for PBACFG */
|
||||
#define TX4927_PCIC_PBACFG_FIXPA 0x00000008
|
||||
#define TX4927_PCIC_PBACFG_RPBA 0x00000004
|
||||
#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
|
||||
#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
|
||||
|
||||
/* bits for PBASTATUS/PBAMASK */
|
||||
#define TX4927_PCIC_PBASTATUS_ALL 0x00000001
|
||||
#define TX4927_PCIC_PBASTATUS_BM 0x00000001
|
||||
|
||||
/* bits for G2PMnGBASE */
|
||||
#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL
|
||||
#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL
|
||||
|
||||
/* bits for G2PIOGBASE */
|
||||
#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL
|
||||
#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL
|
||||
|
||||
/* bits for PCICSTATUS/PCICMASK */
|
||||
#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8
|
||||
#define TX4927_PCIC_PCICSTATUS_PME 0x00000400
|
||||
#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200
|
||||
#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100
|
||||
#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080
|
||||
#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020
|
||||
#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010
|
||||
#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008
|
||||
#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002
|
||||
#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001
|
||||
|
||||
/* bits for PCICCFG */
|
||||
#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
|
||||
#define TX4927_PCIC_PCICCFG_HRST 0x00000800
|
||||
#define TX4927_PCIC_PCICCFG_SRST 0x00000400
|
||||
#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
|
||||
#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
|
||||
#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100
|
||||
#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080
|
||||
#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040
|
||||
#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020
|
||||
#define TX4927_PCIC_PCICCFG_TCAR 0x00000010
|
||||
#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008
|
||||
|
||||
/* bits for P2GMnGBASE */
|
||||
#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL
|
||||
#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL
|
||||
#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL
|
||||
|
||||
/* bits for P2GIOGBASE */
|
||||
#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL
|
||||
#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL
|
||||
#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL
|
||||
|
||||
#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
|
||||
#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
|
||||
|
||||
/* bits for PDMCFG */
|
||||
#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000
|
||||
#define TX4927_PCIC_PDMCFG_EXFER 0x00100000
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
|
||||
#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400
|
||||
#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200
|
||||
#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100
|
||||
#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080
|
||||
#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040
|
||||
#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
|
||||
#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002
|
||||
#define TX4927_PCIC_PDMCFG_CHRST 0x00000001
|
||||
|
||||
/* bits for PDMSTS */
|
||||
#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
|
||||
#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
|
||||
#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
|
||||
#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
|
||||
#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800
|
||||
#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400
|
||||
#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200
|
||||
#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100
|
||||
#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080
|
||||
#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040
|
||||
#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020
|
||||
#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008
|
||||
#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004
|
||||
#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002
|
||||
#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001
|
||||
#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0
|
||||
#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f
|
||||
|
||||
struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
|
||||
struct pci_controller *channel);
|
||||
void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
|
||||
struct pci_controller *channel, int extarb);
|
||||
void tx4927_report_pcic_status(void);
|
||||
|
||||
#endif /* __ASM_TXX9_TX4927PCIC_H */
|
||||
|
|
@ -1,5 +1,4 @@
|
|||
/*
|
||||
* linux/include/asm-mips/tx4938/tx4938.h
|
||||
* Definitions for TX4937/TX4938
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*
|
||||
|
|
@ -10,17 +9,15 @@
|
|||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
#ifndef __ASM_TX_BOARDS_TX4938_H
|
||||
#define __ASM_TX_BOARDS_TX4938_H
|
||||
#ifndef __ASM_TXX9_TX4938_H
|
||||
#define __ASM_TXX9_TX4938_H
|
||||
|
||||
/* some controllers are compatible with 4927 */
|
||||
#include <asm/txx9/tx4927.h>
|
||||
|
||||
#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
|
||||
#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
|
||||
|
||||
#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG
|
||||
|
||||
#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
|
||||
#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
|
||||
|
||||
#define TX4938_PCIIO_0 0x10000000
|
||||
#define TX4938_PCIIO_1 0x01010000
|
||||
#define TX4938_PCIMEM_0 0x08000000
|
||||
|
|
@ -52,9 +49,6 @@
|
|||
#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
|
||||
#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _CONST64(c) c
|
||||
#else
|
||||
#define _CONST64(c) c##ull
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
|
|
@ -114,68 +108,6 @@ struct tx4938_dma_reg {
|
|||
endian_def_l2(unused0, mcr);
|
||||
};
|
||||
|
||||
struct tx4938_pcic_reg {
|
||||
volatile unsigned long pciid;
|
||||
volatile unsigned long pcistatus;
|
||||
volatile unsigned long pciccrev;
|
||||
volatile unsigned long pcicfg1;
|
||||
volatile unsigned long p2gm0plbase; /* +10 */
|
||||
volatile unsigned long p2gm0pubase;
|
||||
volatile unsigned long p2gm1plbase;
|
||||
volatile unsigned long p2gm1pubase;
|
||||
volatile unsigned long p2gm2pbase; /* +20 */
|
||||
volatile unsigned long p2giopbase;
|
||||
volatile unsigned long unused0;
|
||||
volatile unsigned long pcisid;
|
||||
volatile unsigned long unused1; /* +30 */
|
||||
volatile unsigned long pcicapptr;
|
||||
volatile unsigned long unused2;
|
||||
volatile unsigned long pcicfg2;
|
||||
volatile unsigned long g2ptocnt; /* +40 */
|
||||
volatile unsigned long unused3[15];
|
||||
volatile unsigned long g2pstatus; /* +80 */
|
||||
volatile unsigned long g2pmask;
|
||||
volatile unsigned long pcisstatus;
|
||||
volatile unsigned long pcimask;
|
||||
volatile unsigned long p2gcfg; /* +90 */
|
||||
volatile unsigned long p2gstatus;
|
||||
volatile unsigned long p2gmask;
|
||||
volatile unsigned long p2gccmd;
|
||||
volatile unsigned long unused4[24]; /* +a0 */
|
||||
volatile unsigned long pbareqport; /* +100 */
|
||||
volatile unsigned long pbacfg;
|
||||
volatile unsigned long pbastatus;
|
||||
volatile unsigned long pbamask;
|
||||
volatile unsigned long pbabm; /* +110 */
|
||||
volatile unsigned long pbacreq;
|
||||
volatile unsigned long pbacgnt;
|
||||
volatile unsigned long pbacstate;
|
||||
volatile unsigned long long g2pmgbase[3]; /* +120 */
|
||||
volatile unsigned long long g2piogbase;
|
||||
volatile unsigned long g2pmmask[3]; /* +140 */
|
||||
volatile unsigned long g2piomask;
|
||||
volatile unsigned long long g2pmpbase[3]; /* +150 */
|
||||
volatile unsigned long long g2piopbase;
|
||||
volatile unsigned long pciccfg; /* +170 */
|
||||
volatile unsigned long pcicstatus;
|
||||
volatile unsigned long pcicmask;
|
||||
volatile unsigned long unused5;
|
||||
volatile unsigned long long p2gmgbase[3]; /* +180 */
|
||||
volatile unsigned long long p2giogbase;
|
||||
volatile unsigned long g2pcfgadrs; /* +1a0 */
|
||||
volatile unsigned long g2pcfgdata;
|
||||
volatile unsigned long unused6[8];
|
||||
volatile unsigned long g2pintack;
|
||||
volatile unsigned long g2pspc;
|
||||
volatile unsigned long unused7[12]; /* +1d0 */
|
||||
volatile unsigned long long pdmca; /* +200 */
|
||||
volatile unsigned long long pdmga;
|
||||
volatile unsigned long long pdmpa;
|
||||
volatile unsigned long long pdmctr;
|
||||
volatile unsigned long long pdmcfg; /* +220 */
|
||||
volatile unsigned long long pdmsts;
|
||||
};
|
||||
|
||||
struct tx4938_aclc_reg {
|
||||
volatile unsigned long acctlen;
|
||||
volatile unsigned long acctldis;
|
||||
|
|
@ -263,18 +195,18 @@ struct tx4938_sramc_reg {
|
|||
};
|
||||
|
||||
struct tx4938_ccfg_reg {
|
||||
volatile unsigned long long ccfg;
|
||||
volatile unsigned long long crir;
|
||||
volatile unsigned long long pcfg;
|
||||
volatile unsigned long long tear;
|
||||
volatile unsigned long long clkctr;
|
||||
volatile unsigned long long unused0;
|
||||
volatile unsigned long long garbc;
|
||||
volatile unsigned long long unused1;
|
||||
volatile unsigned long long unused2;
|
||||
volatile unsigned long long ramp;
|
||||
volatile unsigned long long unused3;
|
||||
volatile unsigned long long jmpadr;
|
||||
u64 ccfg;
|
||||
u64 crir;
|
||||
u64 pcfg;
|
||||
u64 toea;
|
||||
u64 clkctr;
|
||||
u64 unused0;
|
||||
u64 garbc;
|
||||
u64 unused1;
|
||||
u64 unused2;
|
||||
u64 ramp;
|
||||
u64 unused3;
|
||||
u64 jmpadr;
|
||||
};
|
||||
|
||||
#undef endian_def_l2
|
||||
|
|
@ -283,8 +215,6 @@ struct tx4938_ccfg_reg {
|
|||
#undef endian_def_b2s
|
||||
#undef endian_def_b4
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* NDFMC
|
||||
*/
|
||||
|
|
@ -336,6 +266,8 @@ struct tx4938_ccfg_reg {
|
|||
#define TX4938_IR_ETH0 TX4938_IR_INT(4)
|
||||
#define TX4938_IR_ETH1 TX4938_IR_INT(3)
|
||||
|
||||
#define TX4938_IRC_INT 2 /* IP[2] in Status register */
|
||||
|
||||
/*
|
||||
* CCFG
|
||||
*/
|
||||
|
|
@ -361,7 +293,7 @@ struct tx4938_ccfg_reg {
|
|||
#define TX4938_CCFG_BEOW 0x00010000
|
||||
#define TX4938_CCFG_WR 0x00008000
|
||||
#define TX4938_CCFG_TOE 0x00004000
|
||||
#define TX4938_CCFG_PCIXARB 0x00002000
|
||||
#define TX4938_CCFG_PCIARB 0x00002000
|
||||
#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
|
||||
#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
|
||||
#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
|
||||
|
|
@ -437,110 +369,6 @@ struct tx4938_ccfg_reg {
|
|||
#define TX4938_CLKCTR_SIO0RST 0x00000002
|
||||
#define TX4938_CLKCTR_SIO1RST 0x00000001
|
||||
|
||||
/* bits for G2PSTATUS/G2PMASK */
|
||||
#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003
|
||||
#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002
|
||||
#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001
|
||||
|
||||
/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
|
||||
#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900
|
||||
|
||||
/* bits for PBACFG */
|
||||
#define TX4938_PCIC_PBACFG_FIXPA 0x00000008
|
||||
#define TX4938_PCIC_PBACFG_RPBA 0x00000004
|
||||
#define TX4938_PCIC_PBACFG_PBAEN 0x00000002
|
||||
#define TX4938_PCIC_PBACFG_BMCEN 0x00000001
|
||||
|
||||
/* bits for G2PMnGBASE */
|
||||
#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
|
||||
|
||||
/* bits for G2PIOGBASE */
|
||||
#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
|
||||
|
||||
/* bits for PCICSTATUS/PCICMASK */
|
||||
#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8
|
||||
#define TX4938_PCIC_PCICSTATUS_PME 0x00000400
|
||||
#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200
|
||||
#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100
|
||||
#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080
|
||||
#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020
|
||||
#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010
|
||||
#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008
|
||||
#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002
|
||||
#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001
|
||||
|
||||
/* bits for PCICCFG */
|
||||
#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
|
||||
#define TX4938_PCIC_PCICCFG_HRST 0x00000800
|
||||
#define TX4938_PCIC_PCICCFG_SRST 0x00000400
|
||||
#define TX4938_PCIC_PCICCFG_IRBER 0x00000200
|
||||
#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
|
||||
#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100
|
||||
#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080
|
||||
#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040
|
||||
#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020
|
||||
#define TX4938_PCIC_PCICCFG_TCAR 0x00000010
|
||||
#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008
|
||||
|
||||
/* bits for P2GMnGBASE */
|
||||
#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
|
||||
#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
|
||||
|
||||
/* bits for P2GIOGBASE */
|
||||
#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
|
||||
#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
|
||||
#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
|
||||
|
||||
#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
|
||||
#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
|
||||
|
||||
/* bits for PDMCFG */
|
||||
#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000
|
||||
#define TX4938_PCIC_PDMCFG_EXFER 0x00100000
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
|
||||
#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400
|
||||
#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200
|
||||
#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100
|
||||
#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080
|
||||
#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040
|
||||
#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020
|
||||
#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
|
||||
#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
|
||||
#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
|
||||
#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
|
||||
#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002
|
||||
#define TX4938_PCIC_PDMCFG_CHRST 0x00000001
|
||||
|
||||
/* bits for PDMSTS */
|
||||
#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
|
||||
#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
|
||||
#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
|
||||
#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000
|
||||
#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800
|
||||
#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400
|
||||
#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200
|
||||
#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100
|
||||
#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080
|
||||
#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040
|
||||
#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020
|
||||
#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008
|
||||
#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004
|
||||
#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002
|
||||
#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001
|
||||
#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0
|
||||
#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f
|
||||
|
||||
/*
|
||||
* DMA
|
||||
*/
|
||||
|
|
@ -596,15 +424,15 @@ struct tx4938_ccfg_reg {
|
|||
#define TX4938_DMA_CSR_DESERR 0x00000002
|
||||
#define TX4938_DMA_CSR_SORERR 0x00000001
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
|
||||
#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
|
||||
#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
|
||||
#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
|
||||
#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
|
||||
#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
|
||||
#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
|
||||
#define tx4938_pcicptr tx4927_pcicptr
|
||||
#define tx4938_pcic1ptr \
|
||||
((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
|
||||
#define tx4938_ccfgptr \
|
||||
((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
|
||||
#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
|
||||
#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
|
||||
#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
|
||||
|
|
@ -612,17 +440,26 @@ struct tx4938_ccfg_reg {
|
|||
#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
|
||||
|
||||
|
||||
#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
|
||||
#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16)
|
||||
#define TX4938_REV_PCODE() \
|
||||
((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
|
||||
|
||||
#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
|
||||
#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
|
||||
#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
|
||||
|
||||
#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
|
||||
#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
|
||||
|
||||
#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)])
|
||||
#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
|
||||
#define TX4938_EBUSC_SIZE(ch) \
|
||||
(0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
|
||||
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
int tx4938_report_pciclk(void);
|
||||
void tx4938_report_pci1clk(void);
|
||||
int tx4938_pciclk66_setup(void);
|
||||
struct pci_dev;
|
||||
int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
|
||||
void tx4938_irq_init(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -7,8 +7,8 @@
|
|||
*
|
||||
* Copyright (C) 2000 Toshiba Corporation
|
||||
*/
|
||||
#ifndef __ASM_TXX927_H
|
||||
#define __ASM_TXX927_H
|
||||
#ifndef __ASM_TXX9_TXX927_H
|
||||
#define __ASM_TXX9_TXX927_H
|
||||
|
||||
struct txx927_sio_reg {
|
||||
volatile unsigned long lcr;
|
||||
|
|
@ -118,4 +118,4 @@ struct txx927_sio_reg {
|
|||
* PIO
|
||||
*/
|
||||
|
||||
#endif /* __ASM_TXX927_H */
|
||||
#endif /* __ASM_TXX9_TXX927_H */
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/*
|
||||
* include/asm-mips/vr41xx/cmbvr4133.h
|
||||
*
|
||||
* Include file for NEC CMB-VR4133.
|
||||
*
|
||||
* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
|
||||
* Jun Sun <jsun@mvista.com, or source@mvista.com> and
|
||||
* Alex Sapkov <asapkov@ru.mvista.com>
|
||||
*
|
||||
* 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __NEC_CMBVR4133_H
|
||||
#define __NEC_CMBVR4133_H
|
||||
|
||||
#include <asm/vr41xx/irq.h>
|
||||
|
||||
/*
|
||||
* General-Purpose I/O Pin Number
|
||||
*/
|
||||
#define CMBVR41XX_INTA_PIN 1
|
||||
#define CMBVR41XX_INTB_PIN 1
|
||||
#define CMBVR41XX_INTC_PIN 3
|
||||
#define CMBVR41XX_INTD_PIN 1
|
||||
#define CMBVR41XX_INTE_PIN 1
|
||||
|
||||
/*
|
||||
* Interrupt Number
|
||||
*/
|
||||
#define CMBVR41XX_INTA_IRQ GIU_IRQ(CMBVR41XX_INTA_PIN)
|
||||
#define CMBVR41XX_INTB_IRQ GIU_IRQ(CMBVR41XX_INTB_PIN)
|
||||
#define CMBVR41XX_INTC_IRQ GIU_IRQ(CMBVR41XX_INTC_PIN)
|
||||
#define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN)
|
||||
#define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN)
|
||||
|
||||
#define I8259A_IRQ_BASE 72
|
||||
#define I8259_IRQ(x) (I8259A_IRQ_BASE + (x))
|
||||
#define TIMER_IRQ I8259_IRQ(0)
|
||||
#define KEYBOARD_IRQ I8259_IRQ(1)
|
||||
#define I8259_SLAVE_IRQ I8259_IRQ(2)
|
||||
#define UART3_IRQ I8259_IRQ(3)
|
||||
#define UART1_IRQ I8259_IRQ(4)
|
||||
#define UART2_IRQ I8259_IRQ(5)
|
||||
#define FDC_IRQ I8259_IRQ(6)
|
||||
#define PARPORT_IRQ I8259_IRQ(7)
|
||||
#define RTC_IRQ I8259_IRQ(8)
|
||||
#define USB_IRQ I8259_IRQ(9)
|
||||
#define I8259_INTA_IRQ I8259_IRQ(10)
|
||||
#define AUDIO_IRQ I8259_IRQ(11)
|
||||
#define AUX_IRQ I8259_IRQ(12)
|
||||
#define IDE_PRIMARY_IRQ I8259_IRQ(14)
|
||||
#define IDE_SECONDARY_IRQ I8259_IRQ(15)
|
||||
|
||||
#endif /* __NEC_CMBVR4133_H */
|
||||
Loading…
Reference in a new issue