mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
This pull request contains Broadcom ARM/ARM64 based SoCs drivers changes for
4.16, please pull the following: - Arnd provides an update to the Raspberry Pi firmware interface and uses time64_t to print the time to make it more future proof - Florian provides a set of updates to make the Broadcom STB Bus Interface Unit code work on newer ARM64-based chips, as well as perform the correct interface tuning for these chips to reach the expected performance -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJaPE0dAAoJEIfQlpxEBwcEk/oQALjUzNWkipO31Ahx35r7kblW 4RC39ebaU31fR6yMOlKWQGh/uklHopcDuRQHAGR7IHg2MSr/uQ/xb7rgz4Qa1ZTD gRPcT9rI2mNctiWLFoB3EaYmA0J3EOMJI1GMIvHPGc3WZ5Y4FHKICW3qK7mvGndc obmiAU4mFyK31SKKm8k+TX6bzPsr1ZEm2tW9kRkWKfGk05DVD+KsKa5Xvn0USlS4 0jiXo+naHv5KtYXSuSc+Kg0qcCB3K2SFJVAOPgjTMzo498Vcv6mWLQPfGg3vDmCt 3rEiDhPoJJ6soAuG2OmHQCykTr0uwRZNhOc385JCKf8TP8CjV8aK71lJe0oFQgtg nC67z+uVLJ3tXoI1Y0V0DQXCTNLKgsbU19p14S+rDM2MQ41yGzWoVdT9ZhEDEbyj sDeC+d9DVQTuXqImqe16M3oZSsCWuMCRz0LG2uDhoTHMNmegU//nY6VhVR7ia0Ia BIDCsbNf1KEDEUi1v5nPJSNC2Oyk/mVOPzl8xwMdw3VV4eYggC9aqljmwDWWCxV5 GNCGbP/0UgKG6iUadqK2HM+0syRWA5E3ypWg8VPtU6g+lZKYqnh6g23F4lJklE1U WhKKK52OCRZ0w/ut2TWJmhpmn+CfR7VcVv9IS9zElBbyU/fg27Mkpu/Ty7bBx0my kmCDHOGHZyl4jrKhwxGg =RHHM -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-4.16/drivers' of http://github.com/Broadcom/stblinux into next/drivers This pull request contains Broadcom ARM/ARM64 based SoCs drivers changes for 4.16, please pull the following: - Arnd provides an update to the Raspberry Pi firmware interface and uses time64_t to print the time to make it more future proof - Florian provides a set of updates to make the Broadcom STB Bus Interface Unit code work on newer ARM64-based chips, as well as perform the correct interface tuning for these chips to reach the expected performance * tag 'arm-soc/for-4.16/drivers' of http://github.com/Broadcom/stblinux: soc: brcmstb: biuctrl: Move to early_initcall soc: brcmstb: Split initialization soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings soc: brcmstb: biuctrl: Wire-up new registers soc: brcmstb: biuctrl: Prepare for saving/restoring other registers soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs soc: brcmstb: Make CPU credit offset more parameterized dt-bindings: arm: brcmstb: Correct BIUCTRL node documentation dt-bindings: arm: Add entry for Broadcom Brahma-B53 firmware: raspberrypi: print time using time64_t Signed-off-by: Olof Johansson <[email protected]>
This commit is contained in:
Olof Johansson
commit
7e32c6054e
7 changed files with 187 additions and 49 deletions
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@ -21,11 +21,70 @@
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#include <linux/syscore_ops.h>
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#include <linux/soc/brcmstb/brcmstb.h>
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#define CPU_CREDIT_REG_OFFSET 0x184
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#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
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#define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf
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#define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf
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#define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8)
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#define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4)
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#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8)
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#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff
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#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf
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#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf
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#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4
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#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8)
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static void __iomem *cpubiuctrl_base;
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static bool mcp_wr_pairing_en;
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static const int *cpubiuctrl_regs;
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static inline u32 cbc_readl(int reg)
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{
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int offset = cpubiuctrl_regs[reg];
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if (offset == -1)
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return (u32)-1;
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return readl_relaxed(cpubiuctrl_base + offset);
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}
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static inline void cbc_writel(u32 val, int reg)
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{
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int offset = cpubiuctrl_regs[reg];
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if (offset == -1)
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return;
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writel_relaxed(val, cpubiuctrl_base + offset);
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}
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enum cpubiuctrl_regs {
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CPU_CREDIT_REG = 0,
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CPU_MCP_FLOW_REG,
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CPU_WRITEBACK_CTRL_REG
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};
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static const int b15_cpubiuctrl_regs[] = {
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[CPU_CREDIT_REG] = 0x184,
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[CPU_MCP_FLOW_REG] = -1,
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[CPU_WRITEBACK_CTRL_REG] = -1,
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};
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/* Odd cases, e.g: 7260 */
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static const int b53_cpubiuctrl_no_wb_regs[] = {
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[CPU_CREDIT_REG] = 0x0b0,
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[CPU_MCP_FLOW_REG] = 0x0b4,
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[CPU_WRITEBACK_CTRL_REG] = -1,
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};
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static const int b53_cpubiuctrl_regs[] = {
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[CPU_CREDIT_REG] = 0x0b0,
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[CPU_MCP_FLOW_REG] = 0x0b4,
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[CPU_WRITEBACK_CTRL_REG] = 0x22c,
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};
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#define NUM_CPU_BIUCTRL_REGS 3
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static int __init mcp_write_pairing_set(void)
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{
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@ -34,15 +93,15 @@ static int __init mcp_write_pairing_set(void)
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if (!cpubiuctrl_base)
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return -1;
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creds = readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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creds = cbc_readl(CPU_CREDIT_REG);
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if (mcp_wr_pairing_en) {
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pr_info("MCP: Enabling write pairing\n");
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writel_relaxed(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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CPU_CREDIT_REG);
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} else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
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pr_info("MCP: Disabling write pairing\n");
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writel_relaxed(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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CPU_CREDIT_REG);
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} else {
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pr_info("MCP: Write pairing already disabled\n");
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}
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@ -50,9 +109,62 @@ static int __init mcp_write_pairing_set(void)
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return 0;
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}
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static const u32 b53_mach_compat[] = {
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0x7268,
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0x7271,
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0x7278,
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};
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static void __init mcp_b53_set(void)
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{
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unsigned int i;
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u32 reg;
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reg = brcmstb_get_family_id();
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for (i = 0; i < ARRAY_SIZE(b53_mach_compat); i++) {
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if (BRCM_ID(reg) == b53_mach_compat[i])
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break;
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}
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if (i == ARRAY_SIZE(b53_mach_compat))
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return;
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/* Set all 3 MCP interfaces to 8 credits */
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reg = cbc_readl(CPU_CREDIT_REG);
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for (i = 0; i < 3; i++) {
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reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
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CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
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reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
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CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
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reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
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reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
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}
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cbc_writel(reg, CPU_CREDIT_REG);
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/* Max out the number of in-flight Jwords reads on the MCP interface */
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reg = cbc_readl(CPU_MCP_FLOW_REG);
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for (i = 0; i < 3; i++)
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reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
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CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
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cbc_writel(reg, CPU_MCP_FLOW_REG);
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/* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
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* threshold
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*/
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reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
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reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
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reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
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reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
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CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
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reg |= 8;
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reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
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cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
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}
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static int __init setup_hifcpubiuctrl_regs(void)
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{
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struct device_node *np;
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struct device_node *np, *cpu_dn;
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int ret = 0;
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np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
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@ -69,27 +181,56 @@ static int __init setup_hifcpubiuctrl_regs(void)
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}
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mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
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cpu_dn = of_get_cpu_node(0, NULL);
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if (!cpu_dn) {
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pr_err("failed to obtain CPU device node\n");
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ret = -ENODEV;
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goto out;
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}
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if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
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cpubiuctrl_regs = b15_cpubiuctrl_regs;
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else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
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cpubiuctrl_regs = b53_cpubiuctrl_regs;
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else {
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pr_err("unsupported CPU\n");
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ret = -EINVAL;
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}
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of_node_put(cpu_dn);
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if (BRCM_ID(brcmstb_get_family_id()) == 0x7260)
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cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
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out:
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of_node_put(np);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static u32 cpu_credit_reg_dump; /* for save/restore */
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static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];
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static int brcmstb_cpu_credit_reg_suspend(void)
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{
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if (cpubiuctrl_base)
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cpu_credit_reg_dump =
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readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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unsigned int i;
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if (!cpubiuctrl_base)
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return 0;
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for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
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cpubiuctrl_reg_save[i] = cbc_readl(i);
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return 0;
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}
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static void brcmstb_cpu_credit_reg_resume(void)
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{
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if (cpubiuctrl_base)
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writel_relaxed(cpu_credit_reg_dump,
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cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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unsigned int i;
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if (!cpubiuctrl_base)
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return;
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for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
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cbc_writel(cpubiuctrl_reg_save[i], i);
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}
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static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
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#endif
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void __init brcmstb_biuctrl_init(void)
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static int __init brcmstb_biuctrl_init(void)
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{
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int ret;
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@ -108,10 +249,13 @@ void __init brcmstb_biuctrl_init(void)
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ret = mcp_write_pairing_set();
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if (ret) {
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pr_err("MCP: Unable to disable write pairing!\n");
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return;
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return ret;
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}
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mcp_b53_set();
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#ifdef CONFIG_PM_SLEEP
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register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
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#endif
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return 0;
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}
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early_initcall(brcmstb_biuctrl_init);
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@ -66,13 +66,10 @@ static const struct of_device_id sun_top_ctrl_match[] = {
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{ }
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};
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static int __init brcmstb_soc_device_init(void)
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static int __init brcmstb_soc_device_early_init(void)
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{
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struct soc_device_attribute *soc_dev_attr;
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struct soc_device *soc_dev;
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struct device_node *sun_top_ctrl;
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void __iomem *sun_top_ctrl_base;
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int ret = 0;
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sun_top_ctrl = of_find_matching_node(NULL, sun_top_ctrl_match);
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if (!sun_top_ctrl)
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@ -84,12 +81,19 @@ static int __init brcmstb_soc_device_init(void)
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family_id = readl(sun_top_ctrl_base);
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product_id = readl(sun_top_ctrl_base + 0x4);
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iounmap(sun_top_ctrl_base);
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return 0;
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}
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early_initcall(brcmstb_soc_device_early_init);
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static int __init brcmstb_soc_device_init(void)
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{
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struct soc_device_attribute *soc_dev_attr;
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struct soc_device *soc_dev;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr) {
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ret = -ENOMEM;
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goto out;
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}
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if (!soc_dev_attr)
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return -ENOMEM;
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soc_dev_attr->family = kasprintf(GFP_KERNEL, "%x",
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family_id >> 28 ?
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@ -107,14 +111,9 @@ static int __init brcmstb_soc_device_init(void)
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kfree(soc_dev_attr->soc_id);
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kfree(soc_dev_attr->revision);
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kfree(soc_dev_attr);
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ret = -ENODEV;
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goto out;
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return -ENOMEM;
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}
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return 0;
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out:
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iounmap(sun_top_ctrl_base);
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return ret;
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}
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arch_initcall(brcmstb_soc_device_init);
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