A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-zynq' into clk-next

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- Various static analysis fixes/finds
 - Video Engine (ECLK) support on Aspeed SoCs
 - Xilinx ZynqMP Versal platform support
 - Convert Xilinx ZynqMP driver to be struct oriented

* clk-sa:
  clk: mvebu: fix spelling mistake "gatable" -> "gateable"
  clk: ux500: add range to usleep_range
  clk: tegra: Make tegra_clk_super_mux_ops static
  clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5

* clk-aspeed:
  clk: Aspeed: Setup video engine clocking

* clk-samsung:
  clk: samsung: exynos5410: Add gate clock for ADC
  clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410
  clk: samsung: dt-bindings: Put CLK_UART3 in order

* clk-ingenic:
  clk: ingenic: jz4725b: Add UDC PHY clock
  dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock

* clk-zynq:
  clk: zynqmp: use structs for clk query responses
  clk: zynqmp: fix check for fractional clock
  clk: zynqmp: do not export zynqmp_clk_register_* functions
  clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents
  drivers: clk: Update clock driver to handle clock attribute
  drivers: clk: zynqmp: Allow zero divisor value
This commit is contained in:
Stephen Boyd 2019-05-07 11:44:56 -07:00
commit 7e9c62bdb4
14 changed files with 181 additions and 91 deletions
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3
include/dt-bindings/clock/exynos5410.h
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@ -36,6 +36,7 @@
#define CLK_UART0 257
#define CLK_UART1 258
#define CLK_UART2 259
#define CLK_UART3 260
#define CLK_I2C0 261
#define CLK_I2C1 262
#define CLK_I2C2 263
@ -44,7 +45,7 @@
#define CLK_USI1 266
#define CLK_USI2 267
#define CLK_USI3 268
#define CLK_UART3 260
#define CLK_TSADC 270
#define CLK_PWM 279
#define CLK_MCT 315
#define CLK_WDT 316

1
include/dt-bindings/clock/jz4725b-cgu.h
View file

@ -31,5 +31,6 @@
#define JZ4725B_CLK_TCU 22
#define JZ4725B_CLK_EXT512 23
#define JZ4725B_CLK_RTC 24
#define JZ4725B_CLK_UDC_PHY 25
#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */