A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-28 18:51:56 -04:00
Code Issues Projects Releases Packages Wiki Activity

Linux 4.10-rc6

Browse source 
-----BEGIN PGP SIGNATURE-----
 
 iQEcBAABAgAGBQJYjmvUAAoJEHm+PkMAQRiGHIoH/3VaTj7cCJZDnWZ2Wi2enWip
 f17zj0oAkFxuSx8XEVD5BKqMfGBCBjPNPwURysfcFVoSHNtHjbEr44VxiPfQj5s2
 N+znVm5P9qlFuRA+7dgYUyEKOqcTgyT9jFNpvPF6bgMZDfJoB/wo53UU4lo3drcx
 cRe6OT4fEpAbtgbl73kIjOreBRr7oxlMPVEjCVRdL7ssCg+iqow0MEHcSoO7jmtj
 tu8hwwBMNh5B0yJRCJKV7Edc1+GHK57ju6rnGr5S2rwnR31omLpvnHJx0Ya6NVCZ
 yV3KGQeWm13ifbumMddEnAL61x2hOIzX//BqaZKdy258YPohkNtD8oacnjHnLMc=
 =5Rs+
 -----END PGP SIGNATURE-----

Merge tag 'v4.10-rc6' into devel

Linux 4.10-rc6

Resolved conflicts in:
	drivers/pinctrl/pinctrl-amd.c
	drivers/pinctrl/samsung/pinctrl-exynos.c
This commit is contained in:
Linus Walleij 2017-01-30 14:39:20 +01:00
commit 7f36f5d11c
1081 changed files with 10656 additions and 6340 deletions
Download patch file Download diff file Expand all files Collapse all files

39
drivers/pinctrl/intel/pinctrl-baytrail.c
View file

@ -1092,6 +1092,7 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
enum pin_config_param param = pinconf_to_config_param(*config);
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
unsigned long flags;
u32 conf, pull, val, debounce;
u16 arg = 0;
@ -1128,7 +1129,7 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
return -EINVAL;
raw_spin_lock_irqsave(&vg->lock, flags);
debounce = readl(byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG));
debounce = readl(db_reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
@ -1176,6 +1177,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
unsigned int param, arg;
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
unsigned long flags;
u32 conf, val, debounce;
int i, ret = 0;
@ -1238,36 +1240,40 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
debounce = readl(byt_gpio_reg(vg, offset,
BYT_DEBOUNCE_REG));
conf &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce = readl(db_reg);
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
switch (arg) {
case 0:
conf &= BYT_DEBOUNCE_EN;
break;
case 375:
conf |= BYT_DEBOUNCE_PULSE_375US;
debounce |= BYT_DEBOUNCE_PULSE_375US;
break;
case 750:
conf |= BYT_DEBOUNCE_PULSE_750US;
debounce |= BYT_DEBOUNCE_PULSE_750US;
break;
case 1500:
conf |= BYT_DEBOUNCE_PULSE_1500US;
debounce |= BYT_DEBOUNCE_PULSE_1500US;
break;
case 3000:
conf |= BYT_DEBOUNCE_PULSE_3MS;
debounce |= BYT_DEBOUNCE_PULSE_3MS;
break;
case 6000:
conf |= BYT_DEBOUNCE_PULSE_6MS;
debounce |= BYT_DEBOUNCE_PULSE_6MS;
break;
case 12000:
conf |= BYT_DEBOUNCE_PULSE_12MS;
debounce |= BYT_DEBOUNCE_PULSE_12MS;
break;
case 24000:
conf |= BYT_DEBOUNCE_PULSE_24MS;
debounce |= BYT_DEBOUNCE_PULSE_24MS;
break;
default:
ret = -EINVAL;
}
if (!ret)
writel(debounce, db_reg);
break;
default:
ret = -ENOTSUPP;
@ -1617,6 +1623,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
{
struct gpio_chip *gc = &vg->chip;
struct device *dev = &vg->pdev->dev;
void __iomem *reg;
u32 base, value;
int i;
@ -1638,10 +1646,12 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
}
value = readl(reg);
if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
!(value & BYT_DIRECT_IRQ_EN)) {
if (value & BYT_DIRECT_IRQ_EN) {
clear_bit(i, gc->irq_valid_mask);
dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
byt_gpio_clear_triggering(vg, i);
dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
dev_dbg(dev, "disabling GPIO %d\n", i);
}
}
@ -1680,6 +1690,7 @@ static int byt_gpio_probe(struct byt_gpio *vg)
gc->can_sleep = false;
gc->parent = &vg->pdev->dev;
gc->ngpio = vg->soc_data->npins;
gc->irq_need_valid_mask = true;
#ifdef CONFIG_PM_SLEEP
vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,

2
drivers/pinctrl/intel/pinctrl-broxton.c
View file

@ -19,7 +19,7 @@
#define BXT_PAD_OWN 0x020
#define BXT_HOSTSW_OWN 0x080
#define BXT_PADCFGLOCK 0x090
#define BXT_PADCFGLOCK 0x060
#define BXT_GPI_IE 0x110
#define BXT_COMMUNITY(s, e) \

30
drivers/pinctrl/intel/pinctrl-intel.c
View file

@ -353,6 +353,21 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
return 0;
}
static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
{
u32 value;
value = readl(padcfg0);
if (input) {
value &= ~PADCFG0_GPIORXDIS;
value |= PADCFG0_GPIOTXDIS;
} else {
value &= ~PADCFG0_GPIOTXDIS;
value |= PADCFG0_GPIORXDIS;
}
writel(value, padcfg0);
}
static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned pin)
@ -375,11 +390,11 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
/* Disable SCI/SMI/NMI generation */
value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
/* Disable TX buffer and enable RX (this will be input) */
value &= ~PADCFG0_GPIORXDIS;
value |= PADCFG0_GPIOTXDIS;
writel(value, padcfg0);
/* Disable TX buffer and enable RX (this will be input) */
__intel_gpio_set_direction(padcfg0, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
@ -392,18 +407,11 @@ static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
void __iomem *padcfg0;
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&pctrl->lock, flags);
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
value = readl(padcfg0);
if (input)
value |= PADCFG0_GPIOTXDIS;
else
value &= ~PADCFG0_GPIOTXDIS;
writel(value, padcfg0);
__intel_gpio_set_direction(padcfg0, input);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);

7
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
View file

@ -257,9 +257,8 @@ static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) };
static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) };
static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) };
static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) };
static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_0, 0) };
static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_1, 0),
PIN(GPIOAO_5, 0) };
static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_4, 0) };
static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_5, 0) };
static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) };
static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) };
@ -507,7 +506,7 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
GPIO_GROUP(GPIOAO_13, 0),
/* bank AO */
GROUP(uart_tx_ao_b, 0, 26),
GROUP(uart_tx_ao_b, 0, 24),
GROUP(uart_rx_ao_b, 0, 25),
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),

7
drivers/pinctrl/meson/pinctrl-meson-gxl.c
View file

@ -218,9 +218,8 @@ static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) };
static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) };
static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) };
static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) };
static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_0, 0) };
static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_1, 0),
PIN(GPIOAO_5, 0) };
static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_4, 0) };
static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_5, 0) };
static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) };
static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) };
@ -420,7 +419,7 @@ static struct meson_pmx_group meson_gxl_aobus_groups[] = {
GPIO_GROUP(GPIOAO_9, 0),
/* bank AO */
GROUP(uart_tx_ao_b, 0, 26),
GROUP(uart_tx_ao_b, 0, 24),
GROUP(uart_rx_ao_b, 0, 25),
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),

2
drivers/pinctrl/meson/pinctrl-meson.c
View file

@ -212,7 +212,7 @@ static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1);
meson_pmx_disable_other_groups(pc, offset, -1);
return 0;
}

19
drivers/pinctrl/pinctrl-amd.c
View file

@ -400,26 +400,21 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
int ret = 0;
u32 pin_reg;
unsigned long flags;
bool level_trig;
u32 active_level;
unsigned long flags, irq_flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
/*
* When level_trig is set EDGE and active_level is set HIGH in BIOS
* default settings, ignore incoming settings from client and use
* BIOS settings to configure GPIO register.
/* Ignore the settings coming from the client and
* read the values from the ACPI tables
* while setting the trigger type
*/
level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF));
active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
if(level_trig &&
((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH))
type = IRQ_TYPE_EDGE_FALLING;
irq_flags = irq_get_trigger_type(d->irq);
if (irq_flags != IRQ_TYPE_NONE)
type = irq_flags;
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:

11
drivers/pinctrl/samsung/pinctrl-exynos.c
View file

@ -60,6 +60,17 @@ static const struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
.fld_width = { 4, 1, 2, 4, 2, 2, },
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
};
static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
.fld_width = { 4, 1, 2, 4, },
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
static void exynos_irq_mask(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);

31
drivers/pinctrl/samsung/pinctrl-exynos.h
View file

@ -90,6 +90,37 @@
.pctl_res_idx = pctl_idx, \
} \
#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
{ \
.type = &exynos5433_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
{ \
.type = &exynos5433_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
{ \
.type = &exynos5433_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.name = id, \
.pctl_res_idx = pctl_idx, \
} \
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.

2
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
View file

@ -561,7 +561,7 @@ static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0};
static const unsigned ether_rmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 39,
41, 42, 45};
static const int ether_rmii_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
static const unsigned i2c0_pins[] = {63, 64};
static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {65, 66};